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AboutUs
PavelKryukov edited this page Sep 30, 2015
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Purpose of the project is to create light version of functional and clock-precise simulators of a microprocessor optimized for digital signal processing (DSP).
This project is a part of Intel Lab activity at Moscow Institute of Physics and Technology (MIPT).
Our team consists of a group of students of MIPT and mentors who supervise and direct the team's operation.
| Photo | Name (en) | Name (ru) | |
|---|---|---|---|
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Grigory Rechistov | Григорий Речистов | grigory.rechistov@gmail.com |
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Alexander Titov | Александр Титов | alexander.igorevich.titov@gmail.com |
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Yuri Baida | Юрий Бáйда | yuri.baida@gmail.com |
| Photo | Name (en) | Name (ru) | |
|---|---|---|---|
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Alexey Ahnevsky | Ахневский Алексей | aleksey.ahnevskiy@gmail.com |
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Boris Belousov | Борис Белоусов | plim.the.best@gmail.com |
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Sergey Gvozdaryev | Гвоздарев Сергей | gvozdarev.sa@gmail.com |
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Arthur Gilmullin | Гильмуллин Артур | agilmullin@gmail.com |
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Vladimir Dubihin | Дубихин Владимир | vladimir.dubihin@gmail.com |
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Stanislav Elizarov | Елизаров Станислав | el.stas@gmail.com |
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Pavel Kryukov | Крюков Павел | kryukov@frtk.ru |
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Alexander Kurilovich | Курилович Александр | akurae@mail.ru |
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Alexander Maramzin | Марамзин Александр | - |
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Artemije Margaritov | Маргаритов Артемий | margarty.frtk@gmail.com |
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Boris Stepanenko | Степаненко Борис | stepanenkoat@gmail.com |
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Nazary Tupitsa | Тупица Назарий | two.nazya@gmail.com |
- About us
- HOWTO
- Design
- Instruction set architecture (ISA)
- Functional simulation
-
Performance simulation
- Infrastructure
- Module Structure
- Clocking
- Ports
- Logs
- Stats
- Configuration
- Hardware features
- Infrastructure
- Implementation
- Coding style
- Functional simulation
- Performance simulation
- Infrastructure
- Module structure
- Clocking
- Ports
- Logs
- Stats
- Configuration
- Hardware features
- Infrastructure
- Quality assurance
- Simmy Specification
- FAQ
- BKM














