This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring smooth vehicle movement at intersections through an efficient state-based control mechanism.
- Key Features:
- State Machine Design: Implements a finite state machine (FSM) to manage traffic light transitions. Includes states for Red, Yellow, and Green lights with precise timing.
- Simulation: Functional and timing simulation performed using Xilinx Vivado or equivalent tools. Verified output waveforms for light transitions.
- Parameters: Configurable timing for each light state. Priority handling for emergency or pedestrian signals.
- Fault Tolerance: Built-in error detection for unexpected states.
- Tools Used: Verilog for RTL design. Xilinx Vivado/NCSim for synthesis and simulation.
- Applications: Traffic management systems for intersections. Can be extended for multi-junction or adaptive traffic systems.