System-Verilog

These are system verilog HDL files created for ELM264 Logic Circuits and Desing Laboratory Course at Gebze Technical University.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
.gitattributes		.gitattributes
LICENSE		LICENSE
README.md		README.md
internalsig.sv		internalsig.sv
internalsig_tb.sv		internalsig_tb.sv
labb1.sv		labb1.sv
labb1_tb.sv		labb1_tb.sv
labbb.sv		labbb.sv
labbb_tb.sv		labbb_tb.sv

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