This repository contains Verilog/C projects with Tang Nano (4K/9K/20K) and Zybo Z7.
The core of this project is a UART module that receives and transmits data asynchronously. I've built upon the original tutorial by adding custom Verilog code that enables LED blinking patterns triggered by specific serial inputs.
- Character-based LED Control: The FPGA can receive 'A', 'B', or 'C' to trigger different LED blinking patterns.
- Sequence-based LED Control: A more complex implementation where a specific sequence of characters ('ABC') must be received to trigger the LEDs.
- State Diagrams: The logic for these contributions is visually documented with state diagrams, which can be found in the project's
README.md.
You can find the project files and detailed explanations in the UART directory.
| Project | Description | Hardware | Toolchain | Links |
|---|---|---|---|---|
| vivado | Baremetal Software project with Vivado/Vitis and Zybo Z7 mainly with C. Find various implementations of C for LED-BTN combinations with randomness and different blinking periods. | π Tutorial | ||
| fpga_project | Several simple implementations for Tang Nano 9K: original blinky, simple functions with Verilog, pseudo randomness with LSFR, pseudo random with state, calculation that takes random input and defines a LED, and an attempt to implement constraints and initial logic for Travelling Salesman Problem with Verilog. | π Tutorial π» Code |
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| picotiny | A PicoRV32-based SoC with HDMI terminal, SPI Flash XIP, and custom UART ISP for flash programming. The hardware includes PicoRV32, spimemio, and SimpleVOut modules, with address mapping for various peripherals. The firmware, built with dependencies like python, pyserial, and RISC-V GCC, enables flashing user firmware via ISP and features a UART terminal with LED toggling and flash mode configuration. | π Tutorial π» Code |
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| camera_hdmi | Contains interface, controller, registers, memory interface, synthesis generation and other necessary components for Tang Nano 4K with OV2640 camera. Video is sent to HDMI out and can be displayed on the screen. | π» Code | ||
| UART | A UART module that receives and transmits data asynchronously. It implements state machines for both receiving and transmitting data, with control logic to manage timing and data flow. My modifications include Verilog for receiving A,B, or C to make LEDs blink. And another version that receives a sequence ABC and then makes LEDs blink. | π Tutorial π» Code |
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| screen | A text engine for rendering text on an OLED display was developed. It involves mapping character codes to screen pixel positions, using pre-defined font bitmaps to convert characters to pixels, and generating the pixel data for displaying text dynamically on the display. | π Tutorial π» Code |
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| screen_text | A text engine was developed to dynamically render text onto an OLED screen using pre-defined font bitmaps and mapping character positions to screen pixel addresses. The engine allows for displaying specific characters or strings by initializing memory buffers representing rows of text. | π Tutorial | ||
| screen_data | The Verilog files define the logic of an FPGA design for displaying text on a screen and handling serial communication. The top.v file serves as the top-level module, text.v generates the text to be displayed, screen.v controls the overall display, uart.v manages serial communication with a computer, and rows.v ensures correct row scanning on the screen. | π Tutorial π» Code |
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| flash | This project covers the use of external flash in Tang Nano 9K FPGA board. | π Tutorial π» Code |
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| lfsr | This project creates pseudo random numbers with Linear Feedback Shift Register and visualizes them on OLED screen as bars of different size. | π Tutorial π» Code |
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| arbiter | This project covers sharing of common resources in one FPGA board. | π Tutorial π» Code |
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| ads1115_adc | This project uses analog signal converter and visualizes the data. | π Tutorial π» Code |
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| cpu | This project creates a CPU with FPGA and several programs on top of it. Simple blinking and button click and counting are now done on top of FPGA-based CPU with node. | π Tutorial π» Code |