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Kiran-VLSI/README.md

Hi, I'm Chandrakiran G 👋

🌱 Currently learning: SystemVerilog and UVM
📫 Reach me: gchandrakiran97@gmail.com • 🔗 LinkedIn

What I’m up to

  • Designing UVM testbenches (agents, drivers, monitors, sequences, scoreboards)
  • Exploring SystemVerilog Assertions (SVA) for functional coverage
  • Practicing DSA for problem-solving & coding interviews
  • Learning FPGA prototyping with Vivado

Tech I use

  • HDL/Verification: Verilog, SystemVerilog, UVM
  • EDA Tools: Cadence, ModelSim, Synopsys, Vivado, LTspice
  • FPGA Tools: Xilinx Vivado
  • Scripting: Python, TCL
  • Version Control: Git, GitHub

Pinned Loading

  1. FPGA-Prototyping FPGA-Prototyping Public

  2. Verilog-30-Days-Challenge Verilog-30-Days-Challenge Public

  3. VLSI_Projects VLSI_Projects Public

  4. Kiran-VLSI-100-days-RTL-Design-Challenge Kiran-VLSI-100-days-RTL-Design-Challenge Public

    100 RTL Challenge 🚀🎛️ Designing and verifying RTL modules daily for 100 days! 🎯 📂 Includes: Verilog,testbenches, and synthesis results. ⚙️ Tools: Cadence,Xilinx Vivado. 💡 Goal: Master RTL design! 🏆

    Verilog 1

  5. Idkwat55/I2C-Testbench Idkwat55/I2C-Testbench Public

    PostScript 1

  6. Synopsys-VLSI-RCA-ALU Synopsys-VLSI-RCA-ALU Public

    VLSI design and analysis of an 8-bit Ripple Carry Adder and a 32-bit ALU using Synopsys EDA tools includes RTL design, synthesis (DC), simulation (VCS), and timing analysis (PrimeTime).

    Verilog 1