Single-Cycle-RISC-V

This is a basic single cycle risc-v RV32I implementation meant for learning purposes. Programmed in verilog and simulated in modelsim.

Architecture

addi x1, x0, 1
addi x2, x0, 2
add x3, x1, x2
sw x3, 0(x0)
addi x3, x3, -1
bne x3, x0, -4
xor x3, x2, x0
jal x1, -28

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
.gitignore		.gitignore
.project		.project
README.md		README.md
alu.v		alu.v
alu_control.v		alu_control.v
branch_decider.v		branch_decider.v
control.v		control.v
decoder.v		decoder.v
defines.v		defines.v
imm_gen.v		imm_gen.v
inst		inst
mux_2.v		mux_2.v
mux_4.v		mux_4.v
ram.v		ram.v
reg_file.v		reg_file.v
riscv_core.v		riscv_core.v
riscv_core_tb.v		riscv_core_tb.v
rom.v		rom.v