- π Hi, Iβm @Jawwaad-analyst
- π§© Interests: VLSI β’ Embedded Systems β’ Cybersecurity β’ Machine Learning β’ Data
- π Currently learning: RISC-V | Data Science | ML | Verilog | C | DSA
- π Projects: DWT-SVD Watermarking β’ RISC-V CPU on Verilog (rv32i) β’ Chatbot β’ DSP Mini Projects
- π― Goals: Master VLSI & Embedded + Become strong in Cyber-Sec + Build ML Projects
- π Degree: Electronics & Communication Engineering (ECE)
- πΌ Areas I enjoy: Hardware + Software + Security + Data
- π¬ Fun fact: I love learning new things related to tech, fitness & cybersecurity
- πͺ Outside tech: Fitness, weightlifting & nutrition ποΈββοΈ
Popular repositories Loading
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eSim
eSim PublicForked from FOSSEE/eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Python
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core-v-verif
core-v-verif PublicForked from openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Assembly
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