Skip to content
View Jawwaad-analyst's full-sized avatar

Block or report Jawwaad-analyst

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Jawwaad-analyst/README.md
  • πŸ‘‹ Hi, I’m @Jawwaad-analyst
  • 🧩 Interests: VLSI β€’ Embedded Systems β€’ Cybersecurity β€’ Machine Learning β€’ Data
  • πŸ”­ Currently learning: RISC-V | Data Science | ML | Verilog | C | DSA
  • πŸš€ Projects: DWT-SVD Watermarking β€’ RISC-V CPU on Verilog (rv32i) β€’ Chatbot β€’ DSP Mini Projects
  • 🎯 Goals: Master VLSI & Embedded + Become strong in Cyber-Sec + Build ML Projects
  • πŸŽ“ Degree: Electronics & Communication Engineering (ECE)
  • πŸ’Ό Areas I enjoy: Hardware + Software + Security + Data
  • πŸ’¬ Fun fact: I love learning new things related to tech, fitness & cybersecurity
  • πŸ’ͺ Outside tech: Fitness, weightlifting & nutrition πŸ‹οΈβ€β™‚οΈ

Popular repositories Loading

  1. Jawwaad-analyst Jawwaad-analyst Public

    Config files for my GitHub profile.

  2. E-Yantra E-Yantra Public

    first repository

    HTML

  3. eSim eSim Public

    Forked from FOSSEE/eSim

    This repository contain source code for new flow of FreeEDA now know as eSim

    Python

  4. core-v-verif core-v-verif Public

    Forked from openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly

  5. Risc-v-Hades Risc-v-Hades Public

    Hades challenge submission

    SystemVerilog