Low-Level Hardware Design Systems II

Project for the course Low-level Hardware Design Systems II, 2024-25 ECE AUTH

Objective

Design and verify a single-precision IEEE-754 floating-point multiplier in SystemVerilog. The project implements a pipelined multiplier with normalization, rounding, and exception handling, and verifies it using a SystemVerilog testbench and SystemVerilog Assertions (SVA).
For more detailed explanations, see the full report (in Greek).

Tools & Technologies

Programming Languages: SystemVerilog
Tools: Questa*-Intel® FPGA Edition