Low-Level Hardware Design Systems I

Project for the course Low-Level Hardware Design Systems I, 2024-25 ECE AUTH

Objective

The project implements a RISC-V processor, including RTL design, testbenches, and simulation outputs.
For more detailed explanations, see the full report (in Greek).

Tools & Technologies

• Programming Languages: Verilog
• Other Tools: Icarus Verilog (Simulation), GTKWave (waveform visualization)