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DaisyDrive64 detection and DaisyDrive64 special feature support. #15

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0599a61
Cx4 passthrough implementation
nopjne Aug 22, 2023
9b6ac2b
Expose DaisyDrive64 support as a runtime check
nopjne Jun 24, 2024
ef83449
Copy the RDRAM to Cart space on DaisyDrive64 on the reset interrupt
nopjne Aug 7, 2024
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9 changes: 9 additions & 0 deletions src/defines.h
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Original file line number Diff line number Diff line change
Expand Up @@ -201,3 +201,12 @@

// Macro that converts an RSP DMEM address to a CPU address
#define DMEM(addr) (0xA4000000 + (addr))

// ROM base offset
#define DEFAULT_ROM_BASE 0x10200000

// DaisyDrive feature bits
#define DD64_FEATURE_BITS_NONE 0x00000000
#define DD64_FEATURE_BITS_SD_ACCESS 0x00000001
#define DD64_FEATURE_BITS_CX4_SUPPORT 0x00000002
#define DD64_FEATURE_BITS_DSP1_SUPPORT 0x00000004
85 changes: 83 additions & 2 deletions src/main.S
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@
.globl fps_emulate
.globl fps_display
.globl frame_count

.globl _start

.data
Expand Down Expand Up @@ -113,8 +112,69 @@ clear_vram:
cache 0x10, 0x0100(t0)
cache 0x10, 0x0180(t0)

// Check for Cartridge Emulator support
lui t0, 0xA900 // PI register upper address
lw t1, 0x0220(t0) // DaisyDrive64 MagicID
bne t1, 0x44443634, dom2_signal_speed_init // 0x44443634 == DD64 ascii
daisydrive_init:
lw t1, 0x0224(t0) // DaisyDrive64 Emulation settings
andi t2, t1, DD64_FEATURE_BITS_CX4_SUPPORT
beqz t2, DSP1_support

// Check what features are enabled: CX4, DSP1, etc.
// Patch appropriate IO functions.
li t3, (0x7FB0 - 0x2100)
la t4, read_extension
la t5, write_extension
patch_CX4_passthrough_region:
la t2, read_iomap
mul t6, t3, 4
add t2, t6
sw t4, 0x0(t2)
la t2, write_iomap
add t2, t6
sw t5, 0x0(t2)
addi t3, t3, -1
bne t3, (0x5FFF - 0x2100), patch_CX4_passthrough_region

DSP1_support:
lw t1, 0x0224(t0)
andi t2, t1, DD64_FEATURE_BITS_DSP1_SUPPORT
beqz t2, ROM_BaseAddress
// TODO -- DSP 1 support is still being worked on

// Check the rom start address set by the menu.
// Patch the start address opcodes.
ROM_BaseAddress:
lw t1, 0x0228(t0) // DaisyDrive64 VM rom address (Set by the menu)
sw t1, rom_base_address

// Daisy drive specific DOM2 signal speed.
lui t0, 0xA460 // PI register upper address
li t1, 0x06
sw t1, 0x0024(t0) // LAT
li t1, 0x0B
sw t1, 0x0028(t0) // PWD
li t1, 0x05
sw t1, 0x002C(t0) // PGS
li t1, 0x03
sw t1, 0x0030(t0) // RLS
j sram_init

dom2_signal_speed_init:
// Setup SRAM signal speed to something consistent but safe.
lui t0, 0xA460 // PI register upper address
li t1, 0x06
sw t1, 0x0024(t0) // LAT
li t1, 0x0B
sw t1, 0x0028(t0) // PWD
li t1, 0x07
sw t1, 0x002C(t0) // PGS
li t1, 0x03
sw t1, 0x0030(t0) // RLS

sram_init:
// Use DMA to copy SRAM from the cart to memory
lui t0, 0xA460 // PI register upper address
la t1, sram // Local SRAM
sw t1, 0x0000(t0) // PI_DRAM_ADDR
li t1, 0x08000000 // Cart SRAM
Expand Down Expand Up @@ -283,6 +343,27 @@ reset_interrupt:
li t0, 0x00000001 // Use RDRAM
sw t0, 0xA410000C // DP_STATUS

// Check if running on DaisyDrive64
lui t0, 0xA900 // PI register upper address
lw t1, 0x0220(t0) // DaisyDrive64 MagicID
bne t1, 0x44443634, loop // 0x44443634 == DD64 ascii

// On DaisyDrive64 - DMA the entire RAM to a location in empty cartridge space. (0xb0800000)
// This can be used for debugging.
lui k0, 0xA460 // PI register upper address
la k1, 0x00000000 // RDRAM base address. 0x0
sw k1, 0x0000(k0) // PI_DRAM_ADDR
li k1, 0xb0800000 // Cart SRAM
sw k1, 0x0004(k0) // PI_CART_ADDR
li k1, 0x003FFFFF // 4MB size
sw k1, 0x0008(k0) // PI_RD_LEN

pi_wait3:
// Wait for the DMA to complete
lw k1, 0x0010(k0) // PI_STATUS
andi k1, k1, 0x1 // DMA busy
bnez k1, pi_wait3

loop:
// Wait until the system resets
b loop
73 changes: 51 additions & 22 deletions src/memory.S
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,9 @@
.globl tlbl_exception
.globl tlbs_exception
.globl tlbm_exception
.globl read_extension
.globl write_extension
.globl rom_base_address

.data

Expand All @@ -43,6 +46,7 @@ rom_addrs: .word 0:0x100
rom_entries: .word 0:0x100
rom_pointer: .byte 0
sram_dirty: .byte 0
rom_base_address: .word DEFAULT_ROM_BASE

.align 4
read_iomap:
Expand Down Expand Up @@ -107,6 +111,8 @@ read_iomap:
.word read_a1bx, read_dasxl, read_dasxh, read_dasbx // 0x4374-0x4377
.word read_a2axl, read_a2axh, read_ntrlx, read_unusedx // 0x4378-0x437B
.word read_unk, read_unk, read_unk, read_unusedx // 0x437C-0x437F
.word read_unk:(0x5FFF - 0x437F) // 0x4378-0x5FFF
.word read_unk:(0x7FB0 - 0x5FFF) // 0x6000-0x7FAF // Read Extension -- This gets overwritten during init.

.align 4
write_iomap:
Expand Down Expand Up @@ -178,14 +184,19 @@ write_iomap:
.word write_a1bx, write_dasxl, write_dasxh, write_dasbx // 0x4374-0x4377
.word write_a2axl, write_a2axh, write_ntrlx, write_unusedx // 0x4378-0x437B
.word write_unk, write_unk, write_unk, write_unusedx // 0x437C-0x437F
.word write_unk:(0x5FFF - 0x437F) // 0x4378-0x5FFF
.word write_unk:(0x7FB0 - 0x5FFF) // 0x6000-0x7FAF Write Extension -- this gets overwritten during init

.text

.align 5
memory_init:
// Detect HiROM headers with a rudimentary checksum check
// TODO: improve this?
lw t0, 0xB020FFDC
lw t0, rom_base_address
li t1, 0xA000FFDC
add t0, t0, t1
lw t0, 0(t0)
andi t1, t0, 0xFFFF
srl t0, t0, 16
xor t0, t0, t1
Expand All @@ -201,7 +212,10 @@ map_lorom:
li t2, 0x2000 // Block size (8KB)

// Set the SRAM mask using the header size
lw t9, 0xB0207FD8
lw t9, rom_base_address
li t8, 0xA0007FD8
add t9, t9, t8
lw t9, 0(t9)
srl t9, t9, 24
beqz t9, build_lomap
li t3, 0x400
Expand Down Expand Up @@ -244,16 +258,15 @@ lowram_area:

lorom_area:
// Special case LoROM; the exception handler will dynamically load blocks
li t3, 0x10200000 // ROM appended to file
li t4, 0x7F0000
and t4, t4, t0 // Mirrored bank
srl t4, t4, 1 // 32KB every 64KB bank
add t3, t3, t4
li t4, 0x7FFF
and t4, t4, t0 // Offset within 32KB
add t3, t3, t4
b map_lonone

lw t3, rom_base_address // ROM appended to file
li t4, 0x7F0000
and t4, t4, t0 // Mirrored bank
srl t4, t4, 1 // 32KB every 64KB bank
add t3, t3, t4
li t4, 0x7FFF
and t4, t4, t0 // Offset within 32KB
add t3, t3, t4
b map_lonone
losram_area:
// Check if this is a ROM or SRAM area
andi t4, t0, 0xFFFF
Expand Down Expand Up @@ -306,7 +319,10 @@ map_hirom:
li t2, 0x2000 // Block size (8KB)

// Set the SRAM mask using the header size
lw t9, 0xB020FFD8
lw t9, rom_base_address
li t3, 0xA000FFD8
add t9, t9, t3
lw t9, 0(t9)
srl t9, t9, 24
beqz t9, build_himap
li t3, 0x400
Expand Down Expand Up @@ -347,12 +363,11 @@ hiwram_area:

hirom_area:
// Special case HiROM; the exception handler will dynamically load blocks
li t3, 0x10200000 // ROM appended to file
li t4, 0x3FFFFF // ROM mask
and t4, t4, t0
add t3, t3, t4
b map_hinone

lw t3, rom_base_address // ROM appended to file
li t4, 0x3FFFFF // ROM mask
and t4, t4, t0
add t3, t3, t4
b map_hinone
hisram_area:
// Special case SRAM so writes can be tracked
beqz t9, hiempty_area
Expand Down Expand Up @@ -501,7 +516,7 @@ tlbl_io:
// Look up and return to an I/O read function if no memory is mapped
andi a0, a0, 0xFFFF
addi t0, a0, -0x2100
bgeu t0, 0x4380 - 0x2100, tlbl_unk
bgeu t0, 0x7FB0 - 0x2100, tlbl_unk
sll t0, t0, 2
lw k0, read_iomap(t0)
mtc0 k0, $14 // EPC
Expand Down Expand Up @@ -569,7 +584,7 @@ tlbs_io:
// Look up and return to an I/O write function if no memory is mapped
andi a0, a0, 0xFFFF
addi t0, a0, -0x2100
bgeu t0, 0x4380 - 0x2100, tlbs_unk
bgeu t0, 0x7FB0 - 0x2100, tlbs_unk
sll t0, t0, 2
lw k0, write_iomap(t0)
mtc0 k0, $14 // EPC
Expand Down Expand Up @@ -610,6 +625,11 @@ tlbm_exception:
nop
eret

.align 5
read_extension:
lhu v0, 0xAA008400(t0)
jr ra

.align 5
read_unk:
// Unknown I/O register read; use upper address byte to approximate open bus
Expand All @@ -632,8 +652,17 @@ read_wmdata: // v0: value
jr ra

.align 5
write_extension: // a1: value, t0: address
sb a1, 0xAA008400(t0) // (0x2100 << 2) = 0x8400 this is added to t0 as t0 is lowered by 0x2100.
lui t2, 0xA460 // PI register upper address
write_extension_wait1:
// Wait for the IO to complete
lw t1, 0x0010(t2) // PI_STATUS
andi t1, t1, 0x1 // DMA busy
bnez t1, write_extension_wait1
jr ra

write_unk:
// Unknown I/O register write; do nothing
jr ra

.align 5
Expand Down