AXI3 Memory is the Slave module which consists of all 5 Channels of AXI Protocol. This module is designed in Verilog HDL and Synthesized in Vivado Tool. Slave consists of memory of depth 128. Features of designed and implemented in this design are: Variable awlen, awsize of 32-bit, Burst of increment type, remaining type of burts are under developement stage. Response type okay, slave error and decode error.