AI Chip Navigation

Personal collection of links to research work on AI chips, computing-in-memory

⏰️Programs

	name	registeration	abstract	full_paper	notification	link
0	MICRO'24		24.4.21	24.4.18	24.7.19	https://microarch.org/micro56/submit/papers.php
1	ISCA'24		23.11.14	23.11.21	24.3.19	https://iscaconf.org/isca2023/
2	HPCA'25		24.7.26	24.8.2	24.11.5	https://hpca-conf.org/2025/
3	ASPLOS'25(Fall)		24.10.11	24.10.18	25.2.7	https://www.asplos-conference.org/asplos-2025-call-for-papers/
4	HotChips'24			24.4.19	24.7.15	https://hotchips.org/call_for_contrib/
5	ASP-DAC'25		24.7.5	24.7.12	24.9.4	https://www.aspdac.com/aspdac2025/cfp/
6	DAC'24		23.11.13	23.11.20	24.2.26	https://www.dac.com/Conference/2024-Call-for-Contributions
7	ISSAD'24		24.4.28	24.5.5	24.7.30	https://2024.iccad.com/authors/initial-author-instructions
8	FPGA'24		23.10.6	23.10.13	23.12.10	https://www.isfpga.org/call-for-papers/
9	CICC'24			23.11.20	24.1.5	https://www.ieee-cicc.org/2024-call-for-papers/
10	ISCAS'24					https://ieee-cas.org/event/conference/2024-ieee-international-symposium-circuits-and-systems
11	DATE'25	24.9.15		24.9.22		https://www.date-conference.com/date-2025-call-papers

🌐Paper Websites

PaperWebsite

DAC

• year: 2023.0 | link: https://ieeexplore.ieee.org/xpl/conhome/10247654/proceeding
• year: 2022.0 | link: https://dl.acm.org/doi/proceedings/10.1145/3489517
• link: https://ieeexplore.ieee.org/xpl/conhome/1000196/all-proceedings

ISCA

• year: 2023.0 | link: https://dl.acm.org/doi/proceedings/10.1145/3579371
• year: 2022.0 | link: https://dl.acm.org/doi/proceedings/10.1145/3470496
• link: https://ieeexplore.ieee.org/xpl/conhome/1000123/all-proceedings

JSSC

• link: https://ieeexplore.ieee.org/xpl/issues?punumber=4&isnumber=10608476

⭐️Interesting Papers

JSSC

2024

• name: Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine | volume: 59 | issue: 7
• name: A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection | volume: 59 | issue: 7
• name: An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips | volume: 59 | issue: 7
• name: PRESTO: A Processing-in-Memory-Based k-SAT Solver Using Recurrent Stochastic Neural Network With Unsupervised Learning | volume: 59 | issue: 7
• name: A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method | volume: 59 | issue: 7
• name: EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage | volume: 59 | issue: 7
• name: A 65-nm RRAM Compute-in-Memory Macro for Genome Processing | volume: 59 | issue: 7
• name: Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS | volume: 59 | issue: 6
• name: A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations | volume: 59 | issue: 6
• name: MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks | volume: 59 | issue: 6
• name: eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters | volume: 59 | issue: 6
• name: HGRP: A 181-µW Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free Feature Clustering | volume: 59 | issue: 6
• name: A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit | volume: 59 | issue: 5
• name: An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update | volume: 59 | issue: 5
• name: A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology | volume: 59 | issue: 4
• name: A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking | volume: 59 | issue: 4
• name: Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration | volume: 59 | issue: 4
• name: A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 ◦C | volume: 59 | issue: 4
• name: EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning | volume: 59 | issue: 3
• name: A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM | volume: 59 | issue: 3
• name: FreFlex: A High-Performance Processor for Convolution and Attention Computations via Sparsity-Adaptive Dynamic Frequency Boosting | volume: 59 | issue: 3
• name: Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra | volume: 59 | issue: 3
• name: DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm | volume: 59 | issue: 3
• name: Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip | volume: 59 | issue: 2
• name: A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking | volume: 59 | issue: 1
• name: MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing | volume: 59 | issue: 1
• name: MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity | volume: 59 | issue: 1
• name: DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell | volume: 59 | issue: 1
• name: A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme | volume: 59 | issue: 1
• name: MARSELLUS: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing | volume: 59 | issue: 1
• name: Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste | volume: 59 | issue: 1
• name: C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture | volume: 59 | issue: 1
• name: A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips | volume: 59 | issue: 1
• name: A 9-Mb HZO-Based Embedded FeRAM With 1012-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier | volume: 59 | issue: 1
• name: An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices | volume: 59 | issue: 1
• name: A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection | volume: 59 | issue: 1
• name: A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture | volume: 59 | issue: 8
• name: RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM | volume: 59 | issue: 8
• name: SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning | volume: 59 | issue: 8
• name: iMCU: A 28-nm Digital In-Memory Computing-Based Microcontroller Unit for TinyML | volume: 59 | issue: 8
• name: Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation | volume: 59 | issue: 8
• name: A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations | volume: 59 | issue: 8
• name: ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μJ/Sample On-Chip Learning for Edge-AI Applications | volume: 59 | issue: 8

🛠️Open Source

soc

• name: nvdla | lang: full | model level: cmodel+soc+rtl | link: https://nvdla.org/
• name: gemmini | lang: chisel | model level: rtl | link: https://github.com/ucb-bar/gemmini
• name: gemmini-test | lang: c | link: https://github.com/ucb-bar/gemmini-rocc-tests
• name: RISCV-TLM | lang: system c tlm | model level: cmodel | link: https://github.com/mariusmm/RISC-V-TLM
• name: RISCV-mini | lang: chisel | model level: rtl | link: https://github.com/ucb-bar/riscv-mini
• name: vertus-gpgpu | lang: chisel | model level: rtl | link: https://github.com/THU-DSP-LAB/ventus-gpgpu
• name: eyerissF | lang: python | model level: functional | link: https://github.com/jneless/EyerissF
• name: tiny-riscv | lang: verilog | model level: rtl | link: https://github.com/liangkangnan/tinyriscv
• name: SoDLA | lang: chisel | model level: rtl | link: https://github.com/soDLA-publishment/soDLA | note: chisel version of nvdla
• name: t1 | lang: chisel | model level: rtl | link: https://github.com/chipsalliance/t1 | note: riscv vector machine

tutorials

• name: learnsystemc | lang: systemc | code_link: https://github.com/learnwithexamples/learnsystemc | doc_link: https://www.learnsystemc.com/
• name: UVM | lang: systemverilog | doc_link: https://www.chipverify.com/uvm/uvm-testbench-example-1
• name: systec-training | lang: systemc-tlm | code_link: https://github.com/SingularityKChen/SystemC-Training

model_tool

• name: timeloop | lang: python | doc_link: https://timeloop.csail.mit.edu/
• name: cimloop | lang: python | code_link: https://github.com/mit-emze/cimloop
• name: neuro sim | lang: c++ | code_link: https://github.com/neurosim/DNN_NeuroSim_V2.1
• name: Approximate Computing in Deep Neural Networks | code_link: https://github.com/e-dupuis/awesome-approximate-dnn
• name: awesome pruning | code_link: https://github.com/he-y/Awesome-Pruning
• name: FRAME: Fast Roofline Analytical Modeling and Estimation | lang: python | code_link: https://github.com/maestro-project/frame
• name: DNN-Chip Predictor | lang: python | code_link: https://github.com/GATECH-EIC/DNN-Chip-Predictor
• name: Noxim - the NoC Simulator | lang: systemc | code_link: https://github.com/davidepatti/noxim
• name: CACTI | lang: c++ | code_link: https://github.com/HewlettPackard/cacti
• name: The Constellation NoC Generator | lang: chisel | code_link: https://github.com/ucb-bar/constellation
• name: OpenRAM | lang: python | code_link: https://github.com/VLSIDA/OpenRAM | doc_link: https://openram.org/
• name: chipyard | lang: chisel | code_link: https://github.com/ucb-bar/chipyard

design_flow

• name: awesome-hdl | link: https://github.com/drom/awesome-hdl
• name: logic | lang: systemc+uvm | link: https://github.com/tymonx/logic
• name: Open Hardware Verification | link: https://github.com/ben-marshall/awesome-open-hardware-verification

ip

• name: freecores | link: https://github.com/freecores
• name: SystemC-Components | lang: systemc | link: https://github.com/Minres/SystemC-Components
• name: matchlib | lang: c++/systemc | link: https://github.com/NVlabs/matchlib
• name: chipsalliance | link: https://www.chipsalliance.org/projects/

Other Awesome Rep

Neural-Networks-on-Silicon