Verification IP of fully parameterized 4 modes SPI
CPOL : Clock Polarity
CPHA : Clock Phase
DATA_BYTE_WIDTH : Transaction byte number
MAX_SLAVE_NUMBER : Slave count which are connected to master
sCLK_Period : Spi Clock Period generated by VIP master
Detailed description of SPI can be found in :
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface
Here an example transaction between SPI VIP and SPI Slave :
Configuration of Transaction given above is :
Created test name for writing and reading at the same time is spi_wr_test
Created test name for writing only is spi_w_test
Created test name for reading only is spi_r_test
Results of spi_wr_test is :
Given test above named spi_wr_test assertion results are :
Given test above named spi_wr_test code coverage is :
