This repository contains the lecture schedule (including links to lecture summaries), descriptions of the assignments, and code necessary for completing the assignments for ECEN 520.
| Date | Lecture |
|---|---|
| Week 1 | |
| 9/3/2025 | Class Overview |
| 9/5/2025 | SystemVerilog Review |
| Week 2 | |
| 9/8/2025 | Behavioral SystemVerilog |
| 9/10/2025 | FSM Design #1 |
| 9/12/2025 | FSM Output Glitches and State Encoding |
| Week 3 | |
| 9/15/2025 | RTL Design using ASM Diagrams |
| 9/17/2025 | SystemVerilog Testbenches |
| 9/19/2025 | Functions, Tasks, Threads, generate |
| Week 4 | |
| 9/22/2025 | SystemVerilog Types |
| 9/24/2025 | SystemVerilog Types continued |
| 9/26/2025 | HDL Synthesis |
| Week 5 | |
| 9/29/2025 | SPI Controller |
| 10/1/2025 | |
| 10/3/2025 | Exam #1 |
| Week 6 | |
| 10/6/2025 | Memories |
| 10/8/2025 | Timing overview and review |
| 10/10/2025 | Clock Skew |
| Week 7 | |
| 10/13/2025 | Xilinx Clock Timing reports |
| 10/15/2025 | Xilinx Clock Resources (MMCM) |
| 10/17/2025 | Reset timing and strategies |
| Week 8 | |
| 10/20/2025 | Metastability & Synchronizer design |
| 10/22/2025 | Clock domain crossing |
| 10/24/2025 | Handshaking and Data Transfer |
| Week 9 | |
| 10/27/2025 | Poor Design Practice |
| 10/29/2025 | |
| 10/31/2025 | Pipelining and Retiming |
| Week 10 | |
| 11/3/2025 | VHDL Part 1 |
| 11/5/2025 | VHDL Part 2 |
| 11/7/2025 | Exam #2 |
| Week 11 | |
| 11/10/2025 | Digital Arithmetic #1 |
| 11/12/2025 | Digital Arithmetic #2 |
| 11/14/2025 | DSP Blocks |
| Week 12 | |
| 11/17/2025 | DDR |
| 11/19/2025 | IO Resources |
| 11/21/2025 | |
| Week 13 | |
| 11/24/2025 | No Class |
| 11/26/2025 | No Class - Thanksgiving Break |
| 11/28/2025 | No Class - Thanksgiving Break |
| Week 14 | |
| 12/1/2025 | CLB Blocks |
| 12/3/2025 | AXI Bus |
| 12/5/2025 | IP Integration |
| Week 15 | |
| 12/8/2025 | Review for Exam |
| 12/10/2025 | Review for Exam |
| 12/12/2025 | No Class - Final's Week |
| Week 16 | |
| 12/16/2025 | Final Exam in class |
All assignments must be submitted on a classroom GitHub repository. Review the assignment mechanics page to learn how to properly submit your assignments.
| # | Name | Directory/Lab Tag |
|---|---|---|
| 1 | UART Transmitter-Simulation | tx_sim |
| 2 | UART Transmitter-Synthesis and Download | tx_download |
| 3 | UART Receiver Simulation | rx_sim |
| 4 | UART Synthesis and Download | rx_download |
| 5 | SPI Controller-Simulation | spi_cntrl |
| 6 | SPI Controller-Download | spi_download |
| 7 | BRAM | bram |
| 8 | BRAM-Download | bram_download |
| 9 | MMCM Clocking | mmcm |
| 10 | VGA Controller (VHDL) | vga |
| 11 | DDR | ddr |
| 11 | Project | project |