Simplify board initialisation and get it back working again

.github/workflows/main.yaml

@@ -102,7 +102,7 @@ jobs:
       - name: Run simulation tests
         working-directory: ./${{ matrix.design }}
         run: |
-          make sim-check
+          pdm sim-check
 
       - name: Test submit dry run
         working-directory: ./${{ matrix.design }}

README.md

@@ -44,21 +44,20 @@ First choose a design to test. Here we will use the `minimal` design.
 Change into the `minimal` directory in `chipflow-examples` to use this design. Now we need to 'lock' our pins - the ChipFlow tooling will then automatically allocate inputs and outputs from your design to pins on the chip.
 
 ```
-pdm run chipflow pin lock
+pdm chipflow pin lock
 ```
 
 We can now simulate and test the design by running:
 ```
-make sim-check
+pdm sim-check
 ```
 
 You should see the simulation model being built and run - and a small test firmware running on the simulated System-on-a-Chip (aided by our local friendly cat!)
 
 ```
-pdm run chipflow sim
 -- build_sim_cxxrtl
 -- build_sim
-pdm run chipflow software
+pdm chipflow software
 -- gather_depencencies
 -- build_software_elf
 -- build_software
@@ -74,7 +73,7 @@ Event logs are identical
 Now you are ready to try building this design into a chip! To submit your design to ChipFlow Platform where it will be built into GDS, run:
 
 ```
-pdm run chipflow silicon submit
+pdm submit
 
 ```
 This should return something like:
@@ -88,7 +87,7 @@ Your design will now start building: pictures and logs of the build are availabl
 
 If you would like to get the build logs streamed to your command-line, you can instead call:
 ```
-pdm run chipflow silicon submit --wait
+pdm submit --wait
 ```
 
 

mcu_soc/chipflow.toml

@@ -6,6 +6,7 @@ soc = "design.design:MySoC"
 
 [chipflow.steps]
 sim = "design.steps.sim:MySimStep"
+board = "design.steps.board:MyBoardStep"
 silicon = "chipflow_lib.steps.silicon:SiliconStep"
 software = "design.steps.software:MySoftwareStep"
 

mcu_soc/design/design.py

@@ -3,7 +3,7 @@
 
 from amaranth import Module
 from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out, flipped, connect
+from amaranth.lib.wiring import Out, flipped, connect
 
 from amaranth_soc import csr, wishbone
 from amaranth_soc.csr.wishbone import WishboneCSRBridge

mcu_soc/design/ips/pdm.py

@@ -1,6 +1,5 @@
 from amaranth import *
-from amaranth import Elaboratable, Module
-from amaranth.build import Platform
+from amaranth import Module
 
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, flipped, connect

mcu_soc/design/ips/pwm.py

@@ -1,6 +1,5 @@
 from amaranth import *
-from amaranth import Elaboratable, Module
-from amaranth.build import Platform
+from amaranth import Module
 
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, flipped, connect

mcu_soc/design/sim/doit_build.py

@@ -9,7 +9,7 @@
 RUNTIME_DIR = importlib.resources.files("yowasp_yosys") / "share/include/backends/cxxrtl/runtime"
 
 ZIG_CXX  = f"{sys.executable} -m ziglang c++"
-CXXFLAGS = f"-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
+CXXFLAGS = "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
 INCLUDES = f"-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}"
 
 

mcu_soc/design/software/doit_build.py

@@ -4,7 +4,6 @@
 import shutil
 
 from doit import create_after
-from doit.action import CmdAction
 import chipflow_lib.config
 
 
@@ -15,7 +14,7 @@
 CINCLUDES = f"-I. -I{BUILD_DIR} -I{DESIGN_DIR}/software"
 LINKER_SCR = f"{BUILD_DIR}/generated/sections.lds"
 SOFTWARE_START = f"{BUILD_DIR}/generated/start.S"
-CFLAGS = f"-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
+CFLAGS = "-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
 CFLAGS += f"{LINKER_SCR},--strip-debug -static -ffreestanding -nostdlib {CINCLUDES}"
 
 

mcu_soc/design/steps/board.py

@@ -4,8 +4,7 @@
 
 from amaranth import *
 from amaranth.lib import wiring
-from amaranth.lib.wiring import connect, flipped
-from amaranth.build import Resource, Subsignal, Pins, Attrs
+from amaranth.lib.cdc import ResetSynchronizer
 
 from ..design import MySoC
 
@@ -17,92 +16,58 @@ def elaborate(self, platform):
         m.submodules.soc = soc = MySoC()
 
         m.domains += ClockDomain("sync")
-        m.submodules.clock_reset_provider = platform.providers.ClockResetProvider()
 
-        m.submodules.spiflash_provider = spiflash_provider = platform.providers.QSPIFlashProvider()
-        connect(m, flipped(spiflash_provider.pins), soc.flash)
-
-        m.submodules.led_gpio_provider = led_gpio_provider = platform.providers.LEDGPIOProvider()
-        connect(m, flipped(led_gpio_provider.pins), soc.gpio_0)
-
-        m.submodules.uart_provider = uart_provider = platform.providers.UARTProvider()
-        connect(m, flipped(uart_provider.pins), soc.uart_0)
-
-        # Extra IO on headers
-        platform.add_resources([
-            Resource(
-                "expansion",
-                0,
-                Subsignal("user_spi0_sck",  Pins("0+", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi0_copi", Pins("0-", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi0_cipo", Pins("1+", conn=("gpio", 0), dir='i')),
-                Subsignal("user_spi0_csn", Pins("1-", conn=("gpio", 0), dir='o')),
-
-                Subsignal("user_spi1_sck",  Pins("2+", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi1_copi", Pins("2-", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi1_cipo", Pins("3+", conn=("gpio", 0), dir='i')),
-                Subsignal("user_spi1_csn", Pins("3-", conn=("gpio", 0), dir='o')),
-
-                Subsignal("i2c0_sda", Pins("4+", conn=("gpio", 0), dir='io')),
-                Subsignal("i2c0_scl", Pins("4-", conn=("gpio", 0), dir='io')),
-
-                Subsignal("motor_pwm0_pwm",  Pins("5+", conn=("gpio", 0), dir='o')),
-                Subsignal("motor_pwm0_dir",  Pins("5-", conn=("gpio", 0), dir='o')),
-                Subsignal("motor_pwm0_stop", Pins("6+", conn=("gpio", 0), dir='i'), Attrs(PULLMODE="DOWN")),
-
-                Subsignal("motor_pwm1_pwm",  Pins("6-", conn=("gpio", 0), dir='o')),
-                Subsignal("motor_pwm1_dir",  Pins("7+", conn=("gpio", 0), dir='o')),
-                Subsignal("motor_pwm1_stop", Pins("7-", conn=("gpio", 0), dir='i'), Attrs(PULLMODE="DOWN")),
-
-                Subsignal("uart1_rx", Pins("8+", conn=("gpio", 0), dir='i')),
-                Subsignal("uart1_tx", Pins("8-", conn=("gpio", 0), dir='o')),
-
-                Subsignal("cpu_jtag_tck", Pins("9+", conn=("gpio", 0), dir='i')),
-                Subsignal("cpu_jtag_tms", Pins("9-", conn=("gpio", 0), dir='i')),
-                Subsignal("cpu_jtag_tdi", Pins("10+", conn=("gpio", 0), dir='i')),
-                Subsignal("cpu_jtag_tdo", Pins("10-", conn=("gpio", 0), dir='o')),
-                Subsignal("cpu_jtag_trst", Pins("11+", conn=("gpio", 0), dir='i')),
-
-                Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP"),
+        m.d.comb += ClockSignal("sync").eq(platform.request("clk25").i)
+
+        btn_rst = platform.request("button_pwr")
+        m.submodules.rst_sync = ResetSynchronizer(arst=btn_rst.i, domain="sync") 
+
+        flash = platform.request("spi_flash", dir=dict(cs='-', copi='-', cipo='-', wp='-', hold='-'))
+        # Flash clock requires a special primitive to access in ECP5
+        m.submodules.usrmclk = Instance(
+            "USRMCLK",
+            i_USRMCLKI=soc.flash.clk.o,
+            i_USRMCLKTS=ResetSignal(),  # tristate in reset for programmer accesss
+            a_keep=1,
+        )
+
+        # Flash IO buffers
+        m.submodules += Instance(
+            "OBZ",
+            o_O=flash.cs.io,
+            i_I=soc.flash.csn.o,
+            i_T=ResetSignal(),
+        )
+
+        # Connect flash data pins in order
+        data_pins = ["copi", "cipo", "wp", "hold"]
+        for i in range(4):
+            m.submodules += Instance(
+                "BB",
+                io_B=getattr(flash, data_pins[i]).io,
+                i_I=soc.flash.d.o[i],
+                i_T=~soc.flash.d.oe[i],
+                o_O=soc.flash.d.i[i]
             )
-        ])
-
-        exp = platform.request("expansion")
-        def _connect_interface(interface, name):
-            pins = dict()
-            for member in interface.signature.members:
-                pin, suffix = member.rsplit("_", 2)
-                assert suffix in ("o", "i", "oe"), suffix
-                pins[pin] = getattr(interface, member).width
-            for pin, width in pins.items():
-                for i in range(width):
-                    platform_pin = getattr(exp, f"{name}_{pin}{'' if width == 1 else str(i)}")
-                    if hasattr(interface, f"{pin}_i"):
-                        m.d.comb += getattr(interface, f"{pin}_i")[i].eq(platform_pin.i)
-                    if hasattr(interface, f"{pin}_o"):
-                        m.d.comb += platform_pin.o.eq(getattr(interface, f"{pin}_o")[i])
-                    if hasattr(interface, f"{pin}_oe"):
-                        m.d.comb += platform_pin.oe.eq(getattr(interface, f"{pin}_oe")[i])
-
-        _connect_interface(soc.user_spi_0, "user_spi0")
-        _connect_interface(soc.user_spi_1, "user_spi1")
-
-        _connect_interface(soc.i2c_0, "i2c0")
-
-        _connect_interface(soc.motor_pwm0, "motor_pwm0")
-        _connect_interface(soc.motor_pwm1, "motor_pwm1")
 
-        _connect_interface(soc.uart_1, "uart1")
+        # Connect LEDs to GPIO0
+        for i in range(8):
+            led = platform.request("led", i)
+            m.d.comb += led.o.eq(soc.gpio_0.gpio.o[i])
 
-        _connect_interface(soc.cpu_jtag, "cpu_jtag")
+        # Connect UART0
+        uart = platform.request("uart")
+        m.d.comb += [
+            uart.tx.o.eq(soc.uart_0.tx.o),
+            soc.uart_0.rx.i.eq(uart.rx.i),
+        ]
 
         return m
 
 class MyBoardStep(BoardStep):
     def __init__(self, config):
 
         platform = ULX3S_85F_Platform()
-        platform.providers = board_ulx3s_providers
 
         super().__init__(config, platform)
 

mcu_soc/design/steps/sim.py

@@ -1,8 +1,6 @@
 from chipflow_lib.steps.sim import SimStep
 
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import connect, flipped
 from amaranth.back import rtlil
 
 from ..design import MySoC

minimal/chipflow.toml

@@ -6,6 +6,7 @@ soc = "design.design:MySoC"
 
 [chipflow.steps]
 sim = "design.steps.sim:MySimStep"
+board = "design.steps.board:MyBoardStep"
 silicon = "chipflow_lib.steps.silicon:SiliconStep"
 software = "design.steps.software:MySoftwareStep"
 

minimal/design/design.py

@@ -1,9 +1,8 @@
-from chipflow_lib.platforms.sim import SimPlatform
 from chipflow_lib.software.soft_gen import SoftwareGenerator
 
 from amaranth import Module
 from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out, flipped, connect
+from amaranth.lib.wiring import Out, flipped, connect
 
 from amaranth_soc import csr, wishbone
 from amaranth_soc.csr.wishbone import WishboneCSRBridge
@@ -13,12 +12,9 @@
 from amaranth_soc.wishbone.sram import WishboneSRAM
 from amaranth_orchard.io import GPIOPeripheral
 from amaranth_orchard.io import UARTPeripheral
-from amaranth_orchard.io import SPISignature, SPIPeripheral
-from amaranth_orchard.io import I2CSignature, I2CPeripheral
 
 from minerva.core import Minerva
 
-from chipflow_lib.platforms import InputPinSignature, OutputPinSignature
 # from .ips.pdm import PDMPeripheral
 
 __all__ = ["MySoC"]

minimal/design/sim/doit_build.py

@@ -9,7 +9,7 @@
 RUNTIME_DIR = importlib.resources.files("yowasp_yosys") / "share/include/backends/cxxrtl/runtime"
 
 ZIG_CXX  = f"{sys.executable} -m ziglang c++"
-CXXFLAGS = f"-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
+CXXFLAGS = "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
 INCLUDES = f"-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}"