Quadrilatero BA

do_sim.sh

@@ -0,0 +1,4 @@
+make questasim-sim FUSESOC_PARAM="--X_EXT=1"
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim/
+make run-gui PLUSARGS="c firmware=../../../sw/build/main.hex" 
+cd ../../..

hw/ip_examples/quadrilatero/rtl/include/quadrilatero_pkg.sv

@@ -8,7 +8,8 @@ package quadrilatero_pkg;
   parameter int unsigned N_REGS                 =   8;
   parameter int unsigned DATA_WIDTH             =  32;
   parameter int unsigned BUS_WIDTH              = 128;
-  parameter int unsigned MESH_WIDTH             =   4;
+  parameter int unsigned MESH_WIDTH             =   8;  // change register dimension
+  parameter int unsigned SA_MESH_WIDTH          =   4;  // change systolic array dimension
   parameter int unsigned NUM_EXEC_UNITS         =   3;  // change me to add units
   parameter int unsigned MAX_NUM_READ_OPERANDS  =   3;
   parameter int unsigned MAX_NUM_WRITE_OPERANDS =   1;
@@ -17,8 +18,14 @@ package quadrilatero_pkg;
   parameter int unsigned RF_READ_PORTS          =   4;
   parameter int unsigned RF_WRITE_PORTS         =   3;
 
-  localparam int unsigned N_ROWS = MESH_WIDTH             ;
-  localparam int unsigned RLEN   = DATA_WIDTH * MESH_WIDTH;
+  localparam int unsigned RLEN    = DATA_WIDTH * MESH_WIDTH;
+  localparam int unsigned ALEN    = 128;
+  localparam int unsigned LLEN    = 128;
+  localparam int unsigned LEN = ALEN;
+  localparam int unsigned N_ROWS  = LEN / DATA_WIDTH          ; //TODO: not sure if this is correct?
+  localparam int unsigned N_TILES = (RLEN/LEN)**2; 
+  localparam int unsigned TILE_ADDR = (RLEN/LEN) == 1? 0: RLEN/LEN;
+  localparam int unsigned N_IREGS  = N_REGS * N_TILES;
 
 
   typedef enum logic [2:0] {
@@ -54,9 +61,8 @@ package quadrilatero_pkg;
   } lsu_conf_t;
 
   typedef struct packed {
-    logic [xif_pkg::X_ID_WIDTH-1:0] id;  
-    logic                           rvalid;  
-    logic                           wready;     
+    logic [xif_pkg::X_ID_WIDTH-1:0] id;    
+    logic valid; 
   } rw_queue_t;
 
   localparam int unsigned WR_PORT = (WRITE_PORTS > 1) ? $clog2(WRITE_PORTS) : 1;

hw/ip_examples/quadrilatero/rtl/quadrilatero.sv

@@ -126,29 +126,29 @@ module quadrilatero
 
 
   // RF Sequencer
-  logic [quadrilatero_pkg::READ_PORTS-1    :0][$clog2(quadrilatero_pkg::N_REGS)-1:0] rf_seq_raddr_from_fu   ;
+  logic [quadrilatero_pkg::READ_PORTS-1    :0][$clog2(quadrilatero_pkg::N_IREGS)-1:0] rf_seq_raddr_from_fu   ;
   logic [quadrilatero_pkg::READ_PORTS-1    :0][$clog2(quadrilatero_pkg::N_ROWS)-1:0] rf_seq_rrowaddr_from_fu;
-  logic [quadrilatero_pkg::READ_PORTS-1    :0][quadrilatero_pkg::RLEN-1:0]           rf_seq_rdata_from_fu   ;
+  logic [quadrilatero_pkg::READ_PORTS-1    :0][quadrilatero_pkg::LEN-1:0]           rf_seq_rdata_from_fu   ;
   logic [quadrilatero_pkg::READ_PORTS-1    :0]                                     rf_seq_rvalid_from_fu  ;
   logic [quadrilatero_pkg::READ_PORTS-1    :0]                                     rf_seq_rlast_from_fu   ;
   logic [quadrilatero_pkg::READ_PORTS-1    :0]                                     rf_seq_rready_from_fu  ;
   logic [quadrilatero_pkg::READ_PORTS-1    :0][xif_pkg::X_ID_WIDTH-1:0]            rf_seq_rd_id_from_fu   ;
 
-  logic [quadrilatero_pkg::WRITE_PORTS-1   :0][$clog2(quadrilatero_pkg::N_REGS)-1:0] rf_seq_waddr_from_fu   ;
+  logic [quadrilatero_pkg::WRITE_PORTS-1   :0][$clog2(quadrilatero_pkg::N_IREGS)-1:0] rf_seq_waddr_from_fu   ;
   logic [quadrilatero_pkg::WRITE_PORTS-1   :0][$clog2(quadrilatero_pkg::N_ROWS)-1:0] rf_seq_wrowaddr_from_fu;
-  logic [quadrilatero_pkg::WRITE_PORTS-1   :0][quadrilatero_pkg::RLEN-1:0]           rf_seq_wdata_from_fu   ;
+  logic [quadrilatero_pkg::WRITE_PORTS-1   :0][quadrilatero_pkg::LEN-1:0]           rf_seq_wdata_from_fu   ;
   logic [quadrilatero_pkg::WRITE_PORTS-1   :0]                                     rf_seq_we_from_fu      ;
   logic [quadrilatero_pkg::WRITE_PORTS-1   :0]                                     rf_seq_wlast_from_fu   ;
   logic [quadrilatero_pkg::WRITE_PORTS-1   :0]                                     rf_seq_wready_from_fu  ;
   logic [quadrilatero_pkg::WRITE_PORTS-1   :0][xif_pkg::X_ID_WIDTH-1:0]            rf_seq_wr_id_from_fu   ;
 
-  logic [quadrilatero_pkg::RF_READ_PORTS-1 :0][$clog2(quadrilatero_pkg::N_REGS)-1:0] rf_seq_raddr_to_rf     ;
+  logic [quadrilatero_pkg::RF_READ_PORTS-1 :0][$clog2(quadrilatero_pkg::N_IREGS)-1:0] rf_seq_raddr_to_rf     ;
   logic [quadrilatero_pkg::RF_READ_PORTS-1 :0][$clog2(quadrilatero_pkg::N_ROWS)-1:0] rf_seq_rrowaddr_to_rf  ;
-  logic [quadrilatero_pkg::RF_READ_PORTS-1 :0][quadrilatero_pkg::RLEN-1:0]           rf_seq_rdata_to_rf     ;
+  logic [quadrilatero_pkg::RF_READ_PORTS-1 :0][quadrilatero_pkg::LEN-1:0]           rf_seq_rdata_to_rf     ;
 
-  logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0][$clog2(quadrilatero_pkg::N_REGS)-1:0] rf_seq_waddr_to_rf     ;
+  logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0][$clog2(quadrilatero_pkg::N_IREGS)-1:0] rf_seq_waddr_to_rf     ;
   logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0][$clog2(quadrilatero_pkg::N_ROWS)-1:0] rf_seq_wrowaddr_to_rf  ;
-  logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0][quadrilatero_pkg::RLEN-1:0]           rf_seq_wdata_to_rf     ;
+  logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0][quadrilatero_pkg::LEN-1:0]           rf_seq_wdata_to_rf     ;
   logic [quadrilatero_pkg::RF_WRITE_PORTS-1:0]                                     rf_seq_we_to_rf        ;
 
   quadrilatero_pkg::rw_queue_t                [quadrilatero_pkg::N_REGS-1:0]         rf_seq_rw_queue_entry  ;
@@ -170,30 +170,30 @@ module quadrilatero
   logic                                      sa_weight_rdata_ready;
   logic                                      sa_weight_rlast      ;
   logic [xif_pkg::X_ID_WIDTH-1:0]            sa_input_id          ;
-  logic [quadrilatero_pkg::RLEN-1:0]           sa_weight_rdata      ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] sa_weight_raddr      ;
+  logic [quadrilatero_pkg::LEN-1:0]           sa_weight_rdata      ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] sa_weight_raddr      ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] sa_weight_rrowaddr   ;
 
   logic                                      sa_data_rdata_valid  ;
   logic                                      sa_data_rdata_ready  ;
   logic                                      sa_data_rlast        ;
   logic [xif_pkg::X_ID_WIDTH-1:0]            sa_output_id         ;
-  logic [quadrilatero_pkg::RLEN-1:0]           sa_data_rdata        ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] sa_data_raddr        ;
+  logic [quadrilatero_pkg::LEN-1:0]           sa_data_rdata        ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] sa_data_raddr        ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] sa_data_rrowaddr     ;
 
   logic                                      sa_acc_rdata_valid   ;
   logic                                      sa_acc_rdata_ready   ;
   logic                                      sa_acc_rlast         ;
-  logic [quadrilatero_pkg::RLEN-1:0]           sa_acc_rdata         ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] sa_acc_raddr         ;
+  logic [quadrilatero_pkg::LEN-1:0]           sa_acc_rdata         ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] sa_acc_raddr         ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] sa_acc_rrowaddr      ;
 
   logic                                      sa_res_we            ;
   logic                                      sa_res_wready        ;
   logic                                      sa_res_wlast         ;
-  logic [quadrilatero_pkg::RLEN-1:0]           sa_res_wdata         ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] sa_res_waddr         ;
+  logic [quadrilatero_pkg::LEN-1:0]           sa_res_wdata         ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] sa_res_waddr         ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] sa_res_wrowaddr      ;
 
   logic                                      sa_finished          ;
@@ -226,15 +226,15 @@ module quadrilatero
   logic                                      lsu_wlast            ;
   logic                                      lsu_wready           ;
   logic [xif_pkg::X_ID_WIDTH-1:0]            lsu_id               ;
-  logic [quadrilatero_pkg::RLEN-1:0]           lsu_wdata            ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] lsu_waddr            ;
+  logic [quadrilatero_pkg::LEN-1:0]           lsu_wdata            ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] lsu_waddr            ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] lsu_wrowaddr         ;
 
   logic                                      lsu_rlast            ;
   logic                                      lsu_rready           ;
   logic                                      lsu_rvalid           ;
-  logic [quadrilatero_pkg::RLEN-1:0]           lsu_rdata            ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] lsu_raddr            ;
+  logic [quadrilatero_pkg::LEN-1:0]           lsu_rdata            ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] lsu_raddr            ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] lsu_rrowaddr         ;
 
   logic                                      lsu_busy             ;
@@ -254,8 +254,8 @@ module quadrilatero
   logic [xif_pkg::X_ID_WIDTH-1:0]            perm_unit_id               ;
   logic [xif_pkg::X_ID_WIDTH-1:0]            perm_unit_instr_id         ;
   logic [xif_pkg::X_ID_WIDTH-1:0]            perm_unit_finished_instr_id;
-  logic [quadrilatero_pkg::RLEN-1:0]           perm_unit_wdata            ;
-  logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] perm_unit_waddr            ;
+  logic [quadrilatero_pkg::LEN-1:0]           perm_unit_wdata            ;
+  logic [$clog2(quadrilatero_pkg::N_IREGS)-1:0] perm_unit_waddr            ;
   logic [$clog2(quadrilatero_pkg::N_ROWS)-1:0] perm_unit_wrowaddr         ;
   logic [$clog2(quadrilatero_pkg::N_REGS)-1:0] perm_unit_reg              ;
 
@@ -671,7 +671,7 @@ module quadrilatero
   );
 
   quadrilatero_systolic_array #(
-      .MESH_WIDTH(MESH_WIDTH),
+      .MESH_WIDTH(quadrilatero_pkg::SA_MESH_WIDTH),
       .FPU        (FPU      )
   ) sa_inst (
       .clk_i                                                   ,
@@ -774,6 +774,7 @@ module quadrilatero
 
       // To Register Loader
       .busy_i               (lsu_busy | x_res_almost_full),  // Load Unit busy
+      .finished_i           (lsu_finished),
       .start_o              (lsu_ctrl_start              ),  // 
       .issued_instr_o       (lsu_ctrl_issued_instr       ),  // issued instruction
       .issued_instr_conf_o  (lsu_ctrl_issued_instr_conf  )    // issued instruction configuration

hw/ip_examples/quadrilatero/rtl/quadrilatero_dispatcher.sv

@@ -168,8 +168,8 @@ module quadrilatero_dispatcher #(
 
     delta = 3'b0;
     for(int ii = 0; ii < N_REGS; ii++) begin
-      delta += {2'b0, rw_queue_entry_o[ii].rvalid};
-      delta += {2'b0, rw_queue_entry_o[ii].wready};
+      delta += {2'b0, rvalid[ii]};
+      delta += {2'b0, wready[ii]};
     end
 
     done  = (delta == outstanding_op_q);
@@ -210,10 +210,9 @@ module quadrilatero_dispatcher #(
     rvalid[rreg_q[2]] |= reg3_valid &~ ld_reg3;
     wready[wreg_q   ] = regw_valid &~ ld_regw;
     for(int ii = 0; ii < N_REGS; ii++) begin
-      rw_queue_entry_o[ii].rvalid = rvalid[ii];
-      rw_queue_entry_o[ii].wready = wready[ii];
       rw_queue_entry_o[ii].id     = instr_id_q;
-      rw_queue_push_o [ii]        = rw_queue_entry_o[ii].rvalid | rw_queue_entry_o[ii].wready;
+      rw_queue_push_o [ii]        = rvalid[ii] | wready[ii];
+      rw_queue_entry_o[ii].valid  = rvalid[ii] | wready[ii];
     end
   end
 

hw/ip_examples/quadrilatero/rtl/quadrilatero_ff_fs_dr_stage.sv

@@ -12,7 +12,7 @@ module quadrilatero_ff_fs_dr_stage #(
     parameter DATA_WIDTH = 32,
     parameter N_REGS = 8,
     localparam N_ROWS = MESH_WIDTH,
-    localparam RLEN = DATA_WIDTH * MESH_WIDTH
+    localparam ALEN = DATA_WIDTH * MESH_WIDTH
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -28,23 +28,23 @@ module quadrilatero_ff_fs_dr_stage #(
     // Data Read Register Port 
     output logic [$clog2(N_REGS)-1:0] data_raddr_o,
     output logic [$clog2(N_ROWS)-1:0] data_rrowaddr_o,
-    input logic [RLEN-1:0] data_rdata_i,
+    input logic [ALEN-1:0] data_rdata_i,
     input logic data_rdata_valid_i,
     output logic data_rdata_ready_o,
     output logic data_rlast_o,
 
     // Accumulator Read Register Port
     output logic [$clog2(N_REGS)-1:0] acc_raddr_o,
     output logic [$clog2(N_ROWS)-1:0] acc_rrowaddr_o,
-    input logic [RLEN-1:0] acc_rdata_i,
+    input logic [ALEN-1:0] acc_rdata_i,
     input logic acc_rdata_valid_i,
     output logic acc_rdata_ready_o,
     output logic acc_rlast_o,
 
     // Accumulator Out Write Register Port
     output logic [$clog2(N_REGS)-1:0] res_waddr_o,
     output logic [$clog2(N_ROWS)-1:0] res_wrowaddr_o,
-    output logic [          RLEN-1:0] res_wdata_o,
+    output logic [          ALEN-1:0] res_wdata_o,
     output logic                      res_we_o,
     output logic                      res_wlast_o,
     input  logic                      res_wready_i,
@@ -82,7 +82,7 @@ module quadrilatero_ff_fs_dr_stage #(
 
   logic [     $clog2(N_REGS)-1:0] n_res_waddr;
   logic [     $clog2(N_ROWS)-1:0] n_res_wrowaddr;
-  logic [               RLEN-1:0] n_res_wdata;
+  logic [               ALEN-1:0] n_res_wdata;
   logic                           n_res_we;
 
   logic [     $clog2(N_REGS)-1:0] data_reg_ff;  // data register

hw/ip_examples/quadrilatero/rtl/quadrilatero_lsu.sv

@@ -52,6 +52,8 @@ module quadrilatero_lsu #(
   localparam int unsigned DEPTH           = (FIFO_DEPTH > 0) ? FIFO_DEPTH - 1     : 0;
   localparam int unsigned Addr_Fifo_Depth = (FIFO_DEPTH > 1) ? $clog2(FIFO_DEPTH) : 1;
   localparam int unsigned LastFifoUsage   = DEPTH - 1;
+  localparam int unsigned LastRow = quadrilatero_pkg::MESH_WIDTH-1;
+  localparam int unsigned LastCol = quadrilatero_pkg::TILE_ADDR-1;
 
 
   logic                       terminate         ;
@@ -100,7 +102,10 @@ module quadrilatero_lsu #(
   logic                       store_fifo_empty  ;
   logic [     DATA_WIDTH-1:0] store_fifo_output ;
   logic                       store_fifo_pop    ;
-
+  logic [$clog2(quadrilatero_pkg::MESH_WIDTH)-1:0] row_counter_d;
+  logic [$clog2(quadrilatero_pkg::MESH_WIDTH)-1:0] row_counter_q;
+  logic [$clog2(quadrilatero_pkg::TILE_ADDR)-1:0] col_counter_q; 
+  logic [$clog2(quadrilatero_pkg::TILE_ADDR)-1:0] col_counter_d;
 
   enum {
     LSU_READY,
@@ -128,24 +133,44 @@ module quadrilatero_lsu #(
 
   always_comb begin : ctrl_block
     terminate         = (|rows_q == '0 && |cols_q == '0 && data_gnt_i && data_req_o && (lsu_state_q == LSU_RUNNING)); 
-    load_fifo_valid_o = rd_valid_d;
+    load_fifo_valid_o = rd_valid_d | rd_valid_q;
     busy_o            = (lsu_state_q == LSU_RUNNING) & ~terminate;
     terminate_o       = terminate;
   end
 
   always_comb begin : addr_block
     src_ptr_inc = DATA_WIDTH / 8;
-    addr_op2    = (cols_q == '0)      ? stride_i  : src_ptr_inc;
-    addr        = (start_i || ((rows_q == rows_i - 1) && (cols_q == cols_i - 1)))  ? src_ptr_i : ptr_q + addr_op2;
+    addr_op2    = (stride_i * row_counter_q) + (src_ptr_inc * col_counter_q);
+    addr        = (start_i || ((rows_q == rows_i - 1) && (cols_q == cols_i - 1)))  ? src_ptr_i : src_ptr_i + addr_op2;
     ptr_d       = (data_gnt_i && data_req_o) ? addr : ptr_q; 
   end
 
   always_comb begin : counters_block 
       rows_d = rows_q;
       cols_d = cols_q;
+      row_counter_d = row_counter_q;
+      col_counter_d = col_counter_q;
 
       if(start_i) begin
         if(data_gnt_i && data_req_o) begin
+          if(quadrilatero_pkg::TILE_ADDR != 0) begin
+          if(col_counter_q == LastCol) begin
+            col_counter_d = '0;
+            if(row_counter_q == LastRow) begin
+              row_counter_d = '0;
+            end else begin
+              row_counter_d = row_counter_q + 1;
+            end
+          end else begin
+            col_counter_d = col_counter_d + 1;
+          end
+          end else begin
+            if(row_counter_q == LastRow) begin
+                row_counter_d = '0;
+              end else begin
+                row_counter_d = row_counter_q + 1;
+              end
+          end
           if(cols_i > 1) begin
             rows_d = rows_i - 1;
             cols_d = cols_i - 2;
@@ -158,6 +183,24 @@ module quadrilatero_lsu #(
           cols_d = cols_i - 1;
         end
       end else if (data_gnt_i && data_req_o) begin
+        if(quadrilatero_pkg::TILE_ADDR != 0) begin
+          if(col_counter_q == LastCol) begin
+            col_counter_d = '0;
+            if(row_counter_q == LastRow) begin
+              row_counter_d = '0;
+            end else begin
+              row_counter_d = row_counter_q + 1;
+            end
+          end else begin
+            col_counter_d = col_counter_d + 1;
+          end
+        end else begin
+          if(row_counter_q == LastRow) begin
+              row_counter_d = '0;
+            end else begin
+              row_counter_d = row_counter_q + 1;
+            end
+        end
         if (cols_q > 0) cols_d = cols_q - 1;
         else if (rows_q > 0) begin
           cols_d = cols_i - 1;
@@ -296,6 +339,8 @@ module quadrilatero_lsu #(
       rd_head_q         <= '0       ;
       rd_valid_q        <= '0       ;
       data_we_q         <= '0       ;
+      row_counter_q     <= '0       ;
+      col_counter_q    <= '0       ;
     end else begin
       lsu_state_q       <= lsu_state_d;
       ptr_q             <= ptr_d      ;
@@ -304,7 +349,9 @@ module quadrilatero_lsu #(
       rd_head_q         <= rd_head_d  ;
       rd_valid_q        <= rd_valid_d ;
       data_we_q         <= data_we_d  ;
+      row_counter_q     <= row_counter_d;
+      col_counter_q     <= col_counter_d;
     end
   end
 
-endmodule
+endmodule