This project is about the designing of Instruction word register of 32 bit which is a structure containing opcode of enumerated types and operands.The verification of the design is done by creating layered testbenches using the concept of test environment which includes generator, driver, monitor etc. in system verilog. The functionality of the design is approved through functional coverage.
Hardware Language used for DUT: System Verilog.
Hardware Language used for Verification: System Verilog.
EDA tool: Questasim Advanced Simulator.
Operating System: Red Hat Linux 7.