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VesPA ( Very Simple Processor Architecture) ISA implementation using Xilinx Vivado. The implementation also includes a byte-addressable memory wrapped in 4 BRAMs, an interrupt controller, an address bus, a data bus, and a DMA in the FPGA.
Algergiulhia/VeSPA
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VesPA ( Very Simple Processor Architecture) ISA implementation using Xilinx Vivado. The implementation also includes a byte-addressable memory wrapped in 4 BRAMs, an interrupt controller, an address bus, a data bus, and a DMA in the FPGA.
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