Processor Design and Simulation

This project simulates a fictional processor design and architecture using C. It demonstrates the implementation of a processor pipeline, memory architecture, register management, instruction parsing, and execution control.

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Table of Contents

• Project Overview

• Processor Packages

  • Package 1 – Von Neumann Architecture

• Instruction Set Architecture

• Data Path & Pipeline

• Program Execution

• Branches, Jumps, and PC Management

• Overflow and Carry Flags

• Deliverables

• Evaluation and Grading

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Project Overview

The goal of this project is to design and simulate a processor, implementing the following concepts:

• Processor Architecture: Defines memory organization, registers, and instruction execution.
• Instruction Set: Implements arithmetic, logical, memory, and branch instructions.
• Pipeline Stages: Simulates instruction execution stages: Fetch, Decode, Execute, Memory, Write Back.
• Memory & Register Management: Handles main memory, general-purpose registers, and program counter (PC).
• Branching & Jumping Logic: Correctly updates PC for conditional and unconditional instructions.

The project uses C programming for simulating the processor, parsing assembly instructions, and executing a pipelined architecture.

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Project Structure & Code Organization

Directory Layout

├── include/
│   ├── cpu.h
│   ├── cpu_state.h
│   ├── instruction_utils.h
│   ├── loader.h
│   ├── memory.h
│   └── pipeline_utils.h
│
├── src/
│   ├── main.c
│   ├── cpu.c
│   ├── cpu_state.c
│   ├── instruction_utils.c
│   ├── loader.c
│   └── pipeline_utils.c
│
└── instrTest.txt

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Directory Responsibilities

include/ — Public Interfaces (Headers)

This directory contains all public interfaces of the processor simulator. Each header exposes function prototypes, shared data structures, and global state declarations (extern) used across modules.

Headers are intentionally logic-free, ensuring clean separation between interface and implementation.

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src/ — Implementation

This directory contains the actual processor simulation logic, split into cohesive modules that mirror real processor subsystems.

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File-Level Breakdown

main.c

Role: Program entry point and simulation launcher.

Responsibilities:

• Allocates main memory
• Initializes processor state
• Loads assembly instructions
• Starts the clock-cycle simulation
• Prints final register and memory state

main.c does not implement CPU logic. It orchestrates execution by calling into the CPU and pipeline modules.

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cpu.h / cpu.c

Role: Core processor execution and pipeline control.

Responsibilities:

• Implements the processor pipeline stages:

  • Fetch
  • Decode
  • Execute
  • Memory
  • Write Back

• Controls clock-cycle progression

• Enforces pipeline constraints:

  • Limited parallelism (4 instructions max)
  • Memory access conflicts (IF vs MEM)
  • Stalling and flushing behavior

This module represents the heart of the processor simulation.

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cpu_state.h / cpu_state.c

Role: Global processor state and architectural data.

Responsibilities:

• Program Counter (PC)
• Register file (R0–R31)
• Instruction memory & data memory
• Pipeline tracking arrays
• Instruction metadata (instructionData struct)

All processor state is defined once in cpu_state.c and accessed across modules via extern declarations.

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instruction_utils.h / instruction_utils.c

Role: Instruction decoding and formatting utilities.

Responsibilities:

• Convert binary instructions to human-readable assembly
• Map opcodes to mnemonic strings
• Identify instruction categories (LW, SW, branch, jump, etc.)
• Support debug printing per pipeline stage

This module is used extensively for logging, debugging, and pipeline tracing.

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loader.h / loader.c

Role: Instruction loading and assembly parsing.

Responsibilities:

• Read assembly instructions from input text file
• Parse instruction formats (R-type, I-type, J-type)
• Encode instructions into 32-bit binary format
• Store instructions into instruction memory

This simulates the instruction loading phase of a real processor.

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pipeline_utils.h / pipeline_utils.c

Role: Pipeline control helpers and hazard handling.

Responsibilities:

• Instruction flushing after branches/jumps
• PC manipulation helpers
• Dependency and hazard-related utilities
• Bit manipulation helpers (e.g., jump address concatenation)

This module supports correct pipeline behavior under control hazards.

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memory.h

Role: Memory interface abstraction.

Responsibilities:

• Declares main memory pointer
• Centralizes memory-related constants and definitions
• Ensures consistent memory access across modules

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Design Philosophy

• Modular: Each file maps to a real processor subsystem
• Scalable: Easy to extend with new instructions or pipeline features
• Readable: Debug-friendly with detailed per-cycle output
• Professional: Separation of concerns mirrors real CPU simulators

This structure was intentionally chosen to resemble industry-grade architectural simulators, rather than monolithic academic code.

Processor Packages

Package 1 – Spicy Von Neumann Fillet

Architecture

• Von Neumann Architecture: Both instructions and data share the same memory.

Memory

• Size: 2048 × 32 bits (2048 words, 4 bytes each)

• Address Range: 0–2047

  • 0–1023: Instruction memory
  • 1024–2047: Data memory

• Word Addressable: Each memory block stores 1 word

Registers

• Total: 33 registers (32 bits each)

  • 31 General-Purpose Registers (R1–R31)
  • 1 Zero Register (R0, always 0, cannot be overwritten)
  • 1 Program Counter (PC)

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Instruction Set Architecture

Instruction Details

• Instruction Size: 32 bits

• Instruction Types: 3

• Instruction Count: 12 (opcodes 0–11)

• Special Instructions:

  • Shift operations (SLL, SRL) ignore R3 in format

• Encoding: Concatenation of binary fields (e.g., 0100 || 1100 = 01001100)

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Data Path & Pipeline

Pipeline Stages

All instructions pass through 5 stages, regardless of type:

1. Instruction Fetch (IF): Fetch instruction from memory using PC, then increment PC.
2. Instruction Decode (ID): Decode instruction, read operands from registers.
3. Execute (EX): Perform ALU operations.
4. Memory (MEM): Access memory for load/store operations.
5. Write Back (WB): Write results to destination registers.

Pipeline Rules:

• Maximum 4 instructions in parallel
• IF and MEM cannot be simultaneous due to memory access conflict
• Clock cycles formula: 7 + ((n − 1) × 2) where n = number of instructions

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Program Execution

Execution Flow

• Instructions are written in assembly in a text file.
• Parsing: Instructions are parsed and stored in instruction memory in binary/decimal form.
• Clock Cycle Simulation: Increment variable after completing active stages.
• Stage Execution Example (C):

Fetch();
Decode();
Execute();
Memory();
WriteBack();
Cycle++;

• Printing Requirements per Cycle:

  • Clock cycle number
  • Active pipeline stages and instructions
  • Input/output values of stages
  • Updated registers and memory values

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Branches, Jumps, and PC Management

Conditional & Unconditional Branches

• Conditional Branches:

  • PC = PC + 1 + IMM (immediate offset)
  • Instructions after branch in pipeline are flushed if branch taken

• Unconditional Jumps:

  • PC updated during Execute stage
  • Instructions fetched after branch/jump are dropped

• Package-Specific Timing:

  • Packages 1 & 3: Fetch new instruction after 2-cycle Execute stage
  • Packages 2 & 4: Fetch immediately after Execute stage

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Overflow and Carry Flags

Flag Handling

• Overflow: Occurs when the signed result exceeds the representable range.
• Carry: Occurs when unsigned operations exceed max representable value.

Detection:

• Overflow: XOR last two carry bits
• Carry: Check 9th bit of result

Examples:

1. Overflow & Carry: -128 + -128 = -256 → Overflow = 1, Carry = 1
2. Carry without Overflow: 64 + -64 = 0 → Overflow = 0, Carry = 1
3. Overflow without Carry: 64 + 64 = 128 → Overflow = 1, Carry = 0