alu.v

`include "ctrl_encode_def.v"

module alu(A, B, ALUOp, C, Zero);
   input  signed [31:0] A, B;
   input         [4:0]  ALUOp;
   output signed [31:0] C;
   output Zero;  //condition flag: set if condition is true for B-type instruction
   
   reg [31:0] C;
   integer    i;
   reg ZF;
   /// beq 001
   /// bne 010
   /// blt 011
   /// bge 100
   /// bltu 101
   /// bgeu 110
   always @( * ) begin
      case ( ALUOp )
        `ALUOp_lui:begin C=B;ZF=0;end
        `ALUOp_add:begin C=A+B;ZF=0; end
        `ALUOp_sub:
		begin
			C=A-B;
			ZF=0;
			if (C==0)
				ZF = 1;
		end  //and beq
        `ALUOp_xor:begin C=A^B;ZF=0; end // xori
        `ALUOp_or:begin C=A|B;ZF=0;end // ori
        `ALUOp_and:begin C=A&B;ZF=0;end // andi
        `ALUOp_sll:begin C=A<<B;ZF=0;end // slli
        `ALUOp_srl:begin C=A>>B; ZF=0;end // srli
        `ALUOp_sra:begin C=A>>>B; ZF=0;end // srai
		`ALUOp_slt:begin C=A<B?1:32'b0;ZF=0;end // 包含slti
        `ALUOp_sltu:begin C=$unsigned(A)<$unsigned(B)?1:32'b0;ZF=0;end // 包含sltiu 
		`ALUOp_bne:begin 
			C=A-B;
			ZF=0;
			if (C!=0)
				ZF=1;
			end
		`ALUOp_blt:begin 
			C=A<B?1:32'b0;
			ZF=0;
			if (C==1)
				ZF=1;
			end
		`ALUOp_bge:begin 
			C=A>B?1:32'b0;
			ZF=0;
			if (C==1)
				ZF=1;
			end
		`ALUOp_bltu:begin 
			C=$unsigned(A)<$unsigned(B)?1:32'b0;
			ZF=0;
			if (C==1)
				ZF=1;
			end
		`ALUOp_bgeu:begin 
			C=$unsigned(A)>=$unsigned(B)?1:32'b0;
			ZF=0;
			if (C==1)
				ZF=1;
			end
        default: begin C=A;ZF=0; end
      endcase
   end 
   
   assign Zero = ZF;


endmodule