ad7172_2.cpp

#include "ad7172_2.h"

AD7172_2::AD7172_2(uint8_t cs_pin, uint8_t drdy_pin)
: _cs(cs_pin), _drdy(drdy_pin), _spi(nullptr),
  _settings(1000000, MSBFIRST, SPI_MODE3), _crcMode(CRC_OFF), _dataStat(false) {}


bool AD7172_2::begin(SPIClass &spi, uint32_t spi_hz) {
  _spi = &spi;
  _settings = SPISettings(spi_hz, MSBFIRST, SPI_MODE3);

  pinMode(_cs, OUTPUT);
  csHigh();

  if (_drdy != 255) pinMode(_drdy, INPUT);

  _spi->begin();

  // Datasheet reset: 64 SCLKs with CS low and DIN high (0xFF bytes).
  // Then wait ~500us before access. :contentReference[oaicite:2]{index=2}
  _spi->beginTransaction(_settings);
  csLow();
  for (int i = 0; i < 8; ++i) _spi->transfer(0xFF);
  csHigh();
  _spi->endTransaction();
  delayMicroseconds(600);

  // Make reads safer on MCUs: hold DOUT in "data" state until CS rises (DOUT_RESET=1)
  // (This is optional but generally helps framing).
  uint16_t ifmode = 0;
  if (!readReg16(REG_IFMODE, ifmode)) return false;

  // Cache current DATA_STAT state
  _dataStat = (ifmode & (1u << 6)) != 0;

  // Keep framed reads sane
  ifmode |= IFMODE_DOUT_RESET;
  if (!writeReg16(REG_IFMODE, ifmode)) return false;

  return true;
}

void AD7172_2::setCrcMode(CrcMode mode) {
  // Keep a copy of what the chip currently expects on the wire.
  CrcMode old = _crcMode;

  // IMPORTANT:
  // - If enabling CRC (OFF -> CRC), the enabling write MUST be sent WITHOUT CRC.
  // - If disabling CRC (CRC -> OFF), the disabling write MUST be sent WITH CRC.
  //
  // This matches "checksum appended" behaviour only when enabled. :contentReference[oaicite:3]{index=3}

  // Temporarily use the *old* mode for the transaction
  _crcMode = old;

  uint16_t ifmode = 0;
  if (!readReg16(REG_IFMODE, ifmode)) return;

  ifmode &= ~IFMODE_CRC_EN_MASK;
  ifmode |= (uint16_t(mode) << 2); // CRC_EN bits :contentReference[oaicite:4]{index=4}

  // Write IFMODE using the framing the chip currently expects
  if (!writeReg16(REG_IFMODE, ifmode)) return;

  // Now that the chip has latched the new CRC mode, update our local mode
  _crcMode = mode;

  // Optional: clear CRC_ERROR flag by reading STATUS if you want
  // uint8_t st; readReg(REG_STATUS, &st, 1);
}

bool AD7172_2::setDataStat(bool enable) {
  uint16_t ifmode = 0;
  if (!readReg16(REG_IFMODE, ifmode)) return false;

  // IFMODE.DATA_STAT is bit 6 (append STATUS to DATA reads)
  if (enable) ifmode |= (1u << 6);
  else        ifmode &= (uint16_t)~(1u << 6);

  if (!writeReg16(REG_IFMODE, ifmode)) return false;

  _dataStat = enable;
  return true;
}

uint8_t AD7172_2::makeCommsByte(bool read, uint8_t addr) {
  // COMMS: [7]=WEN (must be 0), [6]=R/W, [5:0]=RA :contentReference[oaicite:4]{index=4}
  return (0u << 7) | (uint8_t(read) << 6) | (addr & 0x3F);
}

// ---- checksum helpers ----

// CRC polynomial x^8 + x^2 + x + 1 (poly 0x07). :contentReference[oaicite:5]{index=5}
uint8_t AD7172_2::crc8_poly07(const uint8_t *data, size_t len) {
  uint8_t crc = 0x00;
  for (size_t i = 0; i < len; i++) {
    crc ^= data[i];
    for (int b = 0; b < 8; b++) {
      if (crc & 0x80) crc = (uint8_t)((crc << 1) ^ 0x07);
      else           crc = (uint8_t)(crc << 1);
    }
  }
  return crc;
}

uint8_t AD7172_2::xor8(const uint8_t *data, size_t len) {
  uint8_t x = 0;
  for (size_t i = 0; i < len; i++) x ^= data[i];
  return x;
}

// ---- raw register access ----
// Note: checksum is appended to end of each read/write transaction. :contentReference[oaicite:6]{index=6}
bool AD7172_2::writeReg(uint8_t addr, const uint8_t *buf, size_t len) {
  if (!_spi || !buf || len == 0) return false;

  uint8_t cmd = makeCommsByte(false, addr);

  // Build checksum input: command + data (8-bit to 24-bit typically). :contentReference[oaicite:7]{index=7}
  uint8_t chk_in[1 + 32];
  if (len > 32) return false;
  chk_in[0] = cmd;
  memcpy(&chk_in[1], buf, len);

  uint8_t crc = 0;
  bool use_crc = (_crcMode == CRC_XOR_READ) || (_crcMode == CRC_CRC8);
  // When CRC_EN=01: writes still use polynomial CRC. :contentReference[oaicite:8]{index=8}
  if (use_crc) crc = crc8_poly07(chk_in, 1 + len);

  _spi->beginTransaction(_settings);
  csLow();

  _spi->transfer(cmd);
  for (size_t i = 0; i < len; i++) _spi->transfer(buf[i]);
  if (use_crc) _spi->transfer(crc);

  csHigh();
  _spi->endTransaction();
  return true;
}

bool AD7172_2::readReg(uint8_t addr, uint8_t *buf, size_t len) {
  if (!_spi || !buf || len == 0) return false;

  uint8_t cmd = makeCommsByte(true, addr);

  _spi->beginTransaction(_settings);
  csLow();

  _spi->transfer(cmd);

  // Read payload
  for (size_t i = 0; i < len; i++) buf[i] = _spi->transfer(0x00);

  // Optional checksum byte at end of read
  if (_crcMode != CRC_OFF) {
    uint8_t got = _spi->transfer(0x00);

    // checksum input: command + data output (8 to 32 bits). :contentReference[oaicite:9]{index=9}
    uint8_t chk_in[1 + 32];
    if (len > 32) { csHigh(); _spi->endTransaction(); return false; }
    chk_in[0] = cmd;
    memcpy(&chk_in[1], buf, len);

    uint8_t expect = 0;
    if (_crcMode == CRC_XOR_READ) {
      // XOR is allowed for reads when CRC_EN=01. :contentReference[oaicite:10]{index=10}
      expect = xor8(chk_in, 1 + len);
    } else {
      expect = crc8_poly07(chk_in, 1 + len);
    }

    csHigh();
    _spi->endTransaction();
    return (got == expect);
  }

  csHigh();
  _spi->endTransaction();
  return true;
}

// ---- small typed helpers ----
bool AD7172_2::readReg16(uint8_t addr, uint16_t &val) {
  uint8_t b[2];
  if (!readReg(addr, b, 2)) return false;
  val = (uint16_t(b[0]) << 8) | b[1];
  return true;
}

bool AD7172_2::writeReg16(uint8_t addr, uint16_t val) {
  uint8_t b[2] = { uint8_t(val >> 8), uint8_t(val & 0xFF) };
  return writeReg(addr, b, 2);
}

bool AD7172_2::readModifyWrite16(uint8_t addr, uint16_t clearMask, uint16_t setMask) {
  uint16_t v = 0;
  if (!readReg16(addr, v)) return false;
  v = (uint16_t)((v & ~clearMask) | setMask);
  return writeReg16(addr, v);
}

// ---- DATA read ----
bool AD7172_2::readData24(uint32_t &code) {
  if (_dataStat) {
    uint8_t status;
    return readData24(code, status);
  }

  uint8_t b[3];
  if (!readReg(REG_DATA, b, 3)) return false;
  code = (uint32_t(b[0]) << 16) | (uint32_t(b[1]) << 8) | b[2];
  return true;
}

bool AD7172_2::readData24(uint32_t &code, uint8_t &status) {
  // When DATA_STAT=1, DATA read returns 3 data bytes + 1 status byte
  uint8_t b[4];
  if (!readReg(REG_DATA, b, 4)) return false;

  code = (uint32_t(b[0]) << 16) | (uint32_t(b[1]) << 8) | b[2];
  status = b[3];
  return true;
}

// ---- GPIO control ----
// GPIO0/GPIO1 enabled using IP_EN0/IP_EN1 or OP_EN0/OP_EN1,
// read/write via GP_DATA0/GP_DATA1. :contentReference[oaicite:11]{index=11}

bool AD7172_2::gpio0AsInput(bool en)  { return readModifyWrite16(REG_GPIOCON, GPIOCON_IP_EN0, en ? GPIOCON_IP_EN0 : 0); }
bool AD7172_2::gpio1AsInput(bool en)  { return readModifyWrite16(REG_GPIOCON, GPIOCON_IP_EN1, en ? GPIOCON_IP_EN1 : 0); }
bool AD7172_2::gpio0AsOutput(bool en) { return readModifyWrite16(REG_GPIOCON, GPIOCON_OP_EN0, en ? GPIOCON_OP_EN0 : 0); }
bool AD7172_2::gpio1AsOutput(bool en) { return readModifyWrite16(REG_GPIOCON, GPIOCON_OP_EN1, en ? GPIOCON_OP_EN1 : 0); }

bool AD7172_2::gpioWrite0(bool level) {
  return readModifyWrite16(REG_GPIOCON, GPIOCON_GP_DATA0, level ? GPIOCON_GP_DATA0 : 0);
}
bool AD7172_2::gpioWrite1(bool level) {
  return readModifyWrite16(REG_GPIOCON, GPIOCON_GP_DATA1, level ? GPIOCON_GP_DATA1 : 0);
}

bool AD7172_2::gpioRead0(bool &level) {
  uint16_t v = 0;
  if (!readReg16(REG_GPIOCON, v)) return false;
  level = (v & GPIOCON_GP_DATA0) != 0; // GP_DATA0 bit :contentReference[oaicite:12]{index=12}
  return true;
}
bool AD7172_2::gpioRead1(bool &level) {
  uint16_t v = 0;
  if (!readReg16(REG_GPIOCON, v)) return false;
  level = (v & GPIOCON_GP_DATA1) != 0; // GP_DATA1 bit :contentReference[oaicite:13]{index=13}
  return true;
}

// ---- SYNC/ERROR as GPIO output ----
// ERR_EN=11 -> general-purpose output, driven by ERR_DAT bit. :contentReference[oaicite:14]{index=14}
bool AD7172_2::syncErrorAsGpioOutput(bool enable) {
  if (enable) {
    return readModifyWrite16(REG_GPIOCON, GPIOCON_ERR_EN_MASK, GPIOCON_ERR_EN_GPIO_OUT);
  } else {
    return readModifyWrite16(REG_GPIOCON, GPIOCON_ERR_EN_MASK, GPIOCON_ERR_EN_DISABLED);
  }
}

bool AD7172_2::syncErrorWrite(bool level) {
  return readModifyWrite16(REG_GPIOCON, GPIOCON_ERR_DAT, level ? GPIOCON_ERR_DAT : 0);
}