From f166087ab9a895f3e03dad667fb563c50dfeb597 Mon Sep 17 00:00:00 2001 From: Chris Vig Date: Sat, 30 Aug 2025 10:34:03 -0500 Subject: [PATCH] Updates for prototype PCB build. --- configuration.cmake | 6 +++--- src/main/application/led.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configuration.cmake b/configuration.cmake index 828cd56..04b41d6 100644 --- a/configuration.cmake +++ b/configuration.cmake @@ -21,7 +21,7 @@ add_compile_definitions( # -- Feature Options -- # Define values -set(FEATURE_OPT_DEBUG_PORT_BAUD USART_BAUD_38400 +set(FEATURE_OPT_DEBUG_PORT_BAUD USART_BAUD_19200 CACHE STRING "Baud rate for debug port. (usart_baud_t)") # Set compile definitions @@ -60,11 +60,11 @@ set(CONFIG_DFLT_IO_TYPE_TRS_1_RING IO_TYPE_INPUT_PADDLE_RIGHT CACHE STRING "I/O type for the ring of TRS 1. (io_type_t)") set(CONFIG_DFLT_IO_POLARITY_TRS_1_RING IO_POLARITY_ACTIVE_LOW CACHE STRING "I/O polarity for the ring of TRS 1. (io_polarity_t)") -set(CONFIG_DFLT_IO_TYPE_TRS_2_TIP IO_TYPE_NONE +set(CONFIG_DFLT_IO_TYPE_TRS_2_TIP IO_TYPE_INPUT_PADDLE_LEFT CACHE STRING "I/O type for the tip of TRS 2. (io_type_t)") set(CONFIG_DFLT_IO_POLARITY_TRS_2_TIP IO_POLARITY_ACTIVE_LOW CACHE STRING "I/O polarity for the tip of TRS 2. (io_polarity_t)") -set(CONFIG_DFLT_IO_TYPE_TRS_2_RING IO_TYPE_NONE +set(CONFIG_DFLT_IO_TYPE_TRS_2_RING IO_TYPE_INPUT_PADDLE_RIGHT CACHE STRING "I/O type for the ring of TRS 2. (io_type_t)") set(CONFIG_DFLT_IO_POLARITY_TRS_2_RING IO_POLARITY_ACTIVE_LOW CACHE STRING "I/O polarity for the ring of TRS 2. (io_polarity_t)") diff --git a/src/main/application/led.c b/src/main/application/led.c index 4b6c09f..a6fc561 100644 --- a/src/main/application/led.c +++ b/src/main/application/led.c @@ -24,7 +24,7 @@ static gpio_pin_t const s_gpio_tbl[] = { // Must be in same order as led_t enum - GPIO_PIN_D7, /* LED_STATUS */ + GPIO_PIN_C0, /* LED_STATUS */ GPIO_PIN_D6, /* LED_KEY */ }; _Static_assert( array_count( s_gpio_tbl ) == LED_COUNT, "Invalid GPIO table!" );