diff --git a/aivotta/hdb/fugen.hdb b/aivotta/hdb/fugen.hdb index 8c83b44..570641d 100644 Binary files a/aivotta/hdb/fugen.hdb and b/aivotta/hdb/fugen.hdb differ diff --git a/aivotta/hdb/fugen/vhdl/ld1024-post-op.vhd b/aivotta/hdb/fugen/vhdl/ld1024-post-op.vhd new file mode 100644 index 0000000..da415cf --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ld1024-post-op.vhd @@ -0,0 +1 @@ +op2 <= rdata_out_1; diff --git a/aivotta/hdb/fugen/vhdl/ld32-post-op.vhd b/aivotta/hdb/fugen/vhdl/ld32-post-op.vhd new file mode 100644 index 0000000..7d9f8a0 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ld32-post-op.vhd @@ -0,0 +1,2 @@ +op2 <= (others => '0'); +op2(31 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1(6 downto 2)))*32+31 downto to_integer(unsigned(addr_low_out_1(6 downto 2)))*32); diff --git a/aivotta/hdb/fugen/vhdl/ld512-post-op.vhd b/aivotta/hdb/fugen/vhdl/ld512-post-op.vhd new file mode 100644 index 0000000..df16cd4 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ld512-post-op.vhd @@ -0,0 +1,6 @@ +op2 <= (others => '0'); +if addr_low_out_1(6) = '0' then + op2(512 downto 0) <= rdata_out_1(511 downto 0); +else + op2(512 downto 0) <= rdata_out_1(1023 downto 512); +end if; diff --git a/aivotta/hdb/fugen/vhdl/ldu16-post-op.vhd b/aivotta/hdb/fugen/vhdl/ldu16-post-op.vhd new file mode 100644 index 0000000..4f06a2b --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ldu16-post-op.vhd @@ -0,0 +1,2 @@ +op2 <= (others => '0'); +op2(15 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1(7 downto 1)))*16+15 downto to_integer(unsigned(addr_low_out_1(7 downto 1)))*16); diff --git a/aivotta/hdb/fugen/vhdl/ldu8-post-op.vhd b/aivotta/hdb/fugen/vhdl/ldu8-post-op.vhd new file mode 100644 index 0000000..e4ac378 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ldu8-post-op.vhd @@ -0,0 +1,2 @@ +op2 <= (others => '0'); +op2(7 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1))*8+7 downto to_integer(unsigned(addr_low_out_1))*8); diff --git a/aivotta/hdb/fugen/vhdl/ldxx.vhd b/aivotta/hdb/fugen/vhdl/ldxx.vhd new file mode 100644 index 0000000..0d3f12e --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/ldxx.vhd @@ -0,0 +1,3 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '0'; diff --git a/aivotta/hdb/fugen/vhdl/lsu_defaults.vhd b/aivotta/hdb/fugen/vhdl/lsu_defaults.vhd new file mode 100644 index 0000000..a460a66 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/lsu_defaults.vhd @@ -0,0 +1,15 @@ +avalid_in_1 <= '0'; +awren_in_1 <= '0'; +aaddr_in_1 <= (others => '0'); +astrb_in_1 <= (others => '0'); +adata_in_1 <= (others => '0'); +avalid_out(0) <= avalid_out_1; +aready_in_1 <= aready_in(0); +aaddr_out <= aaddr_out_1; +awren_out(0) <= awren_out_1; +astrb_out <= astrb_out_1; +adata_out <= adata_out_1; +rvalid_in_1 <= rvalid_in(0); +rready_out(0) <= rready_out_1; +rdata_in_1 <= rdata_in; +glockreq <= glockreq_out_1; \ No newline at end of file diff --git a/aivotta/hdb/fugen/vhdl/lsu_registers.vhdl b/aivotta/hdb/fugen/vhdl/lsu_registers.vhdl new file mode 100644 index 0000000..ee308a0 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/lsu_registers.vhdl @@ -0,0 +1,181 @@ +-- Copyright (c) 2017 Tampere University. +-- +-- This file is part of TTA-Based Codesign Environment (TCE). +-- +-- Permission is hereby granted, free of charge, to any person obtaining a +-- copy of this software and associated documentation files (the "Software"), +-- to deal in the Software without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Software, and to permit persons to whom the +-- Software is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +-- DEALINGS IN THE SOFTWARE. +------------------------------------------------------------------------------- +-- Title : LSU interface registers +------------------------------------------------------------------------------- +-- File : lsu_registers.vhdl +-- Author : Kati Tervo +-- Company : +-- Created : 2019-08-27 +-- Last update: 2019-08-27 +-- Platform : +------------------------------------------------------------------------------- +-- Description: LSU interface, handling registers and locking +-- +-- Revisions : +-- Date Version Author Description +-- 2019-08-27 1.0 katte Created +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.math_real.all; + +entity lsu_registers is + generic ( + dataw_g : integer := 32; + low_bits_g : integer := 2; + addrw_g : integer := 11 + ); + port( + clk : in std_logic; + rstx : in std_logic; + glock_in : in std_logic; + glockreq_out : out std_logic; + + avalid_in : in std_logic; + awren_in : in std_logic; + aaddr_in : in std_logic_vector(addrw_g-1 downto 0); + astrb_in : in std_logic_vector(dataw_g/8-1 downto 0); + adata_in : in std_logic_vector(dataw_g-1 downto 0); + + avalid_out : out std_logic; + aready_in : in std_logic; + aaddr_out : out std_logic_vector(addrw_g-low_bits_g-1 downto 0); + awren_out : out std_logic; + astrb_out : out std_logic_vector(dataw_g/8-1 downto 0); + adata_out : out std_logic_vector(dataw_g-1 downto 0); + + rvalid_in : in std_logic; + rready_out : out std_logic; + + rdata_in : in std_logic_vector(dataw_g-1 downto 0); + rdata_out : out std_logic_vector(dataw_g-1 downto 0); + + addr_low_out : out std_logic_vector(low_bits_g-1 downto 0) + ); +end lsu_registers; + +architecture rtl of lsu_registers is + + -- Access channel registers + signal avalid_r : std_logic; + signal aaddr_r : std_logic_vector(aaddr_out'range); + signal awren_r : std_logic; + signal astrb_r : std_logic_vector(astrb_out'range); + signal adata_r : std_logic_vector(adata_out'range); + signal rready_r : std_logic; + signal rready_rr : std_logic; + signal rdata_r : std_logic_vector(rdata_in'range); + + signal addr_low_r, addr_low_rr : std_logic_vector(addr_low_out'range); + + signal fu_glock, glockreq : std_logic; +begin + -- Design-wide assertions + -- coverage off + -- synthesis translate_off + assert low_bits_g = integer(ceil(log2(real(dataw_g/8)))) + report "Incorrect low_bits_g value" + severity failure; + -- coverage on + -- synthesis translate_on + + avalid_out <= avalid_r; + awren_out <= awren_r; + aaddr_out <= aaddr_r; + astrb_out <= astrb_r; + adata_out <= adata_r; + rready_out <= rready_rr; + addr_low_out <= addr_low_rr; + + gen_lockreq : process(rready_rr, rvalid_in, avalid_r, aready_in, + glock_in, glockreq) + begin + if (rready_rr = '1' and rvalid_in = '0') + or (avalid_r = '1' and aready_in = '0') then + glockreq <= '1'; + else + glockreq <= '0'; + end if; + + fu_glock <= glockreq or glock_in; + glockreq_out <= glockreq; + end process gen_lockreq; + + access_channel_sync : process(clk, rstx) + begin + if rstx = '0' then + avalid_r <= '0'; + awren_r <= '0'; + aaddr_r <= (others => '0'); + astrb_r <= (others => '0'); + adata_r <= (others => '0'); + rready_r <= '0'; + rready_rr <= '0'; + addr_low_r <= (others => '0'); + addr_low_rr <= (others => '0'); + elsif rising_edge(clk) then + + if avalid_r = '1' and aready_in = '1' then + avalid_r <= '0'; + end if; + + if rready_rr = '1' and rvalid_in = '1' then + rready_rr <= '0'; + rdata_r <= rdata_in; + end if; + + if fu_glock = '0' then + avalid_r <= avalid_in; + aaddr_r <= aaddr_in(aaddr_in'high downto low_bits_g); + addr_low_r <= aaddr_in(low_bits_g-1 downto 0); + addr_low_rr <= addr_low_r(low_bits_g-1 downto 0); + awren_r <= awren_in; + astrb_r <= astrb_in; + adata_r <= adata_in; + + if avalid_in = '1' and awren_in = '0' then + rready_r <= '1'; + else + rready_r <= '0'; + end if; + + if rready_r = '1' then + rready_rr <= '1'; + end if; + + end if; + end if; + end process access_channel_sync; + + access_channel_comb : process(rready_rr, rvalid_in, rdata_r, rdata_in) + begin + if (rready_rr = '1' and rvalid_in = '1') then + rdata_out <= rdata_in; + else + rdata_out <= rdata_r; + end if; + end process access_channel_comb; + +end rtl; diff --git a/aivotta/hdb/fugen/vhdl/st1024.vhd b/aivotta/hdb/fugen/vhdl/st1024.vhd new file mode 100644 index 0000000..c95d983 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/st1024.vhd @@ -0,0 +1,5 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '1'; +astrb_in_1 <= (others => '1'); +adata_in_1 <= op2; diff --git a/aivotta/hdb/fugen/vhdl/st16.vhd b/aivotta/hdb/fugen/vhdl/st16.vhd new file mode 100644 index 0000000..12aa18d --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/st16.vhd @@ -0,0 +1,7 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '1'; +astrb_in_1 <= (others => '0'); +astrb_in_1(to_integer(unsigned(op1(6 downto 1))*2+1 downto unsigned(op1(6 downto 1))*2)) <= "11"; +adata_in_1 <= (others => '0'); +adata_in_1(to_integer(unsigned(op1(6 downto 1)))*16+15 downto to_integer(unsigned(op1(6 downto 1)))*16) <= op2; diff --git a/aivotta/hdb/fugen/vhdl/st32.vhd b/aivotta/hdb/fugen/vhdl/st32.vhd new file mode 100644 index 0000000..515283e --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/st32.vhd @@ -0,0 +1,7 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '1'; +astrb_in_1 <= (others => '0'); +astrb_in_1(to_integer(unsigned(op1(6 downto 2))*4+3 downto unsigned(op1(6 downto 2))*4)) <= "1111"; +adata_in_1 <= (others => '0'); +adata_in_1(to_integer(unsigned(op1(6 downto 2)))*32+31 downto to_integer(unsigned(op1(6 downto 2)))*32) <= op2; diff --git a/aivotta/hdb/fugen/vhdl/st512.vhd b/aivotta/hdb/fugen/vhdl/st512.vhd new file mode 100644 index 0000000..fe9e511 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/st512.vhd @@ -0,0 +1,10 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '1'; +if op1(6) = '0' then + astrb_in_1 <= (1023 downto 521 => '0', 511 downto 0 => '1'); + adata_in_1 <= (511 downto 0 => '0') & op2; +else + astrb_in_1 <= (1023 downto 521 => '1', 511 downto 0 => '0'); + adata_in_1 <= op2 & (511 downto 0 => '0'); +end if; diff --git a/aivotta/hdb/fugen/vhdl/st8.vhd b/aivotta/hdb/fugen/vhdl/st8.vhd new file mode 100644 index 0000000..3074193 --- /dev/null +++ b/aivotta/hdb/fugen/vhdl/st8.vhd @@ -0,0 +1,7 @@ +avalid_in_1 <= '1'; +aaddr_in_1 <= op1(addrw_c-1 downto 0); +awren_in_1 <= '1'; +astrb_in_1 <= (others => '0'); +astrb_in_1(to_integer(unsigned(op1(6 downto 0)))) <= '1'; +adata_in_1 <= (others => '0'); +adata_in_1(to_integer(unsigned(op1(6 downto 0)))*8+7 downto to_integer(unsigned(op1(6 downto 0)))*8) <= op2; diff --git a/aivotta/hdb/fugen/xml/lsu_1024bit.absDef.1.0.xml b/aivotta/hdb/fugen/xml/lsu_1024bit.absDef.1.0.xml new file mode 100644 index 0000000..fc59656 --- /dev/null +++ b/aivotta/hdb/fugen/xml/lsu_1024bit.absDef.1.0.xml @@ -0,0 +1,118 @@ + + + CPC + interface + lsu_1024bit.absDef + 1.0 + + + + avalid_out + + + required + 1 + out + + 0 + + + + aready_in + + + required + 1 + in + + + + + aaddr_out + + + true + + + required + addrw_c-7 + out + + 0 + + + + awren_out + + + required + 1 + out + + 0 + + + + astrb_out + + + required + 128 + out + + 0 + + + + rvalid_in + + + required + 1 + in + + + + + rready_out + + + required + 1 + out + + 0 + + + + rdata_in + + + true + + + required + 1024 + in + + + + + adata_out + + + true + + + required + 1024 + out + + 0 + + + + + 3,4,0,0 + + diff --git a/aivotta/hdb/fugen/xml/lsu_registers_1024.xml b/aivotta/hdb/fugen/xml/lsu_registers_1024.xml new file mode 100644 index 0000000..0007acf --- /dev/null +++ b/aivotta/hdb/fugen/xml/lsu_registers_1024.xml @@ -0,0 +1,284 @@ + + + ase + flat + lsu_registers + 1.0 + + + + dataw_g + 1024 + + + low_bits_g + 7 + + + addrw_g + addrw_c + + + + + + + flat + + + + + + clk + + + std_logic + + in + + + + rstx + + + std_logic + + in + + + + glock_in + + + std_logic + + in + + + + + glockreq_out + + + std_logic + + out + + + + + avalid_in + + + std_logic + + in + + + + awren_in + + + std_logic + + in + + + + + aaddr_in + + + std_logic_vector + + + + addrw_c-1 + 0 + + + in + + + + astrb_in + + + std_logic_vector + + + + 1024/8-1 + 0 + + + in + + + + adata_in + + + std_logic_vector + + + + 1024-1 + 0 + + + in + + + + + avalid_out + + + std_logic + + out + + + + aready_in + + + std_logic + + in + + + + aaddr_out + + + std_logic_vector + + + + addrw_c-7-1 + 0 + + + out + + + + awren_out + + + std_logic + + out + + + + astrb_out + + + std_logic_vector + + + + 1024/8-1 + 0 + + + out + + + + adata_out + + + std_logic_vector + + + + 1024-1 + 0 + + + out + + + + + rvalid_in + + + std_logic + + in + + + + rready_out + + + std_logic + + out + + + + + + rdata_in + + + std_logic_vector + + + + 1024-1 + 0 + + + in + + + + rdata_out + + + std_logic_vector + + + + 1024-1 + 0 + + + out + + + + + addr_low_out + + + std_logic_vector + + + + 7-1 + 0 + + + out + + + + + + + 3,4,0,0 + + IP + HW + Fixed + + +