From 68b93e4c92aaa3bfff680405852a3a1e2bfc21d7 Mon Sep 17 00:00:00 2001
From: Joao-Pedro-Cabral <miranda.jp@usp.br>
Date: Mon, 15 Dec 2025 14:46:33 +0000
Subject: [PATCH] Fixing multiplier and accumulator block buffers

---
 rtl/vproc_mul.sv       |  3 +++
 rtl/vproc_mul_block.sv | 24 +++++++++++++++++-------
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/rtl/vproc_mul.sv b/rtl/vproc_mul.sv
index f8e3dd28..c8911917 100644
--- a/rtl/vproc_mul.sv
+++ b/rtl/vproc_mul.sv
@@ -353,6 +353,9 @@ module vproc_mul #(
                 .sync_rst_ni  ( sync_rst_ni             ),
                 .op1_i        ( mul_op1    [17*g +: 17] ),
                 .op2_i        ( mul_op2    [17*g +: 17] ),
+                .ops_valid_i  ( state_ex2_ready & state_ex1_valid_q),
+                .mul_valid_i  ( state_ex3_ready & state_ex2_valid_q),
+                .res_valid_i  ( state_res_ready & state_ex3_valid_q),
                 .acc_i        ( mul_acc    [16*g +: 16] ),
                 .acc_flag_i   ( mul_accflag             ),
                 .acc_sub_i    ( mul_accsub              ),
diff --git a/rtl/vproc_mul_block.sv b/rtl/vproc_mul_block.sv
index df74fe08..ba1f2355 100644
--- a/rtl/vproc_mul_block.sv
+++ b/rtl/vproc_mul_block.sv
@@ -16,6 +16,10 @@ module vproc_mul_block #(
         input  logic [16:0]           op1_i,
         input  logic [16:0]           op2_i,
 
+        input  logic                  ops_valid_i,
+        input  logic                  mul_valid_i,
+        input  logic                  res_valid_i,
+
         // note that when operands are buffered, then acc*_i must be delayed by 1 cycle
         input  logic [15:0]           acc_i,
         input  logic                  acc_flag_i, // use accumulator (otherwise it is replaced with 0)
@@ -37,8 +41,10 @@ module vproc_mul_block #(
 
                 if (BUF_OPS) begin
                     always_ff @(posedge clk_i) begin
-                        op1_q <= op1_i;
-                        op2_q <= op2_i;
+                        if(ops_valid_i) begin
+                            op1_q <= op1_i;
+                            op2_q <= op2_i;
+                        end
                     end
                 end else begin
                     always_comb begin
@@ -49,9 +55,11 @@ module vproc_mul_block #(
 
                 if (BUF_MUL) begin
                     always_ff @(posedge clk_i) begin
-                        mul_q     <= mul_d;
-                        acc_q     <= acc_flag_i ? acc_i : '0;
-                        acc_sub_q <= acc_sub_i;
+                        if(mul_valid_i) begin
+                            mul_q     <= mul_d;
+                            acc_q     <= acc_flag_i ? acc_i : '0;
+                            acc_sub_q <= acc_sub_i;
+                        end
                     end
                 end else begin
                     always_comb begin
@@ -63,7 +71,9 @@ module vproc_mul_block #(
 
                 if (BUF_RES) begin
                     always_ff @(posedge clk_i) begin
-                        res_q <= res_d;
+                        if(res_valid_i) begin
+                            res_q <= res_d;
+                        end
                     end
                 end else begin
                     always_comb begin
@@ -72,7 +82,7 @@ module vproc_mul_block #(
                 end
 
                 assign mul_d = $signed(op1_q) * $signed(op2_q);
-                assign res_d = acc_sub_i ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;
+                assign res_d = acc_sub_q ? {17'b0, acc_q} - mul_q : {17'b0, acc_q} + mul_q;
                 assign res_o = res_q;
 
             end