From c1736a501f1e4690351189a092f9f42be89e0a21 Mon Sep 17 00:00:00 2001
From: jaredbfrost <73719801+jaredbfrost@users.noreply.github.com>
Date: Wed, 3 Dec 2025 03:05:40 +0100
Subject: [PATCH] Update microarchitecture.md

---
 docs/microarchitecture.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/microarchitecture.md b/docs/microarchitecture.md
index 85fa52fd5a..e9965d238c 100644
--- a/docs/microarchitecture.md
+++ b/docs/microarchitecture.md
@@ -9,7 +9,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with
   - Each thread has its own register file (32 int + 32 fp registers)
   - Threads execute in parallel
 - **Warps**
-  - A logical clster of threads
+  - A logical cluster of threads
   - Each thread in a warp execute the same instruction
     - The PC is shared; maintain thread mask for Writeback
   - Warp's execution is time-multiplexed at log steps
@@ -80,4 +80,4 @@ Vortex has a 6-stage pipeline:
   - Grouping of sockets sharing L2 cache
 
 ### Vortex Cache Subsystem
-More details about the cache subsystem are provided [here](./cache_subsystem.md).
\ No newline at end of file
+More details about the cache subsystem are provided [here](./cache_subsystem.md).