From 88d124962ebd72547d8f83ff75928f43d884de8d Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 13 Feb 2019 14:55:42 -0800 Subject: [PATCH 1/2] Fixed index offset in mask port mapping. --- macros/src/main/scala/MacroCompiler.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index a51ac629..c1758e02 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -432,7 +432,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]], // zero out the upper bits. zero } else { - if (i >= memPort.src.width.get) { + if (low + i >= memPort.src.width.get) { // If our bit is larger than the whole width of the mem, just zero out the upper bits. zero } else { From b282ae5c0f9339d8e2685ea3e75ba44a774f46cf Mon Sep 17 00:00:00 2001 From: James Dunn Date: Wed, 13 Feb 2019 15:10:22 -0800 Subject: [PATCH 2/2] Parens. --- macros/src/main/scala/MacroCompiler.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala index c1758e02..8604b439 100644 --- a/macros/src/main/scala/MacroCompiler.scala +++ b/macros/src/main/scala/MacroCompiler.scala @@ -432,7 +432,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]], // zero out the upper bits. zero } else { - if (low + i >= memPort.src.width.get) { + if ((low + i) >= memPort.src.width.get) { // If our bit is larger than the whole width of the mem, just zero out the upper bits. zero } else {