From 052c6725803407ebb0828f4249d81b1704fbf8fc Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 8 May 2025 21:25:10 -0700 Subject: [PATCH 01/18] ADD: local CI --- .github/workflows/run-vivado-flow.yaml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 .github/workflows/run-vivado-flow.yaml diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml new file mode 100644 index 0000000..8dea216 --- /dev/null +++ b/.github/workflows/run-vivado-flow.yaml @@ -0,0 +1,23 @@ +name: Run Vivado Flow + +on: + push: + branches: [ "main" ] + pull_request: + branches: [ "main" ] + +jobs: + build: + runs-on: self-hosted + + steps: + - name: Checkout + uses: actions/checkout@v4 + + - name: Set up Vivado + run: source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh + + - name: Run Vivado Flow + run: | + source ./env.sh + make project CONFIG=MlpPolicyRunner From 20d630902aa7f8870e05102ec0e848156da1da53 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 8 May 2025 21:27:44 -0700 Subject: [PATCH 02/18] UPDATE: change mill invocation --- .github/workflows/build-example.yaml | 4 - .github/workflows/run-vivado-flow.yaml | 7 +- .gitignore | 1 - Makefile | 9 +- scripts/install-mill.sh | 10 - scripts/vivado-ecad.sh | 1 - toolchains/mill | 265 +++++++++++++++++++++++++ 7 files changed, 272 insertions(+), 25 deletions(-) delete mode 100755 scripts/install-mill.sh delete mode 100755 scripts/vivado-ecad.sh create mode 100755 toolchains/mill diff --git a/.github/workflows/build-example.yaml b/.github/workflows/build-example.yaml index c6144c8..d3e5f49 100644 --- a/.github/workflows/build-example.yaml +++ b/.github/workflows/build-example.yaml @@ -16,10 +16,6 @@ jobs: # with: # submodules: recursive - - name: Set up Toolchain - run: source $GITHUB_WORKSPACE/scripts/install-mill.sh - - name: Run make verilog run: | - export PATH=$GITHUB_WORKSPACE/toolchains:$PATH make verilog diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index 8dea216..1155a6a 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -14,10 +14,7 @@ jobs: - name: Checkout uses: actions/checkout@v4 - - name: Set up Vivado - run: source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - - - name: Run Vivado Flow + - name: Run Vivado flow on MlpPolicyRunner run: | - source ./env.sh + source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh make project CONFIG=MlpPolicyRunner diff --git a/.gitignore b/.gitignore index b372fed..eb37ad1 100644 --- a/.gitignore +++ b/.gitignore @@ -17,7 +17,6 @@ firmware/*.section firmware/*.symbol # Toolchains -toolchains/mill # Vivado vivado*.jou diff --git a/Makefile b/Makefile index d8224b9..690cf69 100644 --- a/Makefile +++ b/Makefile @@ -4,19 +4,20 @@ PRJ = ChiselProject CONFIG ?= MinimalArty100T +MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - mill -i $(PRJ).runMain GenerateVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(PRJ).runMain GenerateVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) project: verilog - mill -i $(PRJ).runMain GenerateProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(PRJ).runMain GenerateProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) bitstream: project - mill -i $(PRJ).runMain GenerateBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(PRJ).runMain GenerateBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) test: - mill -i $(PRJ).Test + $(MILL_PATH) -i $(PRJ).Test clean: rm -rf $(BUILD_DIR) diff --git a/scripts/install-mill.sh b/scripts/install-mill.sh deleted file mode 100755 index d025405..0000000 --- a/scripts/install-mill.sh +++ /dev/null @@ -1,10 +0,0 @@ -source ./env.sh - -# Install mill -echo "Installing mill..." -echo "Toolchain directory: $TOOLCHAIN_DIR" - -mkdir -p $TOOLCHAIN_DIR - -curl -L https://github.com/com-lihaoyi/mill/releases/download/0.12.3/0.12.3 > $TOOLCHAIN_DIR/mill && chmod +x $TOOLCHAIN_DIR/mill -export PATH="$TOOLCHAIN_DIR:$PATH" diff --git a/scripts/vivado-ecad.sh b/scripts/vivado-ecad.sh deleted file mode 100755 index 2088b4e..0000000 --- a/scripts/vivado-ecad.sh +++ /dev/null @@ -1 +0,0 @@ -source /ecad/tools/xilinx/Vivado/2023.2/settings64.sh diff --git a/toolchains/mill b/toolchains/mill new file mode 100755 index 0000000..f868036 --- /dev/null +++ b/toolchains/mill @@ -0,0 +1,265 @@ +#!/usr/bin/env sh + +# This is a wrapper script, that automatically download mill from GitHub release pages +# You can give the required mill version with --mill-version parameter +# If no version is given, it falls back to the value of DEFAULT_MILL_VERSION +# +# Original Project page: https://github.com/lefou/millw +# Script Version: 0.4.12 +# +# If you want to improve this script, please also contribute your changes back! +# +# Licensed under the Apache License, Version 2.0 + +set -e + +if [ -z "${DEFAULT_MILL_VERSION}" ] ; then + DEFAULT_MILL_VERSION=0.12.10 +fi + + +if [ -z "${GITHUB_RELEASE_CDN}" ] ; then + GITHUB_RELEASE_CDN="" +fi + + +MILL_REPO_URL="https://github.com/com-lihaoyi/mill" + +if [ -z "${CURL_CMD}" ] ; then + CURL_CMD=curl +fi + +# Explicit commandline argument takes precedence over all other methods +if [ "$1" = "--mill-version" ] ; then + shift + if [ "x$1" != "x" ] ; then + MILL_VERSION="$1" + shift + else + echo "You specified --mill-version without a version." 1>&2 + echo "Please provide a version that matches one provided on" 1>&2 + echo "${MILL_REPO_URL}/releases" 1>&2 + false + fi +fi + +# Please note, that if a MILL_VERSION is already set in the environment, +# We reuse it's value and skip searching for a value. + +# If not already set, read .mill-version file +if [ -z "${MILL_VERSION}" ] ; then + if [ -f ".mill-version" ] ; then + MILL_VERSION="$(tr '\r' '\n' < .mill-version | head -n 1 2> /dev/null)" + elif [ -f ".config/mill-version" ] ; then + MILL_VERSION="$(tr '\r' '\n' < .config/mill-version | head -n 1 2> /dev/null)" + fi +fi + +MILL_USER_CACHE_DIR="${XDG_CACHE_HOME:-${HOME}/.cache}/mill" + +if [ -z "${MILL_DOWNLOAD_PATH}" ] ; then + MILL_DOWNLOAD_PATH="${MILL_USER_CACHE_DIR}/download" +fi + +# If not already set, try to fetch newest from Github +if [ -z "${MILL_VERSION}" ] ; then + # TODO: try to load latest version from release page + echo "No mill version specified." 1>&2 + echo "You should provide a version via '.mill-version' file or --mill-version option." 1>&2 + + mkdir -p "${MILL_DOWNLOAD_PATH}" + LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest" 2>/dev/null || ( + # we might be on OSX or BSD which don't have -d option for touch + # but probably a -A [-][[hh]mm]SS + touch "${MILL_DOWNLOAD_PATH}/.expire_latest"; touch -A -010000 "${MILL_DOWNLOAD_PATH}/.expire_latest" + ) || ( + # in case we still failed, we retry the first touch command with the intention + # to show the (previously suppressed) error message + LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest" + ) + + # POSIX shell variant of bash's -nt operator, see https://unix.stackexchange.com/a/449744/6993 + # if [ "${MILL_DOWNLOAD_PATH}/.latest" -nt "${MILL_DOWNLOAD_PATH}/.expire_latest" ] ; then + if [ -n "$(find -L "${MILL_DOWNLOAD_PATH}/.latest" -prune -newer "${MILL_DOWNLOAD_PATH}/.expire_latest")" ]; then + # we know a current latest version + MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null) + fi + + if [ -z "${MILL_VERSION}" ] ; then + # we don't know a current latest version + echo "Retrieving latest mill version ..." 1>&2 + LANG=C ${CURL_CMD} -s -i -f -I ${MILL_REPO_URL}/releases/latest 2> /dev/null | grep --ignore-case Location: | sed s'/^.*tag\///' | tr -d '\r\n' > "${MILL_DOWNLOAD_PATH}/.latest" + MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null) + fi + + if [ -z "${MILL_VERSION}" ] ; then + # Last resort + MILL_VERSION="${DEFAULT_MILL_VERSION}" + echo "Falling back to hardcoded mill version ${MILL_VERSION}" 1>&2 + else + echo "Using mill version ${MILL_VERSION}" 1>&2 + fi +fi + +MILL_NATIVE_SUFFIX="-native" +FULL_MILL_VERSION=$MILL_VERSION +ARTIFACT_SUFFIX="" +case "$MILL_VERSION" in + *"$MILL_NATIVE_SUFFIX") + MILL_VERSION=${MILL_VERSION%"$MILL_NATIVE_SUFFIX"} + if [ "$(expr substr $(uname -s) 1 5 2>/dev/null)" = "Linux" ]; then + if [ "$(uname -m)" = "aarch64" ]; then + ARTIFACT_SUFFIX="-native-linux-aarch64" + else + ARTIFACT_SUFFIX="-native-linux-amd64" + fi + elif [ "$(uname)" = "Darwin" ]; then + if [ "$(uname -m)" = "arm64" ]; then + ARTIFACT_SUFFIX="-native-mac-aarch64" + else + ARTIFACT_SUFFIX="-native-mac-amd64" + fi + else + echo "This native mill launcher supports only Linux and macOS." 1>&2 + exit 1 + fi +esac + +MILL="${MILL_DOWNLOAD_PATH}/${FULL_MILL_VERSION}" + +try_to_use_system_mill() { + if [ "$(uname)" != "Linux" ]; then + return 0 + fi + + MILL_IN_PATH="$(command -v mill || true)" + + if [ -z "${MILL_IN_PATH}" ]; then + return 0 + fi + + SYSTEM_MILL_FIRST_TWO_BYTES=$(head --bytes=2 "${MILL_IN_PATH}") + if [ "${SYSTEM_MILL_FIRST_TWO_BYTES}" = "#!" ]; then + # MILL_IN_PATH is (very likely) a shell script and not the mill + # executable, ignore it. + return 0 + fi + + SYSTEM_MILL_PATH=$(readlink -e "${MILL_IN_PATH}") + SYSTEM_MILL_SIZE=$(stat --format=%s "${SYSTEM_MILL_PATH}") + SYSTEM_MILL_MTIME=$(stat --format=%y "${SYSTEM_MILL_PATH}") + + if [ ! -d "${MILL_USER_CACHE_DIR}" ]; then + mkdir -p "${MILL_USER_CACHE_DIR}" + fi + + SYSTEM_MILL_INFO_FILE="${MILL_USER_CACHE_DIR}/system-mill-info" + if [ -f "${SYSTEM_MILL_INFO_FILE}" ]; then + parseSystemMillInfo() { + LINE_NUMBER="${1}" + # Select the line number of the SYSTEM_MILL_INFO_FILE, cut the + # variable definition in that line in two halves and return + # the value, and finally remove the quotes. + sed -n "${LINE_NUMBER}p" "${SYSTEM_MILL_INFO_FILE}" |\ + cut -d= -f2 |\ + sed 's/"\(.*\)"/\1/' + } + + CACHED_SYSTEM_MILL_PATH=$(parseSystemMillInfo 1) + CACHED_SYSTEM_MILL_VERSION=$(parseSystemMillInfo 2) + CACHED_SYSTEM_MILL_SIZE=$(parseSystemMillInfo 3) + CACHED_SYSTEM_MILL_MTIME=$(parseSystemMillInfo 4) + + if [ "${SYSTEM_MILL_PATH}" = "${CACHED_SYSTEM_MILL_PATH}" ] \ + && [ "${SYSTEM_MILL_SIZE}" = "${CACHED_SYSTEM_MILL_SIZE}" ] \ + && [ "${SYSTEM_MILL_MTIME}" = "${CACHED_SYSTEM_MILL_MTIME}" ]; then + if [ "${CACHED_SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then + MILL="${SYSTEM_MILL_PATH}" + return 0 + else + return 0 + fi + fi + fi + + SYSTEM_MILL_VERSION=$(${SYSTEM_MILL_PATH} --version | head -n1 | sed -n 's/^Mill.*version \(.*\)/\1/p') + + cat < "${SYSTEM_MILL_INFO_FILE}" +CACHED_SYSTEM_MILL_PATH="${SYSTEM_MILL_PATH}" +CACHED_SYSTEM_MILL_VERSION="${SYSTEM_MILL_VERSION}" +CACHED_SYSTEM_MILL_SIZE="${SYSTEM_MILL_SIZE}" +CACHED_SYSTEM_MILL_MTIME="${SYSTEM_MILL_MTIME}" +EOF + + if [ "${SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then + MILL="${SYSTEM_MILL_PATH}" + fi +} +try_to_use_system_mill + +# If not already downloaded, download it +if [ ! -s "${MILL}" ] ; then + + # support old non-XDG download dir + MILL_OLD_DOWNLOAD_PATH="${HOME}/.mill/download" + OLD_MILL="${MILL_OLD_DOWNLOAD_PATH}/${MILL_VERSION}" + if [ -x "${OLD_MILL}" ] ; then + MILL="${OLD_MILL}" + else + case $MILL_VERSION in + 0.0.* | 0.1.* | 0.2.* | 0.3.* | 0.4.* ) + DOWNLOAD_SUFFIX="" + DOWNLOAD_FROM_MAVEN=0 + ;; + 0.5.* | 0.6.* | 0.7.* | 0.8.* | 0.9.* | 0.10.* | 0.11.0-M* ) + DOWNLOAD_SUFFIX="-assembly" + DOWNLOAD_FROM_MAVEN=0 + ;; + *) + DOWNLOAD_SUFFIX="-assembly" + DOWNLOAD_FROM_MAVEN=1 + ;; + esac + + DOWNLOAD_FILE=$(mktemp mill.XXXXXX) + + if [ "$DOWNLOAD_FROM_MAVEN" = "1" ] ; then + DOWNLOAD_URL="https://repo1.maven.org/maven2/com/lihaoyi/mill-dist${ARTIFACT_SUFFIX}/${MILL_VERSION}/mill-dist${ARTIFACT_SUFFIX}-${MILL_VERSION}.jar" + else + MILL_VERSION_TAG=$(echo "$MILL_VERSION" | sed -E 's/([^-]+)(-M[0-9]+)?(-.*)?/\1\2/') + DOWNLOAD_URL="${GITHUB_RELEASE_CDN}${MILL_REPO_URL}/releases/download/${MILL_VERSION_TAG}/${MILL_VERSION}${DOWNLOAD_SUFFIX}" + unset MILL_VERSION_TAG + fi + + # TODO: handle command not found + echo "Downloading mill ${MILL_VERSION} from ${DOWNLOAD_URL} ..." 1>&2 + ${CURL_CMD} -f -L -o "${DOWNLOAD_FILE}" "${DOWNLOAD_URL}" + chmod +x "${DOWNLOAD_FILE}" + mkdir -p "${MILL_DOWNLOAD_PATH}" + mv "${DOWNLOAD_FILE}" "${MILL}" + + unset DOWNLOAD_FILE + unset DOWNLOAD_SUFFIX + fi +fi + +if [ -z "$MILL_MAIN_CLI" ] ; then + MILL_MAIN_CLI="${0}" +fi + +MILL_FIRST_ARG="" +if [ "$1" = "--bsp" ] || [ "$1" = "-i" ] || [ "$1" = "--interactive" ] || [ "$1" = "--no-server" ] || [ "$1" = "--repl" ] || [ "$1" = "--help" ] ; then + # Need to preserve the first position of those listed options + MILL_FIRST_ARG=$1 + shift +fi + +unset MILL_DOWNLOAD_PATH +unset MILL_OLD_DOWNLOAD_PATH +unset OLD_MILL +unset MILL_VERSION +unset MILL_REPO_URL + +# We don't quote MILL_FIRST_ARG on purpose, so we can expand the empty value without quotes +# shellcheck disable=SC2086 +exec "${MILL}" $MILL_FIRST_ARG -D "mill.main.cli=${MILL_MAIN_CLI}" "$@" From fe91fd4148a692cc98ca65eea4cb188406cb9fbd Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 8 May 2025 21:39:49 -0700 Subject: [PATCH 03/18] ADD: more config --- .github/workflows/run-vivado-flow.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index 1155a6a..926edae 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -14,7 +14,12 @@ jobs: - name: Checkout uses: actions/checkout@v4 - - name: Run Vivado flow on MlpPolicyRunner + - name: Build MemorySubsystem + run: | + source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh + make project CONFIG=MemorySubsystem + + - name: Build MlpPolicyRunner run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh make project CONFIG=MlpPolicyRunner From 444455e2fe5714879d1cb650482b2f0f1e65fef9 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 8 May 2025 22:02:52 -0700 Subject: [PATCH 04/18] ADD: separate out builder --- build.mill.scala | 45 +++++++------------ .../src/Builder.scala | 2 +- 2 files changed, 18 insertions(+), 29 deletions(-) rename ChiselProject/src/Elaborate.scala => builder/src/Builder.scala (99%) diff --git a/build.mill.scala b/build.mill.scala index 9c078dd..cb2ecb2 100644 --- a/build.mill.scala +++ b/build.mill.scala @@ -17,15 +17,11 @@ import mill.bsp._ /** - * Main build definition for the Chisel project. - * This object defines the project structure and its dependencies. + * Common configuration trait for Chisel projects */ -object ChiselProject extends ScalaModule with ScalafmtModule { m => - // Flag to switch between Chisel 3.x and Chisel 6.x - val useChisel3 = false - +trait ChiselModule extends ScalaModule with ScalafmtModule { m => // Configure Scala version based on Chisel version - override def scalaVersion = if (useChisel3) "2.13.10" else "2.13.15" + override def scalaVersion = "2.13.16" // Scala compiler options override def scalacOptions = Seq( @@ -36,19 +32,13 @@ object ChiselProject extends ScalaModule with ScalafmtModule { m => ) // Define Chisel dependencies based on version - override def ivyDeps = Agg( - if (useChisel3) - ivy"edu.berkeley.cs::chisel3:3.6.0" - else - ivy"org.chipsalliance::chisel:6.7.0" + override def ivyDeps = Agg( + ivy"org.chipsalliance::chisel:7.0.0-RC1", ) // Add Chisel compiler plugin override def scalacPluginIvyDeps = Agg( - if (useChisel3) - ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0" - else - ivy"org.chipsalliance:::chisel-plugin:6.7.0" + ivy"org.chipsalliance:::chisel-plugin:7.0.0-RC1", ) /** @@ -58,19 +48,18 @@ object ChiselProject extends ScalaModule with ScalafmtModule { m => // Add test dependencies override def ivyDeps = super.ivyDeps() ++ Agg( ivy"org.scalatest::scalatest::3.2.19", - if (useChisel3) - ivy"edu.berkeley.cs::chiseltest:0.6.0" - else - ivy"edu.berkeley.cs::chiseltest:6.0.0" + ivy"edu.berkeley.cs::chiseltest:6.0.0" ) } +} - // Configure additional Maven repositories for dependency resolution - def repositoriesTask = Task.Anon { - Seq( - coursier.MavenRepository("https://repo.scala-sbt.org/scalasbt/maven-releases"), - coursier.MavenRepository("https://oss.sonatype.org/content/repositories/releases"), - coursier.MavenRepository("https://oss.sonatype.org/content/repositories/snapshots") - ) ++ super.repositoriesTask() - } + +object builder extends ChiselModule + +/** + * Main build definition for the Chisel project. + * This object defines the project structure and its dependencies. + */ +object ChiselProject extends ChiselModule { m => + override def moduleDeps = Seq(builder) } diff --git a/ChiselProject/src/Elaborate.scala b/builder/src/Builder.scala similarity index 99% rename from ChiselProject/src/Elaborate.scala rename to builder/src/Builder.scala index 6ba4604..08edc9a 100644 --- a/ChiselProject/src/Elaborate.scala +++ b/builder/src/Builder.scala @@ -1,5 +1,5 @@ /** - * Elaborate.scala + * Builder.scala * * This file is responsible for elaborating the Chisel design into SystemVerilog. It is the main entry point for * generating the hardware description. From 30de576ac138fbeb072dab599931b2d4a79f2a14 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Thu, 8 May 2025 23:48:46 -0700 Subject: [PATCH 05/18] ADD: improve build system --- .../constraints/Arty-A7-100-Master.xdc | 226 ------------------ .../src/examples/MlpPolicyRunner.scala | 6 + .../generators/delta/memory/Axi4Memory.scala | 2 +- .../generators/xilinx/Axi4BlockMemory.scala | 2 +- .../src/generators/xilinx/Axi4Crossbar.scala | 2 +- .../xilinx/Axi4DataWidthConverter.scala | 2 +- .../generators/xilinx/Axi4LiteCrossbar.scala | 2 +- .../src/generators/xilinx/Axi4LiteGpio.scala | 2 +- .../xilinx/Axi4LiteStreamDataFifo.scala | 2 +- .../src/generators/xilinx/Axi4LiteTimer.scala | 2 +- .../generators/xilinx/Axi4LiteUartLite.scala | 2 +- .../xilinx/Axi4ProtocolConverter.scala | 2 +- .../generators/xilinx/Axi4QuadSpiFlash.scala | 2 +- .../src/generators/xilinx/Axi4SpiFlash.scala | 2 +- .../generators/xilinx/Axi4WiderMemory.scala | 2 +- .../generators/xilinx/ClockingWizard.scala | 2 +- .../src/generators/xilinx/FloatingPoint.scala | 2 +- Makefile | 10 +- builder/src/Builder.scala | 202 ++++++++-------- 19 files changed, 134 insertions(+), 340 deletions(-) diff --git a/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc b/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc index 664d463..e69de29 100644 --- a/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc +++ b/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc @@ -1,226 +0,0 @@ -## This file is a general .xdc for the Arty A7-100 Rev. D and Rev. E -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { io_CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { io_CLK100MHZ }]; - -## Switches -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { io_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0] -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { io_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] -set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { io_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { io_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] - -## RGB LEDs -set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { io_led0_b }]; #IO_L18N_T2_35 Sch=led0_b -set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { io_led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g -set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { io_led0_r }]; #IO_L19P_T3_35 Sch=led0_r -set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { io_led1_b }]; #IO_L20P_T3_35 Sch=led1_b -set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { io_led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g -set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { io_led1_r }]; #IO_L20N_T3_35 Sch=led1_r -set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { io_led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b -set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { io_led2_g }]; #IO_L22N_T3_35 Sch=led2_g -set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { io_led2_r }]; #IO_L22P_T3_35 Sch=led2_r -set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { io_led3_b }]; #IO_L23P_T3_35 Sch=led3_b -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { io_led3_g }]; #IO_L24P_T3_35 Sch=led3_g -set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { io_led3_r }]; #IO_L23N_T3_35 Sch=led3_r - -## LEDs -set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { io_led[0] }]; #IO_L24N_T3_35 Sch=led[4] -set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { io_led[1] }]; #IO_25_35 Sch=led[5] -set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { io_led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] -set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { io_led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] - -## Buttons -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] -set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { io_btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] - -## Pmod Header JA -set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { io_ja_0 }]; #IO_0_15 Sch=ja[1] -set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { io_ja_1 }]; #IO_L4P_T0_15 Sch=ja[2] -set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { io_ja_2 }]; #IO_L4N_T0_15 Sch=ja[3] -set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { io_ja_3 }]; #IO_L6P_T0_15 Sch=ja[4] -set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { io_ja_4 }]; #IO_L6N_T0_VREF_15 Sch=ja[7] -set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { io_ja_5 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] -set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { io_ja_6 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] -set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { io_ja_7 }]; #IO_25_15 Sch=ja[10] - -## Pmod Header JB -set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_0 }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] -set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { io_jb_1 }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] -set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_2 }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2] -set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_3 }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2] -set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { io_jb_4 }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3] -set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { io_jb_5 }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_6 }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4] -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_7 }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4] - -## Pmod Header JC -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { io_jc_0 }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { io_jc_1 }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { io_jc_2 }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { io_jc_3 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { io_jc_4 }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { io_jc_5 }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { io_jc_6 }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4] -set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { io_jc_7 }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4] - -## Pmod Header JD -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { io_jd_0 }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] -set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { io_jd_1 }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] -set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { io_jd_2 }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] -set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { io_jd_3 }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] -set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_4 }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] -set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_5 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] -set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_6 }]; #IO_L15P_T2_DQS_35 Sch=jd[9] -set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_7 }]; #IO_L15N_T2_DQS_35 Sch=jd[10] - -## USB-UART Interface -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { io_uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { io_uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in - -## ChipKit Outer Digital Header -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] -set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] -set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] -set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] -set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8] -set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12] -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13] - -## ChipKit Inner Digital Header -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28] -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_29 }]; #IO_25_14 Sch=ck_io[29] -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_30 }]; #IO_0_14 Sch=ck_io[30] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32] -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39] -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41] - -## ChipKit Outer Analog Header - as Single-Ended Analog Inputs -## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O. -## WARNING: Do not use both sets of constraints at the same time! -## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs. -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0 -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0 -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1 -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1 -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2 -#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2 -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3 -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3 -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4 -#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4 -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5 -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5 -## ChipKit Outer Analog Header - as Digital I/O -## NOTE: The following constraints should be used when using these ports as digital I/O. -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] - -## ChipKit Inner Analog Header - as Differential Analog Inputs -## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O. -## WARNING: Do not use both sets of constraints at the same time! -## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs. -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6 -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7 -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8 -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9 -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10 -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11 -## ChipKit Inner Analog Header - as Digital I/O -## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O. -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] - -## ChipKit SPI -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss - -## ChipKit I2C -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup - -## Misc. ChipKit Ports -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { io_ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst - -## SMSC Ethernet PHY -set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col -set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs -# set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc -# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio -set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk -set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn -set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk -set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv -set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2] -set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3] -set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk -set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { io_eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en -set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2] -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3] - -create_clock -period 40.000 -name io_eth_rx_clk [get_ports io_eth_rx_clk] -create_clock -period 40.000 -name io_eth_tx_clk [get_ports io_eth_tx_clk] - -## Quad SPI Flash - -# manually created clock for qspi_sck -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_sck }]; -create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10} [get_ports { io_qspi_sck }]; - -set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs -set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_1 }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_2 }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_3 }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] - -set_property -dict { BITSTREAM.CONFIG.SPI_BUSWIDTH {4} } [current_design] - -## Power Measurements -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2] -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1] -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1] -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] \ No newline at end of file diff --git a/ChiselProject/src/examples/MlpPolicyRunner.scala b/ChiselProject/src/examples/MlpPolicyRunner.scala index cad2908..d7a95dc 100644 --- a/ChiselProject/src/examples/MlpPolicyRunner.scala +++ b/ChiselProject/src/examples/MlpPolicyRunner.scala @@ -171,4 +171,10 @@ class MlpPolicyRunner extends RawModule { tile.io.debug.sysresp3 := 0.U(32.W) } + + + + addConstraintResource("ChiselProject/resources/constraints/Arty-A7-100-Master.xdc") + + addSimulationResource("ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv") } diff --git a/ChiselProject/src/generators/delta/memory/Axi4Memory.scala b/ChiselProject/src/generators/delta/memory/Axi4Memory.scala index ce3b477..88156ad 100644 --- a/ChiselProject/src/generators/delta/memory/Axi4Memory.scala +++ b/ChiselProject/src/generators/delta/memory/Axi4Memory.scala @@ -132,7 +132,7 @@ class Axi4Memory( def generate_tcl_script(): Unit = { if (memoryFileHex != "") { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" // Get current working directory val file_path = System.getProperty("user.dir") + "/firmware/" + memoryFileHex diff --git a/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala b/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala index 33b1778..a3c8aac 100644 --- a/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala +++ b/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala @@ -34,7 +34,7 @@ class Axi4BlockMemoryBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4BlockMemoryBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala b/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala index 2404790..fdd83fd 100644 --- a/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala +++ b/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala @@ -164,7 +164,7 @@ class Axi4CrossbarBlackbox( override def desiredName: String = s"Axi4CrossbarBlackbox_s${numSlave}_m${numMaster}_w${params.dataWidth}_id${params.idWidth}" def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = desiredName val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala b/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala index ef15084..4a4d4c3 100644 --- a/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala +++ b/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala @@ -32,7 +32,7 @@ class Axi4DataWidthConverterBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4DataWidthConverterBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala b/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala index a21fa0d..33cfa86 100644 --- a/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala +++ b/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala @@ -124,7 +124,7 @@ class Axi4LiteCrossbarBlackbox( def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4LiteCrossbarBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala b/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala index 9757f7d..8d179b7 100644 --- a/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala +++ b/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala @@ -34,7 +34,7 @@ class Axi4LiteGpioBlackbox extends BlackBox { }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4LiteGpioBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala b/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala index c1a0472..1f7983e 100644 --- a/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala +++ b/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala @@ -27,7 +27,7 @@ class Axi4LiteStreamDataFifoBlackbox(width: Int) extends BlackBox { }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "AXIStreamDataFifo" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala b/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala index 861454c..9c98fd3 100644 --- a/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala +++ b/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala @@ -44,7 +44,7 @@ class Axi4LiteTimerBlackbox extends BlackBox { }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4LiteTimerBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala b/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala index 3ab4193..1289d3e 100644 --- a/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala +++ b/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala @@ -33,7 +33,7 @@ class Axi4LiteUartLiteBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4LiteUartLiteBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala b/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala index 30592d4..010f7f8 100644 --- a/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala +++ b/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala @@ -32,7 +32,7 @@ class Axi4ProtocolConverterBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4ProtocolConverterBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala b/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala index 53fc6b0..db84326 100644 --- a/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala +++ b/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala @@ -121,7 +121,7 @@ class Axi4QuadSpiFlashBlackbox extends BlackBox { }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4QuadSpiFlashBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala b/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala index 9f0a0de..b7d3ff2 100644 --- a/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala +++ b/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala @@ -103,7 +103,7 @@ class Axi4SpiFlashBlackbox extends BlackBox { }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "Axi4SpiFlashBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala b/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala index f71dada..c5b377f 100644 --- a/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala +++ b/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala @@ -133,7 +133,7 @@ class WiderBlockMemoryBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "WiderBlockMemoryBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/ClockingWizard.scala b/ChiselProject/src/generators/xilinx/ClockingWizard.scala index 4fd2b18..f14f92a 100644 --- a/ChiselProject/src/generators/xilinx/ClockingWizard.scala +++ b/ChiselProject/src/generators/xilinx/ClockingWizard.scala @@ -48,7 +48,7 @@ class ClockingWizardBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "ClockingWizardBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/ChiselProject/src/generators/xilinx/FloatingPoint.scala b/ChiselProject/src/generators/xilinx/FloatingPoint.scala index 6bfc778..d512ab7 100644 --- a/ChiselProject/src/generators/xilinx/FloatingPoint.scala +++ b/ChiselProject/src/generators/xilinx/FloatingPoint.scala @@ -43,7 +43,7 @@ class FloatingPointBlackbox( }) def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/VivadoProject" + val vivado_project_dir = "out/vivado-project" val ip_name = "FloatingPointBlackbox" val ip_name_lower = ip_name.toLowerCase() diff --git a/Makefile b/Makefile index 690cf69..e7b0851 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,6 @@ BUILD_DIR = ./generated-src -PRJ = ChiselProject +MODULE = ChiselProject CONFIG ?= MinimalArty100T @@ -8,16 +8,16 @@ MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - $(MILL_PATH) -i $(PRJ).runMain GenerateVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(MODULE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) project: verilog - $(MILL_PATH) -i $(PRJ).runMain GenerateProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(MODULE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) bitstream: project - $(MILL_PATH) -i $(PRJ).runMain GenerateBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i $(MODULE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) test: - $(MILL_PATH) -i $(PRJ).Test + $(MILL_PATH) -i $(MODULE).Test clean: rm -rf $(BUILD_DIR) diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 08edc9a..9821b9c 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -10,9 +10,40 @@ import scala.sys.process._ import java.io.PrintWriter import java.io.File import java.io.FileFilter +import java.io.FileWriter + + +object BuilderConfig { + val chiselGeneratedFilelist = "generated-src/filelist.f" + val simulationFilelist = "generated-src/sim_filelist.f" + val constraintsFilelist = "generated-src/constraints_filelist.f" + + val vivadoProjectDir = "out/vivado-project" +} + + +object addSimulationResource { + def apply(path: String): Unit = { + println(s"adding Simulation resource: $path") + val filelists = new File(BuilderConfig.simulationFilelist) + val writer = new PrintWriter(new FileWriter(filelists, true)) + writer.println(path) + writer.close() + } +} + +object addConstraintResource { + def apply(path: String): Unit = { + println(s"adding Constraint resource: $path") + val filelists = new File(BuilderConfig.constraintsFilelist) + val writer = new PrintWriter(new FileWriter(filelists, true)) + writer.println(path) + writer.close() + } +} // helper function to parse the module name from the arguments -object ParseModuleName { +object _parseModuleName { def apply(args: Array[String]): (String, Array[String]) = { if (args.length < 1) { println("Error: Please provide the module name as an argument") @@ -29,159 +60,142 @@ object ParseModuleName { } } -object CreateVivadoDirectory { - def apply(vivado_project_dir: String): Unit = { - new File(vivado_project_dir).mkdirs() - new File(s"${vivado_project_dir}/scripts").mkdirs() - } -} - - -object GenerateVerilog extends App { - val (module_name, remaining_args) = ParseModuleName(args) +object buildVerilog extends App { + { + val simulationFilelist = new FileWriter(new File(BuilderConfig.simulationFilelist)) + simulationFilelist.write("") + simulationFilelist.close() - val vivado_project_dir = "out/VivadoProject" - CreateVivadoDirectory(vivado_project_dir) + val constraintsFilelist = new FileWriter(new File(BuilderConfig.constraintsFilelist)) + constraintsFilelist.write("") + constraintsFilelist.close() + } + new File(BuilderConfig.vivadoProjectDir).mkdirs() + new File(s"${BuilderConfig.vivadoProjectDir}/scripts").mkdirs() + + val (moduleName, remainingArgs) = _parseModuleName(args) val moduleClass = () => { - val module = Class.forName(module_name) + val module = Class.forName(moduleName) .getDeclaredConstructor() .newInstance() .asInstanceOf[chisel3.RawModule] module } - - println(s"elaborating module: $module_name") - val chisel_opts = remaining_args ++ Array("--split-verilog") - - val firtool_opts = Array( + val chiselOpts = remainingArgs ++ Array("--split-verilog") + val firtoolOpts = Array( "-disable-all-randomization", "-strip-debug-info", ) ChiselStage.emitSystemVerilogFile( gen=moduleClass(), - args=chisel_opts, - firtoolOpts=firtool_opts + args=chiselOpts, + firtoolOpts=firtoolOpts ) } -object GenerateProject extends App { - val (module_name, remaining_args) = ParseModuleName(args) - - val project_source_dir = "ChiselProject/" - val vivado_project_dir = "out/VivadoProject" +object buildProject extends App { + val (moduleName, remainingArgs) = _parseModuleName(args) - CreateVivadoDirectory(vivado_project_dir) + new File(BuilderConfig.vivadoProjectDir).mkdirs() + new File(s"${BuilderConfig.vivadoProjectDir}/scripts").mkdirs() /* Arty A7 100T */ - // val fpga_part = "xc7a100ticsg324-1L" - // val board_part = "digilentinc.com:arty-a7-100t:part0:1.1" + // val fpgaPart = "xc7a100ticsg324-1L" + // val boardPart = "digilentinc.com:arty-a7-100t:part0:1.1" /* Arty A7 35T */ - val fpga_part = "xc7a35ticsg324-1L" - val board_part = "digilentinc.com:arty-a7-35:part0:1.1" + val fpgaPart = "xc7a35ticsg324-1L" + val boardPart = "digilentinc.com:arty-a7-35:part0:1.1" /* Zedboard */ - // val fpga_part = "xc7z020clg484-1" - // val board_part = "digilentinc.com:zedboard:part0:1.1" - - // get all files under the generated-src directory - val sources = new File("generated-src").listFiles(new FileFilter { - def accept(file: File): Boolean = file.isFile || file.isDirectory - }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath)) - val verilog_sources = new File("ChiselProject/test/resources").listFiles(new FileFilter { - def accept(file: File): Boolean = file.isFile || file.isDirectory - }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath)) - - val excluded_sources = Array( - "ClockSourceAtFreqMHz.v", - "SimJTAG.v", - "SimTSI.v", - "SimUART.v", - "TestDriver.v", - ) - + // val fpgaPart = "xc7z020clg484-1" + // val boardPart = "digilentinc.com:zedboard:part0:1.1" + + val chiselGeneratedSources = scala.io.Source.fromFile(new File(BuilderConfig.chiselGeneratedFilelist)) + .getLines() + .map(_.trim) + .filter(_.nonEmpty) + .map(line => s"generated-src/${line}") + .toList + val simulationSources = scala.io.Source.fromFile(new File(BuilderConfig.simulationFilelist)) + .getLines() + .map(_.trim) + .filter(_.nonEmpty) + val constraintResources = scala.io.Source.fromFile(new File(BuilderConfig.constraintsFilelist)) + .getLines() + .map(_.trim) + .filter(_.nonEmpty) - // val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.WithPeripheralAXI4LiteTinyRocketConfig/gen-collateral").listFiles(new FileFilter { - // def accept(file: File): Boolean = file.isFile || file.isDirectory - // }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath)) - // // Exclude files listed in excluded_sources - // .filterNot(source => excluded_sources.contains(new File(source).getName)) { // create a run.tcl file - val run_tcl = new PrintWriter(s"${vivado_project_dir}/scripts/create_project.tcl") + val runTcl = new PrintWriter(s"${BuilderConfig.vivadoProjectDir}/scripts/create_project.tcl") // create project - run_tcl.println(s"create_project VivadoProject ${vivado_project_dir} -part ${fpga_part} -force") + runTcl.println(s"create_project VivadoProject ${BuilderConfig.vivadoProjectDir} -part ${fpgaPart} -force") // run_tcl.println(s"set_property board_part $board_part [current_project]") // add constraints - run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/Arty-A7-100-Master.xdc") - - run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/axis_async_fifo.tcl") - run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/eth_mac_fifo.tcl") - run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/mii_phy_if.tcl") - run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/sync_reset.tcl") - + if (constraintResources.nonEmpty) { + runTcl.print(s"add_files -fileset constrs_1 {") + constraintResources.foreach(filepath => { + runTcl.println(s" ${filepath} \\") + }) + runTcl.println("}") + } // add sources - run_tcl.print(s"add_files") - sources.foreach(source => { - run_tcl.println(s" ${source} \\") + runTcl.print(s"add_files") + chiselGeneratedSources.foreach(filepath => { + runTcl.println(s" ${filepath} \\") }) - run_tcl.println("") - - run_tcl.print(s"add_files -fileset sim_1 {") - verilog_sources.foreach(source => { - run_tcl.println(s" ${source} \\") - }) - run_tcl.println("}") - - // run_tcl.print(s"add_files") - // chipyard_sources.foreach(source => { - // run_tcl.println(s" ${source} \\") - // }) - // run_tcl.println("") + runTcl.println("") + + if (simulationSources.nonEmpty) { + runTcl.print(s"add_files -fileset sim_1 {") + simulationSources.foreach(filepath => { + runTcl.println(s" ${filepath} \\") + }) + runTcl.println("}") + } - run_tcl.println(s"set_property top ${module_name} [current_fileset]") + runTcl.println(s"set_property top ${moduleName} [current_fileset]") /* create Vivado IPs */ - run_tcl.println("update_ip_catalog") + runTcl.println("update_ip_catalog") - val create_ip_files = new File(s"${vivado_project_dir}/scripts").listFiles(new FileFilter { + val create_ip_files = new File(s"${BuilderConfig.vivadoProjectDir}/scripts").listFiles(new FileFilter { def accept(file: File): Boolean = file.isFile && file.getName != "create_project.tcl" }).map(_.getAbsolutePath) create_ip_files.foreach(file => { - run_tcl.println(s"source ${file}") + runTcl.println(s"source ${file}") }) // configure simulation settings - run_tcl.println(s"update_compile_order -fileset sources_1") - run_tcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]") - run_tcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]") - run_tcl.println(s"set_property top ${module_name}Testbench [get_filesets sim_1]") + runTcl.println(s"update_compile_order -fileset sources_1") + runTcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]") + runTcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]") + runTcl.println(s"set_property top ${moduleName}Testbench [get_filesets sim_1]") // run_tcl.println(s"set_property top_lib xil_defaultlib [get_filesets sim_1]") - run_tcl.close() - run_tcl.flush() + runTcl.close() + runTcl.flush() } - s"vivado -mode batch -source ${vivado_project_dir}/scripts/create_project.tcl".! + s"vivado -mode batch -source ${BuilderConfig.vivadoProjectDir}/scripts/create_project.tcl".! } object GenerateBitstream extends App { - val (module_name, remaining_args) = ParseModuleName(args) + val (module_name, remaining_args) = _parseModuleName(args) - val vivado_project_dir = "out/VivadoProject" - CreateVivadoDirectory(vivado_project_dir) // { // // create a generate_bitstream.tcl file From 972bbbf4a841f54bb18ea70241b10aaea78d803b Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 00:07:16 -0700 Subject: [PATCH 06/18] ADD: break component into modules --- .github/workflows/run-vivado-flow.yaml | 4 +- .../generators/alexforencich/UDPCore.scala | 69 ----------------- .../test/resources/verilog/TestDriver.sv | 25 ------ .../verilog/examples/GenericTestBench.sv | 77 ------------------- ChiselProject/test/src/SyncRamSpec.scala | 41 ---------- Makefile | 10 +-- build.mill.scala | 15 ++-- builder/src/Builder.scala | 4 +- .../src}/DigitalTop.scala | 0 .../src}/MotorArty100T.scala | 0 .../src}/TinyRocketArty100T.scala | 0 .../src}/UdpTinyRocketArty100T.scala | 0 .../resources/verilog/AsyncRam.v | 0 .../resources/verilog/Ram.v | 0 .../resources/verilog}/SimSpiFlashModel.sv | 0 .../resources/verilog}/SimUart.sv | 0 .../resources/verilog}/SpiFlashMemCtrl.sv | 0 .../src}/TestTiles.scala | 0 .../delta => module-delta-soc/src}/Tile.scala | 0 .../src/configs}/MemorySubsystem.scala | 4 +- .../src/configs}/MlpPolicyRunner.scala | 10 ++- .../src}/constants/Constants.scala | 0 .../src}/constants/Instructions.scala | 0 .../src}/core/ALU.scala | 0 .../src}/core/CSR.scala | 0 .../src}/core/Core.scala | 0 .../src}/core/InstructionDecode.scala | 0 .../src}/core/InstructionFetch.scala | 0 .../src}/core/LoadStore.scala | 0 .../src}/core/SimdFloatingPoint.scala | 0 .../src}/core/SimdLoadStore.scala | 0 .../interconnect/Axi4WidthDownsizer.scala | 0 .../src}/interconnect/Axi4WidthUpsizer.scala | 0 .../src}/memory/AsyncRam.scala | 0 .../src}/memory/Axi4LiteMemory.scala | 0 .../src}/memory/Axi4Memory.scala | 0 .../src}/memory/Axi4MemoryWithLatency.scala | 0 .../src}/memory/Ram.scala | 0 .../test}/EECS151TileISATestbench.sv | 0 .../test}/EECS151TileTestbench.sv | 0 .../test}/EECS252TileTestbench.sv | 0 .../test}/InstructionFetchTestbench.sv | 0 .../test}/MemorySubsystemTestbench.sv | 0 .../test}/MlpPolicyRunnerTestbench.sv | 0 .../src}/MadaTimer.scala | 0 .../constraints/Arty-A7-100-Master.xdc | 0 .../resources/constraints/Arty_C_mig.ucf | 0 .../resources/constraints/Zedboard-Master.xdc | 0 .../resources/constraints/axis_async_fifo.tcl | 0 .../resources/constraints/eth_mac_fifo.tcl | 0 .../resources/constraints/mig.prj | 0 .../resources/constraints/mii_phy_if.tcl | 0 .../resources/constraints/sync_reset.tcl | 0 .../resources/verilog/Arty100TShell.v | 0 .../.github/workflows/regression-tests.yml | 0 .../verilog/alexforencich/lib/axis/.gitignore | 0 .../alexforencich/lib/axis/.test_durations | 0 .../verilog/alexforencich/lib/axis/AUTHORS | 0 .../verilog/alexforencich/lib/axis/COPYING | 0 .../verilog/alexforencich/lib/axis/README | 0 .../verilog/alexforencich/lib/axis/README.md | 0 .../alexforencich/lib/axis/rtl/arbiter.v | 0 .../alexforencich/lib/axis/rtl/axis_adapter.v | 0 .../alexforencich/lib/axis/rtl/axis_arb_mux.v | 0 .../lib/axis/rtl/axis_arb_mux_wrap.py | 0 .../lib/axis/rtl/axis_async_fifo.v | 0 .../lib/axis/rtl/axis_async_fifo_adapter.v | 0 .../lib/axis/rtl/axis_broadcast.v | 0 .../lib/axis/rtl/axis_broadcast_wrap.py | 0 .../lib/axis/rtl/axis_cobs_decode.v | 0 .../lib/axis/rtl/axis_cobs_encode.v | 0 .../lib/axis/rtl/axis_crosspoint.v | 0 .../lib/axis/rtl/axis_crosspoint_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_demux.v | 0 .../lib/axis/rtl/axis_demux_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_fifo.v | 0 .../lib/axis/rtl/axis_fifo_adapter.v | 0 .../lib/axis/rtl/axis_frame_join.v | 0 .../lib/axis/rtl/axis_frame_join_wrap.py | 0 .../lib/axis/rtl/axis_frame_len.v | 0 .../lib/axis/rtl/axis_frame_length_adjust.v | 0 .../axis/rtl/axis_frame_length_adjust_fifo.v | 0 .../lib/axis/rtl/axis_ll_bridge.v | 0 .../alexforencich/lib/axis/rtl/axis_mux.v | 0 .../lib/axis/rtl/axis_mux_wrap.py | 0 .../lib/axis/rtl/axis_pipeline_fifo.v | 0 .../lib/axis/rtl/axis_pipeline_register.v | 0 .../lib/axis/rtl/axis_ram_switch.v | 0 .../lib/axis/rtl/axis_ram_switch_wrap.py | 0 .../lib/axis/rtl/axis_rate_limit.v | 0 .../lib/axis/rtl/axis_register.v | 0 .../lib/axis/rtl/axis_srl_fifo.v | 0 .../lib/axis/rtl/axis_srl_register.v | 0 .../lib/axis/rtl/axis_stat_counter.v | 0 .../alexforencich/lib/axis/rtl/axis_switch.v | 0 .../lib/axis/rtl/axis_switch_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_tap.v | 0 .../lib/axis/rtl/ll_axis_bridge.v | 0 .../lib/axis/rtl/priority_encoder.v | 0 .../alexforencich/lib/axis/rtl/sync_reset.v | 0 .../lib/axis/syn/quartus/axis_async_fifo.sdc | 0 .../lib/axis/syn/quartus/sync_reset.sdc | 0 .../axis/syn/quartus_pro/axis_async_fifo.sdc | 0 .../lib/axis/syn/quartus_pro/sync_reset.sdc | 0 .../lib/axis/syn/vivado/axis_async_fifo.tcl | 0 .../lib/axis/syn/vivado/sync_reset.tcl | 0 .../alexforencich/lib/axis/tb/Makefile | 0 .../lib/axis/tb/axis_adapter/Makefile | 0 .../axis/tb/axis_adapter/test_axis_adapter.py | 0 .../lib/axis/tb/axis_arb_mux/Makefile | 0 .../axis/tb/axis_arb_mux/test_axis_arb_mux.py | 0 .../lib/axis/tb/axis_async_fifo/Makefile | 0 .../axis_async_fifo/test_axis_async_fifo.py | 0 .../axis/tb/axis_async_fifo_adapter/Makefile | 0 .../test_axis_async_fifo_adapter.py | 0 .../lib/axis/tb/axis_broadcast/Makefile | 0 .../tb/axis_broadcast/test_axis_broadcast.py | 0 .../lib/axis/tb/axis_cobs_decode/Makefile | 0 .../axis_cobs_decode/test_axis_cobs_decode.py | 0 .../lib/axis/tb/axis_cobs_encode/Makefile | 0 .../axis_cobs_encode/test_axis_cobs_encode.py | 0 .../lib/axis/tb/axis_demux/Makefile | 0 .../lib/axis/tb/axis_demux/test_axis_demux.py | 0 .../alexforencich/lib/axis/tb/axis_ep.py | 0 .../lib/axis/tb/axis_fifo/Makefile | 0 .../lib/axis/tb/axis_fifo/test_axis_fifo.py | 0 .../lib/axis/tb/axis_fifo_adapter/Makefile | 0 .../test_axis_fifo_adapter.py | 0 .../axis/tb/axis_frame_length_adjust/Makefile | 0 .../test_axis_frame_length_adjust.py | 0 .../tb/axis_frame_length_adjust_fifo/Makefile | 0 .../test_axis_frame_length_adjust_fifo.py | 0 .../lib/axis/tb/axis_mux/Makefile | 0 .../lib/axis/tb/axis_mux/test_axis_mux.py | 0 .../lib/axis/tb/axis_pipeline_fifo/Makefile | 0 .../test_axis_pipeline_fifo.py | 0 .../axis/tb/axis_pipeline_register/Makefile | 0 .../test_axis_pipeline_register.py | 0 .../lib/axis/tb/axis_ram_switch/Makefile | 0 .../axis_ram_switch/test_axis_ram_switch.py | 0 .../lib/axis/tb/axis_rate_limit/Makefile | 0 .../axis_rate_limit/test_axis_rate_limit.py | 0 .../lib/axis/tb/axis_register/Makefile | 0 .../tb/axis_register/test_axis_register.py | 0 .../lib/axis/tb/axis_srl_fifo/Makefile | 0 .../tb/axis_srl_fifo/test_axis_srl_fifo.py | 0 .../lib/axis/tb/axis_srl_register/Makefile | 0 .../test_axis_srl_register.py | 0 .../lib/axis/tb/axis_switch/Makefile | 0 .../axis/tb/axis_switch/test_axis_switch.py | 0 .../alexforencich/lib/axis/tb/ll_ep.py | 0 .../alexforencich/lib/axis/tb/test_arbiter.py | 0 .../alexforencich/lib/axis/tb/test_arbiter.v | 0 .../lib/axis/tb/test_arbiter_rr.py | 0 .../lib/axis/tb/test_arbiter_rr.v | 0 .../lib/axis/tb/test_axis_adapter_64_8.py | 0 .../lib/axis/tb/test_axis_adapter_64_8.v | 0 .../lib/axis/tb/test_axis_adapter_8_64.py | 0 .../lib/axis/tb/test_axis_adapter_8_64.v | 0 .../lib/axis/tb/test_axis_arb_mux_4.py | 0 .../lib/axis/tb/test_axis_arb_mux_4.v | 0 .../lib/axis/tb/test_axis_arb_mux_4_64.py | 0 .../lib/axis/tb/test_axis_arb_mux_4_64.v | 0 .../lib/axis/tb/test_axis_async_fifo.py | 0 .../lib/axis/tb/test_axis_async_fifo.v | 0 .../lib/axis/tb/test_axis_async_fifo_64.py | 0 .../lib/axis/tb/test_axis_async_fifo_64.v | 0 .../tb/test_axis_async_fifo_adapter_64_8.py | 0 .../tb/test_axis_async_fifo_adapter_64_8.v | 0 .../tb/test_axis_async_fifo_adapter_8_64.py | 0 .../tb/test_axis_async_fifo_adapter_8_64.v | 0 .../lib/axis/tb/test_axis_async_frame_fifo.py | 0 .../lib/axis/tb/test_axis_async_frame_fifo.v | 0 .../axis/tb/test_axis_async_frame_fifo_64.py | 0 .../axis/tb/test_axis_async_frame_fifo_64.v | 0 .../lib/axis/tb/test_axis_broadcast_4.py | 0 .../lib/axis/tb/test_axis_broadcast_4.v | 0 .../lib/axis/tb/test_axis_cobs_decode.py | 0 .../lib/axis/tb/test_axis_cobs_decode.v | 0 .../lib/axis/tb/test_axis_cobs_encode.py | 0 .../lib/axis/tb/test_axis_cobs_encode.v | 0 .../tb/test_axis_cobs_encode_zero_frame.py | 0 .../tb/test_axis_cobs_encode_zero_frame.v | 0 .../lib/axis/tb/test_axis_crosspoint_4x4.py | 0 .../lib/axis/tb/test_axis_crosspoint_4x4.v | 0 .../axis/tb/test_axis_crosspoint_4x4_64.py | 0 .../lib/axis/tb/test_axis_crosspoint_4x4_64.v | 0 .../lib/axis/tb/test_axis_demux_4.py | 0 .../lib/axis/tb/test_axis_demux_4.v | 0 .../lib/axis/tb/test_axis_demux_4_64.py | 0 .../lib/axis/tb/test_axis_demux_4_64.v | 0 .../lib/axis/tb/test_axis_fifo.py | 0 .../lib/axis/tb/test_axis_fifo.v | 0 .../lib/axis/tb/test_axis_fifo_64.py | 0 .../lib/axis/tb/test_axis_fifo_64.v | 0 .../axis/tb/test_axis_fifo_adapter_64_8.py | 0 .../lib/axis/tb/test_axis_fifo_adapter_64_8.v | 0 .../axis/tb/test_axis_fifo_adapter_8_64.py | 0 .../lib/axis/tb/test_axis_fifo_adapter_8_64.v | 0 .../lib/axis/tb/test_axis_frame_fifo.py | 0 .../lib/axis/tb/test_axis_frame_fifo.v | 0 .../lib/axis/tb/test_axis_frame_fifo_64.py | 0 .../lib/axis/tb/test_axis_frame_fifo_64.v | 0 .../lib/axis/tb/test_axis_frame_join_4.py | 0 .../lib/axis/tb/test_axis_frame_join_4.v | 0 .../lib/axis/tb/test_axis_frame_len_64.py | 0 .../lib/axis/tb/test_axis_frame_len_64.v | 0 .../lib/axis/tb/test_axis_frame_len_8.py | 0 .../lib/axis/tb/test_axis_frame_len_8.v | 0 .../tb/test_axis_frame_length_adjust_64.py | 0 .../tb/test_axis_frame_length_adjust_64.v | 0 .../tb/test_axis_frame_length_adjust_8.py | 0 .../axis/tb/test_axis_frame_length_adjust_8.v | 0 .../tb/test_axis_frame_length_adjust_fifo.py | 0 .../tb/test_axis_frame_length_adjust_fifo.v | 0 .../test_axis_frame_length_adjust_fifo_64.py | 0 .../test_axis_frame_length_adjust_fifo_64.v | 0 .../lib/axis/tb/test_axis_ll_bridge.py | 0 .../lib/axis/tb/test_axis_ll_bridge.v | 0 .../lib/axis/tb/test_axis_mux_4.py | 0 .../lib/axis/tb/test_axis_mux_4.v | 0 .../lib/axis/tb/test_axis_mux_4_64.py | 0 .../lib/axis/tb/test_axis_mux_4_64.v | 0 .../tb/test_axis_ram_switch_1x4_256_64.py | 0 .../axis/tb/test_axis_ram_switch_1x4_256_64.v | 0 .../tb/test_axis_ram_switch_4x1_64_256.py | 0 .../axis/tb/test_axis_ram_switch_4x1_64_256.v | 0 .../axis/tb/test_axis_ram_switch_4x4_64_64.py | 0 .../axis/tb/test_axis_ram_switch_4x4_64_64.v | 0 .../lib/axis/tb/test_axis_rate_limit.py | 0 .../lib/axis/tb/test_axis_rate_limit.v | 0 .../lib/axis/tb/test_axis_rate_limit_64.py | 0 .../lib/axis/tb/test_axis_rate_limit_64.v | 0 .../lib/axis/tb/test_axis_register.py | 0 .../lib/axis/tb/test_axis_register.v | 0 .../lib/axis/tb/test_axis_register_64.py | 0 .../lib/axis/tb/test_axis_register_64.v | 0 .../lib/axis/tb/test_axis_srl_fifo.py | 0 .../lib/axis/tb/test_axis_srl_fifo.v | 0 .../lib/axis/tb/test_axis_srl_fifo_64.py | 0 .../lib/axis/tb/test_axis_srl_fifo_64.v | 0 .../lib/axis/tb/test_axis_srl_register.py | 0 .../lib/axis/tb/test_axis_srl_register.v | 0 .../lib/axis/tb/test_axis_srl_register_64.py | 0 .../lib/axis/tb/test_axis_srl_register_64.v | 0 .../lib/axis/tb/test_axis_stat_counter.py | 0 .../lib/axis/tb/test_axis_stat_counter.v | 0 .../lib/axis/tb/test_axis_switch_4x4.py | 0 .../lib/axis/tb/test_axis_switch_4x4.v | 0 .../lib/axis/tb/test_axis_switch_4x4_64.py | 0 .../lib/axis/tb/test_axis_switch_4x4_64.v | 0 .../lib/axis/tb/test_axis_tap.py | 0 .../alexforencich/lib/axis/tb/test_axis_tap.v | 0 .../lib/axis/tb/test_axis_tap_64.py | 0 .../lib/axis/tb/test_axis_tap_64.v | 0 .../lib/axis/tb/test_ll_axis_bridge.py | 0 .../lib/axis/tb/test_ll_axis_bridge.v | 0 .../lib/axis/tb/test_priority_encoder.py | 0 .../lib/axis/tb/test_priority_encoder.v | 0 .../verilog/alexforencich/lib/axis/tox.ini | 0 .../verilog/alexforencich/lib/update-axis.sh | 0 .../resources/verilog/alexforencich/rtl/arp.v | 0 .../verilog/alexforencich/rtl/arp_cache.v | 0 .../verilog/alexforencich/rtl/arp_eth_rx.v | 0 .../verilog/alexforencich/rtl/arp_eth_tx.v | 0 .../alexforencich/rtl/axis_baser_rx_64.v | 0 .../alexforencich/rtl/axis_baser_tx_64.v | 0 .../verilog/alexforencich/rtl/axis_eth_fcs.v | 0 .../alexforencich/rtl/axis_eth_fcs_check.v | 0 .../alexforencich/rtl/axis_eth_fcs_check_64.v | 0 .../alexforencich/rtl/axis_eth_fcs_insert.v | 0 .../rtl/axis_eth_fcs_insert_64.v | 0 .../verilog/alexforencich/rtl/axis_gmii_rx.v | 0 .../verilog/alexforencich/rtl/axis_gmii_tx.v | 0 .../alexforencich/rtl/axis_xgmii_rx_32.v | 0 .../alexforencich/rtl/axis_xgmii_rx_64.v | 0 .../alexforencich/rtl/axis_xgmii_tx_32.v | 0 .../alexforencich/rtl/axis_xgmii_tx_64.v | 0 .../verilog/alexforencich/rtl/eth_arb_mux.v | 0 .../verilog/alexforencich/rtl/eth_axis_rx.v | 0 .../verilog/alexforencich/rtl/eth_axis_tx.v | 0 .../verilog/alexforencich/rtl/eth_demux.v | 0 .../verilog/alexforencich/rtl/eth_mac_10g.v | 0 .../alexforencich/rtl/eth_mac_10g_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g.v | 0 .../alexforencich/rtl/eth_mac_1g_fifo.v | 0 .../alexforencich/rtl/eth_mac_1g_gmii.v | 0 .../alexforencich/rtl/eth_mac_1g_gmii_fifo.v | 0 .../alexforencich/rtl/eth_mac_1g_rgmii.v | 0 .../alexforencich/rtl/eth_mac_1g_rgmii_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_mii.v | 0 .../alexforencich/rtl/eth_mac_mii_fifo.v | 0 .../alexforencich/rtl/eth_mac_phy_10g.v | 0 .../alexforencich/rtl/eth_mac_phy_10g_fifo.v | 0 .../alexforencich/rtl/eth_mac_phy_10g_rx.v | 0 .../alexforencich/rtl/eth_mac_phy_10g_tx.v | 0 .../verilog/alexforencich/rtl/eth_mux.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g.v | 0 .../alexforencich/rtl/eth_phy_10g_rx.v | 0 .../rtl/eth_phy_10g_rx_ber_mon.v | 0 .../rtl/eth_phy_10g_rx_frame_sync.v | 0 .../alexforencich/rtl/eth_phy_10g_rx_if.v | 0 .../rtl/eth_phy_10g_rx_watchdog.v | 0 .../alexforencich/rtl/eth_phy_10g_tx.v | 0 .../alexforencich/rtl/eth_phy_10g_tx_if.v | 0 .../verilog/alexforencich/rtl/gmii_phy_if.v | 0 .../verilog/alexforencich/rtl/iddr.v | 0 .../resources/verilog/alexforencich/rtl/ip.v | 0 .../verilog/alexforencich/rtl/ip_64.v | 0 .../verilog/alexforencich/rtl/ip_arb_mux.v | 0 .../verilog/alexforencich/rtl/ip_complete.v | 0 .../alexforencich/rtl/ip_complete_64.v | 0 .../verilog/alexforencich/rtl/ip_demux.v | 0 .../verilog/alexforencich/rtl/ip_eth_rx.v | 0 .../verilog/alexforencich/rtl/ip_eth_rx_64.v | 0 .../verilog/alexforencich/rtl/ip_eth_tx.v | 0 .../verilog/alexforencich/rtl/ip_eth_tx_64.v | 0 .../verilog/alexforencich/rtl/ip_mux.v | 0 .../verilog/alexforencich/rtl/lfsr.v | 0 .../verilog/alexforencich/rtl/mac_ctrl_rx.v | 0 .../verilog/alexforencich/rtl/mac_ctrl_tx.v | 0 .../alexforencich/rtl/mac_pause_ctrl_rx.v | 0 .../alexforencich/rtl/mac_pause_ctrl_tx.v | 0 .../verilog/alexforencich/rtl/mii_phy_if.v | 0 .../verilog/alexforencich/rtl/oddr.v | 0 .../verilog/alexforencich/rtl/ptp_clock.v | 0 .../verilog/alexforencich/rtl/ptp_clock_cdc.v | 0 .../verilog/alexforencich/rtl/ptp_perout.v | 0 .../alexforencich/rtl/ptp_tag_insert.v | 0 .../verilog/alexforencich/rtl/ptp_td_leaf.v | 0 .../verilog/alexforencich/rtl/ptp_td_phc.v | 0 .../alexforencich/rtl/ptp_td_rel2tod.v | 0 .../alexforencich/rtl/ptp_ts_extract.v | 0 .../verilog/alexforencich/rtl/rgmii_phy_if.v | 0 .../verilog/alexforencich/rtl/ssio_ddr_in.v | 0 .../alexforencich/rtl/ssio_ddr_in_diff.v | 0 .../verilog/alexforencich/rtl/ssio_ddr_out.v | 0 .../alexforencich/rtl/ssio_ddr_out_diff.v | 0 .../verilog/alexforencich/rtl/ssio_sdr_in.v | 0 .../alexforencich/rtl/ssio_sdr_in_diff.v | 0 .../verilog/alexforencich/rtl/ssio_sdr_out.v | 0 .../alexforencich/rtl/ssio_sdr_out_diff.v | 0 .../resources/verilog/alexforencich/rtl/udp.v | 0 .../verilog/alexforencich/rtl/udp_64.v | 0 .../verilog/alexforencich/rtl/udp_arb_mux.v | 0 .../alexforencich/rtl/udp_checksum_gen.v | 0 .../alexforencich/rtl/udp_checksum_gen_64.v | 0 .../verilog/alexforencich/rtl/udp_complete.v | 0 .../alexforencich/rtl/udp_complete_64.v | 0 .../verilog/alexforencich/rtl/udp_demux.v | 0 .../verilog/alexforencich/rtl/udp_ip_rx.v | 0 .../verilog/alexforencich/rtl/udp_ip_rx_64.v | 0 .../verilog/alexforencich/rtl/udp_ip_tx.v | 0 .../verilog/alexforencich/rtl/udp_ip_tx_64.v | 0 .../verilog/alexforencich/rtl/udp_mux.v | 0 .../alexforencich/rtl/xgmii_baser_dec_64.v | 0 .../alexforencich/rtl/xgmii_baser_enc_64.v | 0 .../alexforencich/rtl/xgmii_deinterleave.v | 0 .../alexforencich/rtl/xgmii_interleave.v | 0 .../verilog/alexforencich/udp_core.v | 0 .../resources/verilog/sync_reset.v | 0 .../src}/Arty100TTop.scala | 0 .../src}/MinimalArty100T.scala | 0 .../src}/ZedboardTop.scala | 0 .../src}/basic/ClockDivider.scala | 0 .../src}/basic/SyncReset.scala | 0 .../src}/xilinx/Axi4BlockMemory.scala | 0 .../src}/xilinx/Axi4Crossbar.scala | 0 .../src}/xilinx/Axi4DataWidthConverter.scala | 0 .../src}/xilinx/Axi4LiteCrossbar.scala | 0 .../src}/xilinx/Axi4LiteGpio.scala | 0 .../src}/xilinx/Axi4LiteStreamDataFifo.scala | 0 .../src}/xilinx/Axi4LiteTimer.scala | 0 .../src}/xilinx/Axi4LiteUartLite.scala | 0 .../src}/xilinx/Axi4ProtocolConverter.scala | 0 .../src}/xilinx/Axi4QuadSpiFlash.scala | 0 .../src}/xilinx/Axi4SpiFlash.scala | 0 .../src}/xilinx/Axi4WiderMemory.scala | 0 .../src}/xilinx/ClockingWizard.scala | 0 .../src}/xilinx/FloatingPoint.scala | 0 .../src}/xilinx/IOBuffer.scala | 0 .../xilinx/bundle/Axi4BlackboxBundles.scala | 0 .../src}/xilinx/bundle/Axi4Bundles.scala | 0 .../src}/xilinx/bundle/Axi4Params.scala | 0 .../verilog/components/RamTestbench.sv | 0 .../verilog/components/plusarg_file_mem.sv | 0 .../examples/Axi4MemoryForTestTestbench.sv | 0 .../verilog/examples/Axi4SpiFlashTestBench.sv | 0 .../verilog/examples/AxiInterface.vh | 0 .../verilog/examples/UartTestbench.sv | 0 .../resources/vhdl/components/SimSpiFlash.vhd | 0 391 files changed, 26 insertions(+), 233 deletions(-) delete mode 100644 ChiselProject/src/generators/alexforencich/UDPCore.scala delete mode 100644 ChiselProject/test/resources/verilog/TestDriver.sv delete mode 100644 ChiselProject/test/resources/verilog/examples/GenericTestBench.sv delete mode 100644 ChiselProject/test/src/SyncRamSpec.scala rename {ChiselProject/src/generators/chipyard => module-chipyard-wrapper/src}/DigitalTop.scala (100%) rename {ChiselProject/src/examples => module-chipyard-wrapper/src}/MotorArty100T.scala (100%) rename {ChiselProject/src/examples => module-chipyard-wrapper/src}/TinyRocketArty100T.scala (100%) rename {ChiselProject/src/examples => module-chipyard-wrapper/src}/UdpTinyRocketArty100T.scala (100%) rename {ChiselProject => module-delta-soc}/resources/verilog/AsyncRam.v (100%) rename {ChiselProject => module-delta-soc}/resources/verilog/Ram.v (100%) rename {ChiselProject/test/resources/verilog/components => module-delta-soc/resources/verilog}/SimSpiFlashModel.sv (100%) rename {ChiselProject/test/resources/verilog/components => module-delta-soc/resources/verilog}/SimUart.sv (100%) rename {ChiselProject/test/resources/verilog/components => module-delta-soc/resources/verilog}/SpiFlashMemCtrl.sv (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/TestTiles.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/Tile.scala (100%) rename {ChiselProject/src/examples => module-delta-soc/src/configs}/MemorySubsystem.scala (97%) rename {ChiselProject/src/examples => module-delta-soc/src/configs}/MlpPolicyRunner.scala (90%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/constants/Constants.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/constants/Instructions.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/ALU.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/CSR.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/Core.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/InstructionDecode.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/InstructionFetch.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/LoadStore.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/SimdFloatingPoint.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/core/SimdLoadStore.scala (100%) rename {ChiselProject/src/generators => module-delta-soc/src}/interconnect/Axi4WidthDownsizer.scala (100%) rename {ChiselProject/src/generators => module-delta-soc/src}/interconnect/Axi4WidthUpsizer.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/memory/AsyncRam.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/memory/Axi4LiteMemory.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/memory/Axi4Memory.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/memory/Axi4MemoryWithLatency.scala (100%) rename {ChiselProject/src/generators/delta => module-delta-soc/src}/memory/Ram.scala (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/EECS151TileISATestbench.sv (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/EECS151TileTestbench.sv (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/EECS252TileTestbench.sv (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/InstructionFetchTestbench.sv (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/MemorySubsystemTestbench.sv (100%) rename {ChiselProject/test/resources/verilog/examples => module-delta-soc/test}/MlpPolicyRunnerTestbench.sv (100%) rename {ChiselProject/src/generators/tacit => module-tacit/src}/MadaTimer.scala (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/Arty-A7-100-Master.xdc (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/Arty_C_mig.ucf (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/Zedboard-Master.xdc (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/axis_async_fifo.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/eth_mac_fifo.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/mig.prj (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/mii_phy_if.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/constraints/sync_reset.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/Arty100TShell.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/.gitignore (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/.test_durations (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/AUTHORS (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/COPYING (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/README (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/README.md (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/axis/tox.ini (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/lib/update-axis.sh (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/arp.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/arp_cache.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/arp_eth_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/arp_eth_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_gmii_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_gmii_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_arb_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_axis_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_axis_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_demux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_10g.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_mii.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/gmii_phy_if.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/iddr.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_arb_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_complete.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_complete_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_demux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ip_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/lfsr.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/mii_phy_if.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/oddr.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_clock.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_perout.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_tag_insert.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_leaf.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_phc.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_ts_extract.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/rgmii_phy_if.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_in.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_out.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_in.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_out.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_arb_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_checksum_gen.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_complete.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_complete_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_demux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_rx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_tx.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/udp_mux.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_interleave.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/alexforencich/udp_core.v (100%) rename {ChiselProject => module-vivado-ips}/resources/verilog/sync_reset.v (100%) rename {ChiselProject/src/top => module-vivado-ips/src}/Arty100TTop.scala (100%) rename {ChiselProject/src/examples => module-vivado-ips/src}/MinimalArty100T.scala (100%) rename {ChiselProject/src/top => module-vivado-ips/src}/ZedboardTop.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/basic/ClockDivider.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/basic/SyncReset.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4BlockMemory.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4Crossbar.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4DataWidthConverter.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4LiteCrossbar.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4LiteGpio.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4LiteStreamDataFifo.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4LiteTimer.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4LiteUartLite.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4ProtocolConverter.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4QuadSpiFlash.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4SpiFlash.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/Axi4WiderMemory.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/ClockingWizard.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/FloatingPoint.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/IOBuffer.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/bundle/Axi4BlackboxBundles.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/bundle/Axi4Bundles.scala (100%) rename {ChiselProject/src/generators => module-vivado-ips/src}/xilinx/bundle/Axi4Params.scala (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/components/RamTestbench.sv (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/components/plusarg_file_mem.sv (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/examples/AxiInterface.vh (100%) rename {ChiselProject => module-vivado-ips}/test/resources/verilog/examples/UartTestbench.sv (100%) rename {ChiselProject => module-vivado-ips}/test/resources/vhdl/components/SimSpiFlash.vhd (100%) diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index 926edae..a64003e 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -17,9 +17,9 @@ jobs: - name: Build MemorySubsystem run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project CONFIG=MemorySubsystem + make project MODULE=delta-soc CONFIG=MemorySubsystem - name: Build MlpPolicyRunner run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project CONFIG=MlpPolicyRunner + make project MODULE=delta-soc CONFIG=MlpPolicyRunner diff --git a/ChiselProject/src/generators/alexforencich/UDPCore.scala b/ChiselProject/src/generators/alexforencich/UDPCore.scala deleted file mode 100644 index 1ff2a72..0000000 --- a/ChiselProject/src/generators/alexforencich/UDPCore.scala +++ /dev/null @@ -1,69 +0,0 @@ -import chisel3.{BlackBox, _} -import chisel3.util._ -import chisel3.experimental.IntParam - - -class udp_core( - mac_address: Long = 0x02_00_00_00_00_00L, - ip_address: Int = 0xC0_A8_01_80, - gateway_ip: Int = 0xC0_A8_01_01, - subnet_mask: Int = 0xFF_FF_FF_00, - udp_port: Int = 1234 -) extends BlackBox(Map( - "MAC_ADDRESS" -> IntParam(mac_address), - "IP_ADDRESS" -> IntParam(ip_address), - "GATEWAY_IP" -> IntParam(gateway_ip), - "SUBNET_MASK" -> IntParam(subnet_mask), - "UDP_PORT" -> IntParam(udp_port) - )) with HasBlackBoxResource { - val io = IO(new Bundle { - val clk = Input(Clock()) - val rst = Input(Reset()) - - val btn = Input(UInt(4.W)) - val sw = Input(UInt(4.W)) - val led0_r = Output(Bool()) - val led0_g = Output(Bool()) - val led0_b = Output(Bool()) - val led1_r = Output(Bool()) - val led1_g = Output(Bool()) - val led1_b = Output(Bool()) - val led2_r = Output(Bool()) - val led2_g = Output(Bool()) - val led2_b = Output(Bool()) - val led3_r = Output(Bool()) - val led3_g = Output(Bool()) - val led3_b = Output(Bool()) - val led4 = Output(Bool()) - val led5 = Output(Bool()) - val led6 = Output(Bool()) - val led7 = Output(Bool()) - - val phy_rx_clk = Input(Bool()) - val phy_rxd = Input(UInt(4.W)) - val phy_rx_dv = Input(Bool()) - val phy_rx_er = Input(Bool()) - val phy_tx_clk = Input(Bool()) - val phy_txd = Output(UInt(4.W)) - val phy_tx_en = Output(Bool()) - val phy_col = Input(Bool()) - val phy_crs = Input(Bool()) - val phy_reset_n = Output(Bool()) - - val uart_rxd = Input(Bool()) - val uart_txd = Output(Bool()) - - val rx_fifo_udp_payload_axis_tdata = Output(UInt(8.W)) - val rx_fifo_udp_payload_axis_tvalid = Output(Bool()) - val rx_fifo_udp_payload_axis_tready = Input(Bool()) - val rx_fifo_udp_payload_axis_tlast = Output(Bool()) - val rx_fifo_udp_payload_axis_tuser = Output(Bool()) - - val tx_fifo_udp_payload_axis_tdata = Input(UInt(8.W)) - val tx_fifo_udp_payload_axis_tvalid = Input(Bool()) - val tx_fifo_udp_payload_axis_tready = Output(Bool()) - val tx_fifo_udp_payload_axis_tlast = Input(Bool()) - val tx_fifo_udp_payload_axis_tuser = Input(Bool()) - }) -} - diff --git a/ChiselProject/test/resources/verilog/TestDriver.sv b/ChiselProject/test/resources/verilog/TestDriver.sv deleted file mode 100644 index 5407275..0000000 --- a/ChiselProject/test/resources/verilog/TestDriver.sv +++ /dev/null @@ -1,25 +0,0 @@ -`timescale 1ns / 1ps - - -module TestDriver( - output logic clock, - output logic reset -); - parameter CLOCK_FREQ = 100_000_000; - parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ; - - // setup clock and reset - reg clock, reset; - initial clock = 'b0; - always #(CLOCK_PERIOD/2) clock = ~clock; - - initial begin - reset = 1'b1; - repeat (10) @(posedge clock); - reset = 1'b0; - - repeat (10000) @(posedge clock); - $finish; - end - -endmodule diff --git a/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv b/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv deleted file mode 100644 index 05eb236..0000000 --- a/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv +++ /dev/null @@ -1,77 +0,0 @@ -`timescale 1ns / 1ps - - -module GenericTestBench(); - parameter CLOCK_FREQ = 100_000_000; - parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ; - - // setup clock and reset - reg clock, reset; - initial clock = 'b0; - always #(CLOCK_PERIOD/2) clock = ~clock; - - logic led; - - - wire IO0_IO; - wire IO1_IO; - wire SCK_IO; - wire SS_IO; - - - - SimSpiFlashModel #( - .PLUSARG("firmware.8.hex"), - .READONLY(0), - .CAPACITY_BYTES(1024) - ) sim_spi ( - .sck(SCK_IO), - .cs_0(SS_IO), - .reset(reset), - .dq_0(IO0_IO), - .dq_1(IO1_IO), - .dq_2(), - .dq_3() - ); - - BiliArty100T dut( - .io_CLK100MHZ(clock), - .io_sw(4'b0), - .io_btn(4'b0), - .io_ja_0(), - .io_ja_1(), - .io_ja_2(), - .io_ja_3(), - .io_ja_4(), - .io_ja_5(), - .io_ja_6(), - .io_ja_7(), - .io_uart_txd_in(1'b0), - .io_uart_rxd_out(), - .io_ck_ioa(1'b0), - .io_ck_rst(~reset), - .io_eth_col(1'b0), - .io_eth_crs(1'b0), - .io_eth_rx_clk(1'b0), - .io_eth_rx_dv(1'b0), - .io_eth_rxd(4'b0), - .io_eth_rxerr(1'b0), - .io_eth_tx_clk(1'b0), - .io_qspi_cs(SS_IO), - .io_qspi_sck(SCK_IO), - .io_qspi_dq_0(IO0_IO), - .io_qspi_dq_1(IO1_IO), - .io_qspi_dq_2(), - .io_qspi_dq_3(), - .io_led(led) - ); - - initial begin - reset = 1'b1; - repeat (10) @(posedge clock); - reset = 1'b0; - - repeat (10000) @(posedge clock); - $finish; - end -endmodule diff --git a/ChiselProject/test/src/SyncRamSpec.scala b/ChiselProject/test/src/SyncRamSpec.scala deleted file mode 100644 index cc907e0..0000000 --- a/ChiselProject/test/src/SyncRamSpec.scala +++ /dev/null @@ -1,41 +0,0 @@ -import chisel3._ -import chisel3.experimental.BundleLiterals._ -import chisel3.simulator.EphemeralSimulator._ -import org.scalatest.flatspec.AnyFlatSpec -import org.scalatest.matchers.must.Matchers - - -class SyncRamSpec extends AnyFlatSpec { - behavior of "SyncRam" - it should "do something" in { - simulate(new SimRam) { dut => - dut.reset.poke(true.B) - - for (i <- 0 until 10) { - dut.clock.step() - } - dut.reset.poke(false.B) - - dut.io.waddr.poke(0x00000000.U) - dut.io.wstrb.poke(0x0F.U) - dut.io.wdata.poke(0xDEADBEEFL.U) - dut.clock.step() - dut.io.waddr.poke(0x00000000.U) - dut.io.wstrb.poke(0x00.U) - dut.io.wdata.poke(0x00000000.U) - dut.io.raddr.poke(0x00000000.U) - dut.clock.step() - dut.io.rdata.expect(0xDEADBEEFL.U) - - dut.io.waddr.poke(0x00000004.U) - dut.io.wstrb.poke(0x0F.U) - dut.io.wdata.poke(0xDEADBEEFL.U) - dut.clock.step() - dut.io.waddr.poke(0x00000000.U) - dut.io.wdata.poke(0x00000000.U) - dut.io.raddr.poke(0x00000004.U) - dut.clock.step() - dut.io.rdata.expect(0x0000BEEFL.U) - } - } -} \ No newline at end of file diff --git a/Makefile b/Makefile index e7b0851..2013128 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,6 @@ BUILD_DIR = ./generated-src -MODULE = ChiselProject +MODULE = vivado-ips CONFIG ?= MinimalArty100T @@ -8,16 +8,16 @@ MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - $(MILL_PATH) -i $(MODULE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i module-$(MODULE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) project: verilog - $(MILL_PATH) -i $(MODULE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i module-$(MODULE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) bitstream: project - $(MILL_PATH) -i $(MODULE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i module-$(MODULE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) test: - $(MILL_PATH) -i $(MODULE).Test + $(MILL_PATH) -i module-$(MODULE).Test clean: rm -rf $(BUILD_DIR) diff --git a/build.mill.scala b/build.mill.scala index cb2ecb2..4e04fa8 100644 --- a/build.mill.scala +++ b/build.mill.scala @@ -56,10 +56,15 @@ trait ChiselModule extends ScalaModule with ScalafmtModule { m => object builder extends ChiselModule -/** - * Main build definition for the Chisel project. - * This object defines the project structure and its dependencies. - */ -object ChiselProject extends ChiselModule { m => +object `module-vivado-ips` extends ChiselModule { m => override def moduleDeps = Seq(builder) } + +object `module-delta-soc` extends ChiselModule { m => + override def moduleDeps = Seq(builder, `module-vivado-ips`) +} + +object `module-chipyard-wrapper` extends ChiselModule { m => + override def moduleDeps = Seq(builder, `module-vivado-ips`) +} + diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 9821b9c..388c954 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -15,8 +15,8 @@ import java.io.FileWriter object BuilderConfig { val chiselGeneratedFilelist = "generated-src/filelist.f" - val simulationFilelist = "generated-src/sim_filelist.f" - val constraintsFilelist = "generated-src/constraints_filelist.f" + val simulationFilelist = "generated-src/filelist_simulation.f" + val constraintsFilelist = "generated-src/filelist_constraints.f" val vivadoProjectDir = "out/vivado-project" } diff --git a/ChiselProject/src/generators/chipyard/DigitalTop.scala b/module-chipyard-wrapper/src/DigitalTop.scala similarity index 100% rename from ChiselProject/src/generators/chipyard/DigitalTop.scala rename to module-chipyard-wrapper/src/DigitalTop.scala diff --git a/ChiselProject/src/examples/MotorArty100T.scala b/module-chipyard-wrapper/src/MotorArty100T.scala similarity index 100% rename from ChiselProject/src/examples/MotorArty100T.scala rename to module-chipyard-wrapper/src/MotorArty100T.scala diff --git a/ChiselProject/src/examples/TinyRocketArty100T.scala b/module-chipyard-wrapper/src/TinyRocketArty100T.scala similarity index 100% rename from ChiselProject/src/examples/TinyRocketArty100T.scala rename to module-chipyard-wrapper/src/TinyRocketArty100T.scala diff --git a/ChiselProject/src/examples/UdpTinyRocketArty100T.scala b/module-chipyard-wrapper/src/UdpTinyRocketArty100T.scala similarity index 100% rename from ChiselProject/src/examples/UdpTinyRocketArty100T.scala rename to module-chipyard-wrapper/src/UdpTinyRocketArty100T.scala diff --git a/ChiselProject/resources/verilog/AsyncRam.v b/module-delta-soc/resources/verilog/AsyncRam.v similarity index 100% rename from ChiselProject/resources/verilog/AsyncRam.v rename to module-delta-soc/resources/verilog/AsyncRam.v diff --git a/ChiselProject/resources/verilog/Ram.v b/module-delta-soc/resources/verilog/Ram.v similarity index 100% rename from ChiselProject/resources/verilog/Ram.v rename to module-delta-soc/resources/verilog/Ram.v diff --git a/ChiselProject/test/resources/verilog/components/SimSpiFlashModel.sv b/module-delta-soc/resources/verilog/SimSpiFlashModel.sv similarity index 100% rename from ChiselProject/test/resources/verilog/components/SimSpiFlashModel.sv rename to module-delta-soc/resources/verilog/SimSpiFlashModel.sv diff --git a/ChiselProject/test/resources/verilog/components/SimUart.sv b/module-delta-soc/resources/verilog/SimUart.sv similarity index 100% rename from ChiselProject/test/resources/verilog/components/SimUart.sv rename to module-delta-soc/resources/verilog/SimUart.sv diff --git a/ChiselProject/test/resources/verilog/components/SpiFlashMemCtrl.sv b/module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv similarity index 100% rename from ChiselProject/test/resources/verilog/components/SpiFlashMemCtrl.sv rename to module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv diff --git a/ChiselProject/src/generators/delta/TestTiles.scala b/module-delta-soc/src/TestTiles.scala similarity index 100% rename from ChiselProject/src/generators/delta/TestTiles.scala rename to module-delta-soc/src/TestTiles.scala diff --git a/ChiselProject/src/generators/delta/Tile.scala b/module-delta-soc/src/Tile.scala similarity index 100% rename from ChiselProject/src/generators/delta/Tile.scala rename to module-delta-soc/src/Tile.scala diff --git a/ChiselProject/src/examples/MemorySubsystem.scala b/module-delta-soc/src/configs/MemorySubsystem.scala similarity index 97% rename from ChiselProject/src/examples/MemorySubsystem.scala rename to module-delta-soc/src/configs/MemorySubsystem.scala index a1dc120..fc24158 100644 --- a/ChiselProject/src/examples/MemorySubsystem.scala +++ b/module-delta-soc/src/configs/MemorySubsystem.scala @@ -132,12 +132,10 @@ class MemorySubsystem extends Module { flash.io.s_axi := DontCare flash.io.io0_i := false.B flash.io.io1_i := true.B - // flash.io.sck_i := false.B flash.io.ss_i := false.B - // io.qspi_sck := flash.io.sck_o.asClock + io.qspi_sck := DontCare io.qspi_cs := flash.io.ss_o - // flash.io.sck_i := 0.B flash.io.ss_i := 0.B val qspi_io0_buf = Module(new IOBUF()) diff --git a/ChiselProject/src/examples/MlpPolicyRunner.scala b/module-delta-soc/src/configs/MlpPolicyRunner.scala similarity index 90% rename from ChiselProject/src/examples/MlpPolicyRunner.scala rename to module-delta-soc/src/configs/MlpPolicyRunner.scala index d7a95dc..1d6331d 100644 --- a/ChiselProject/src/examples/MlpPolicyRunner.scala +++ b/module-delta-soc/src/configs/MlpPolicyRunner.scala @@ -172,9 +172,11 @@ class MlpPolicyRunner extends RawModule { } + addConstraintResource("module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") - - addConstraintResource("ChiselProject/resources/constraints/Arty-A7-100-Master.xdc") - - addSimulationResource("ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv") + addSimulationResource("module-delta-soc/test/MlpPolicyRunnerTestbench.sv") + addSimulationResource("module-delta-soc/resources/verilog/SimUart.sv") + addSimulationResource("module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") + addSimulationResource("module-delta-soc/resources/verilog/SimSpiFlashModel.sv") + addSimulationResource("module-delta-soc/resources/verilog/Ram.v") } diff --git a/ChiselProject/src/generators/delta/constants/Constants.scala b/module-delta-soc/src/constants/Constants.scala similarity index 100% rename from ChiselProject/src/generators/delta/constants/Constants.scala rename to module-delta-soc/src/constants/Constants.scala diff --git a/ChiselProject/src/generators/delta/constants/Instructions.scala b/module-delta-soc/src/constants/Instructions.scala similarity index 100% rename from ChiselProject/src/generators/delta/constants/Instructions.scala rename to module-delta-soc/src/constants/Instructions.scala diff --git a/ChiselProject/src/generators/delta/core/ALU.scala b/module-delta-soc/src/core/ALU.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/ALU.scala rename to module-delta-soc/src/core/ALU.scala diff --git a/ChiselProject/src/generators/delta/core/CSR.scala b/module-delta-soc/src/core/CSR.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/CSR.scala rename to module-delta-soc/src/core/CSR.scala diff --git a/ChiselProject/src/generators/delta/core/Core.scala b/module-delta-soc/src/core/Core.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/Core.scala rename to module-delta-soc/src/core/Core.scala diff --git a/ChiselProject/src/generators/delta/core/InstructionDecode.scala b/module-delta-soc/src/core/InstructionDecode.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/InstructionDecode.scala rename to module-delta-soc/src/core/InstructionDecode.scala diff --git a/ChiselProject/src/generators/delta/core/InstructionFetch.scala b/module-delta-soc/src/core/InstructionFetch.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/InstructionFetch.scala rename to module-delta-soc/src/core/InstructionFetch.scala diff --git a/ChiselProject/src/generators/delta/core/LoadStore.scala b/module-delta-soc/src/core/LoadStore.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/LoadStore.scala rename to module-delta-soc/src/core/LoadStore.scala diff --git a/ChiselProject/src/generators/delta/core/SimdFloatingPoint.scala b/module-delta-soc/src/core/SimdFloatingPoint.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/SimdFloatingPoint.scala rename to module-delta-soc/src/core/SimdFloatingPoint.scala diff --git a/ChiselProject/src/generators/delta/core/SimdLoadStore.scala b/module-delta-soc/src/core/SimdLoadStore.scala similarity index 100% rename from ChiselProject/src/generators/delta/core/SimdLoadStore.scala rename to module-delta-soc/src/core/SimdLoadStore.scala diff --git a/ChiselProject/src/generators/interconnect/Axi4WidthDownsizer.scala b/module-delta-soc/src/interconnect/Axi4WidthDownsizer.scala similarity index 100% rename from ChiselProject/src/generators/interconnect/Axi4WidthDownsizer.scala rename to module-delta-soc/src/interconnect/Axi4WidthDownsizer.scala diff --git a/ChiselProject/src/generators/interconnect/Axi4WidthUpsizer.scala b/module-delta-soc/src/interconnect/Axi4WidthUpsizer.scala similarity index 100% rename from ChiselProject/src/generators/interconnect/Axi4WidthUpsizer.scala rename to module-delta-soc/src/interconnect/Axi4WidthUpsizer.scala diff --git a/ChiselProject/src/generators/delta/memory/AsyncRam.scala b/module-delta-soc/src/memory/AsyncRam.scala similarity index 100% rename from ChiselProject/src/generators/delta/memory/AsyncRam.scala rename to module-delta-soc/src/memory/AsyncRam.scala diff --git a/ChiselProject/src/generators/delta/memory/Axi4LiteMemory.scala b/module-delta-soc/src/memory/Axi4LiteMemory.scala similarity index 100% rename from ChiselProject/src/generators/delta/memory/Axi4LiteMemory.scala rename to module-delta-soc/src/memory/Axi4LiteMemory.scala diff --git a/ChiselProject/src/generators/delta/memory/Axi4Memory.scala b/module-delta-soc/src/memory/Axi4Memory.scala similarity index 100% rename from ChiselProject/src/generators/delta/memory/Axi4Memory.scala rename to module-delta-soc/src/memory/Axi4Memory.scala diff --git a/ChiselProject/src/generators/delta/memory/Axi4MemoryWithLatency.scala b/module-delta-soc/src/memory/Axi4MemoryWithLatency.scala similarity index 100% rename from ChiselProject/src/generators/delta/memory/Axi4MemoryWithLatency.scala rename to module-delta-soc/src/memory/Axi4MemoryWithLatency.scala diff --git a/ChiselProject/src/generators/delta/memory/Ram.scala b/module-delta-soc/src/memory/Ram.scala similarity index 100% rename from ChiselProject/src/generators/delta/memory/Ram.scala rename to module-delta-soc/src/memory/Ram.scala diff --git a/ChiselProject/test/resources/verilog/examples/EECS151TileISATestbench.sv b/module-delta-soc/test/EECS151TileISATestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/EECS151TileISATestbench.sv rename to module-delta-soc/test/EECS151TileISATestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/EECS151TileTestbench.sv b/module-delta-soc/test/EECS151TileTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/EECS151TileTestbench.sv rename to module-delta-soc/test/EECS151TileTestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/EECS252TileTestbench.sv b/module-delta-soc/test/EECS252TileTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/EECS252TileTestbench.sv rename to module-delta-soc/test/EECS252TileTestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/InstructionFetchTestbench.sv b/module-delta-soc/test/InstructionFetchTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/InstructionFetchTestbench.sv rename to module-delta-soc/test/InstructionFetchTestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/MemorySubsystemTestbench.sv b/module-delta-soc/test/MemorySubsystemTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/MemorySubsystemTestbench.sv rename to module-delta-soc/test/MemorySubsystemTestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv b/module-delta-soc/test/MlpPolicyRunnerTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv rename to module-delta-soc/test/MlpPolicyRunnerTestbench.sv diff --git a/ChiselProject/src/generators/tacit/MadaTimer.scala b/module-tacit/src/MadaTimer.scala similarity index 100% rename from ChiselProject/src/generators/tacit/MadaTimer.scala rename to module-tacit/src/MadaTimer.scala diff --git a/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc b/module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc similarity index 100% rename from ChiselProject/resources/constraints/Arty-A7-100-Master.xdc rename to module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc diff --git a/ChiselProject/resources/constraints/Arty_C_mig.ucf b/module-vivado-ips/resources/constraints/Arty_C_mig.ucf similarity index 100% rename from ChiselProject/resources/constraints/Arty_C_mig.ucf rename to module-vivado-ips/resources/constraints/Arty_C_mig.ucf diff --git a/ChiselProject/resources/constraints/Zedboard-Master.xdc b/module-vivado-ips/resources/constraints/Zedboard-Master.xdc similarity index 100% rename from ChiselProject/resources/constraints/Zedboard-Master.xdc rename to module-vivado-ips/resources/constraints/Zedboard-Master.xdc diff --git a/ChiselProject/resources/constraints/axis_async_fifo.tcl b/module-vivado-ips/resources/constraints/axis_async_fifo.tcl similarity index 100% rename from ChiselProject/resources/constraints/axis_async_fifo.tcl rename to module-vivado-ips/resources/constraints/axis_async_fifo.tcl diff --git a/ChiselProject/resources/constraints/eth_mac_fifo.tcl b/module-vivado-ips/resources/constraints/eth_mac_fifo.tcl similarity index 100% rename from ChiselProject/resources/constraints/eth_mac_fifo.tcl rename to module-vivado-ips/resources/constraints/eth_mac_fifo.tcl diff --git a/ChiselProject/resources/constraints/mig.prj b/module-vivado-ips/resources/constraints/mig.prj similarity index 100% rename from ChiselProject/resources/constraints/mig.prj rename to module-vivado-ips/resources/constraints/mig.prj diff --git a/ChiselProject/resources/constraints/mii_phy_if.tcl b/module-vivado-ips/resources/constraints/mii_phy_if.tcl similarity index 100% rename from ChiselProject/resources/constraints/mii_phy_if.tcl rename to module-vivado-ips/resources/constraints/mii_phy_if.tcl diff --git a/ChiselProject/resources/constraints/sync_reset.tcl b/module-vivado-ips/resources/constraints/sync_reset.tcl similarity index 100% rename from ChiselProject/resources/constraints/sync_reset.tcl rename to module-vivado-ips/resources/constraints/sync_reset.tcl diff --git a/ChiselProject/resources/verilog/Arty100TShell.v b/module-vivado-ips/resources/verilog/Arty100TShell.v similarity index 100% rename from ChiselProject/resources/verilog/Arty100TShell.v rename to module-vivado-ips/resources/verilog/Arty100TShell.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.gitignore b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.gitignore rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.test_durations b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.test_durations rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/AUTHORS b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/AUTHORS rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/COPYING b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/COPYING rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/README b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/README similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/README rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/README diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/README.md b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/README.md rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tox.ini b/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tox.ini rename to module-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini diff --git a/ChiselProject/resources/verilog/alexforencich/lib/update-axis.sh b/module-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/lib/update-axis.sh rename to module-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/arp.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/arp.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/arp.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/arp.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/arp_cache.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/arp_cache.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/arp_eth_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/arp_eth_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/arp_eth_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/arp_eth_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_gmii_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_gmii_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_gmii_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_gmii_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_arb_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_arb_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_axis_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_axis_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_axis_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_axis_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_demux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_demux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_10g.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_10g.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/gmii_phy_if.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/gmii_phy_if.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/iddr.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/iddr.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_arb_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_arb_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_complete.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_complete.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_complete_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_complete_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_demux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_demux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/lfsr.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/lfsr.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mii_phy_if.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/mii_phy_if.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/oddr.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/oddr.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_perout.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_perout.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_tag_insert.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_tag_insert.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_leaf.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_leaf.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_phc.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_phc.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_ts_extract.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_ts_extract.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/rgmii_phy_if.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/rgmii_phy_if.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_arb_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_arb_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_complete.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_complete.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_complete_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_complete_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_demux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_demux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_mux.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_mux.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_interleave.v b/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_interleave.v rename to module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v diff --git a/ChiselProject/resources/verilog/alexforencich/udp_core.v b/module-vivado-ips/resources/verilog/alexforencich/udp_core.v similarity index 100% rename from ChiselProject/resources/verilog/alexforencich/udp_core.v rename to module-vivado-ips/resources/verilog/alexforencich/udp_core.v diff --git a/ChiselProject/resources/verilog/sync_reset.v b/module-vivado-ips/resources/verilog/sync_reset.v similarity index 100% rename from ChiselProject/resources/verilog/sync_reset.v rename to module-vivado-ips/resources/verilog/sync_reset.v diff --git a/ChiselProject/src/top/Arty100TTop.scala b/module-vivado-ips/src/Arty100TTop.scala similarity index 100% rename from ChiselProject/src/top/Arty100TTop.scala rename to module-vivado-ips/src/Arty100TTop.scala diff --git a/ChiselProject/src/examples/MinimalArty100T.scala b/module-vivado-ips/src/MinimalArty100T.scala similarity index 100% rename from ChiselProject/src/examples/MinimalArty100T.scala rename to module-vivado-ips/src/MinimalArty100T.scala diff --git a/ChiselProject/src/top/ZedboardTop.scala b/module-vivado-ips/src/ZedboardTop.scala similarity index 100% rename from ChiselProject/src/top/ZedboardTop.scala rename to module-vivado-ips/src/ZedboardTop.scala diff --git a/ChiselProject/src/generators/basic/ClockDivider.scala b/module-vivado-ips/src/basic/ClockDivider.scala similarity index 100% rename from ChiselProject/src/generators/basic/ClockDivider.scala rename to module-vivado-ips/src/basic/ClockDivider.scala diff --git a/ChiselProject/src/generators/basic/SyncReset.scala b/module-vivado-ips/src/basic/SyncReset.scala similarity index 100% rename from ChiselProject/src/generators/basic/SyncReset.scala rename to module-vivado-ips/src/basic/SyncReset.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala b/module-vivado-ips/src/xilinx/Axi4BlockMemory.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala rename to module-vivado-ips/src/xilinx/Axi4BlockMemory.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala b/module-vivado-ips/src/xilinx/Axi4Crossbar.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4Crossbar.scala rename to module-vivado-ips/src/xilinx/Axi4Crossbar.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala b/module-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala rename to module-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala b/module-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala rename to module-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala b/module-vivado-ips/src/xilinx/Axi4LiteGpio.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala rename to module-vivado-ips/src/xilinx/Axi4LiteGpio.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala b/module-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala rename to module-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala b/module-vivado-ips/src/xilinx/Axi4LiteTimer.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala rename to module-vivado-ips/src/xilinx/Axi4LiteTimer.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala b/module-vivado-ips/src/xilinx/Axi4LiteUartLite.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala rename to module-vivado-ips/src/xilinx/Axi4LiteUartLite.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala b/module-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala rename to module-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala b/module-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala rename to module-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala b/module-vivado-ips/src/xilinx/Axi4SpiFlash.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala rename to module-vivado-ips/src/xilinx/Axi4SpiFlash.scala diff --git a/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala b/module-vivado-ips/src/xilinx/Axi4WiderMemory.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala rename to module-vivado-ips/src/xilinx/Axi4WiderMemory.scala diff --git a/ChiselProject/src/generators/xilinx/ClockingWizard.scala b/module-vivado-ips/src/xilinx/ClockingWizard.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/ClockingWizard.scala rename to module-vivado-ips/src/xilinx/ClockingWizard.scala diff --git a/ChiselProject/src/generators/xilinx/FloatingPoint.scala b/module-vivado-ips/src/xilinx/FloatingPoint.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/FloatingPoint.scala rename to module-vivado-ips/src/xilinx/FloatingPoint.scala diff --git a/ChiselProject/src/generators/xilinx/IOBuffer.scala b/module-vivado-ips/src/xilinx/IOBuffer.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/IOBuffer.scala rename to module-vivado-ips/src/xilinx/IOBuffer.scala diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4BlackboxBundles.scala b/module-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/bundle/Axi4BlackboxBundles.scala rename to module-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4Bundles.scala b/module-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/bundle/Axi4Bundles.scala rename to module-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4Params.scala b/module-vivado-ips/src/xilinx/bundle/Axi4Params.scala similarity index 100% rename from ChiselProject/src/generators/xilinx/bundle/Axi4Params.scala rename to module-vivado-ips/src/xilinx/bundle/Axi4Params.scala diff --git a/ChiselProject/test/resources/verilog/components/RamTestbench.sv b/module-vivado-ips/test/resources/verilog/components/RamTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/components/RamTestbench.sv rename to module-vivado-ips/test/resources/verilog/components/RamTestbench.sv diff --git a/ChiselProject/test/resources/verilog/components/plusarg_file_mem.sv b/module-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv similarity index 100% rename from ChiselProject/test/resources/verilog/components/plusarg_file_mem.sv rename to module-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv diff --git a/ChiselProject/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv b/module-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv rename to module-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv diff --git a/ChiselProject/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv b/module-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv rename to module-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv diff --git a/ChiselProject/test/resources/verilog/examples/AxiInterface.vh b/module-vivado-ips/test/resources/verilog/examples/AxiInterface.vh similarity index 100% rename from ChiselProject/test/resources/verilog/examples/AxiInterface.vh rename to module-vivado-ips/test/resources/verilog/examples/AxiInterface.vh diff --git a/ChiselProject/test/resources/verilog/examples/UartTestbench.sv b/module-vivado-ips/test/resources/verilog/examples/UartTestbench.sv similarity index 100% rename from ChiselProject/test/resources/verilog/examples/UartTestbench.sv rename to module-vivado-ips/test/resources/verilog/examples/UartTestbench.sv diff --git a/ChiselProject/test/resources/vhdl/components/SimSpiFlash.vhd b/module-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd similarity index 100% rename from ChiselProject/test/resources/vhdl/components/SimSpiFlash.vhd rename to module-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd From a2bd1c54807c0ea20aff28efb633ad22138f88ae Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 00:29:34 -0700 Subject: [PATCH 07/18] REFACTOR: rename modules to packages --- build.mill.scala | 10 +++++----- .../src/DigitalTop.scala | 0 .../src/MotorArty100T.scala | 0 .../src/TinyRocketArty100T.scala | 0 .../src/UdpTinyRocketArty100T.scala | 0 .../resources/verilog/AsyncRam.v | 0 .../resources/verilog/Ram.v | 0 .../resources/verilog/SimSpiFlashModel.sv | 0 .../resources/verilog/SimUart.sv | 0 .../resources/verilog/SpiFlashMemCtrl.sv | 0 .../src/TestTiles.scala | 0 {module-delta-soc => package-delta-soc}/src/Tile.scala | 0 .../src/configs/MemorySubsystem.scala | 0 .../src/configs/MlpPolicyRunner.scala | 0 .../src/constants/Constants.scala | 0 .../src/constants/Instructions.scala | 0 .../src/core/ALU.scala | 0 .../src/core/CSR.scala | 0 .../src/core/Core.scala | 0 .../src/core/InstructionDecode.scala | 0 .../src/core/InstructionFetch.scala | 0 .../src/core/LoadStore.scala | 0 .../src/core/SimdFloatingPoint.scala | 0 .../src/core/SimdLoadStore.scala | 0 .../src/interconnect/Axi4WidthDownsizer.scala | 0 .../src/interconnect/Axi4WidthUpsizer.scala | 0 .../src/memory/AsyncRam.scala | 0 .../src/memory/Axi4LiteMemory.scala | 0 .../src/memory/Axi4Memory.scala | 0 .../src/memory/Axi4MemoryWithLatency.scala | 0 .../src/memory/Ram.scala | 0 .../test/EECS151TileISATestbench.sv | 0 .../test/EECS151TileTestbench.sv | 0 .../test/EECS252TileTestbench.sv | 0 .../test/InstructionFetchTestbench.sv | 0 .../test/MemorySubsystemTestbench.sv | 0 .../test/MlpPolicyRunnerTestbench.sv | 0 {module-tacit => package-tacit}/src/MadaTimer.scala | 0 .../resources/constraints/Arty-A7-100-Master.xdc | 0 .../resources/constraints/Arty_C_mig.ucf | 0 .../resources/constraints/Zedboard-Master.xdc | 0 .../resources/constraints/axis_async_fifo.tcl | 0 .../resources/constraints/eth_mac_fifo.tcl | 0 .../resources/constraints/mig.prj | 0 .../resources/constraints/mii_phy_if.tcl | 0 .../resources/constraints/sync_reset.tcl | 0 .../resources/verilog/Arty100TShell.v | 0 .../lib/axis/.github/workflows/regression-tests.yml | 0 .../verilog/alexforencich/lib/axis/.gitignore | 0 .../verilog/alexforencich/lib/axis/.test_durations | 0 .../resources/verilog/alexforencich/lib/axis/AUTHORS | 0 .../resources/verilog/alexforencich/lib/axis/COPYING | 0 .../resources/verilog/alexforencich/lib/axis/README | 0 .../resources/verilog/alexforencich/lib/axis/README.md | 0 .../verilog/alexforencich/lib/axis/rtl/arbiter.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_adapter.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v | 0 .../alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_async_fifo.v | 0 .../lib/axis/rtl/axis_async_fifo_adapter.v | 0 .../alexforencich/lib/axis/rtl/axis_broadcast.v | 0 .../alexforencich/lib/axis/rtl/axis_broadcast_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_cobs_decode.v | 0 .../alexforencich/lib/axis/rtl/axis_cobs_encode.v | 0 .../alexforencich/lib/axis/rtl/axis_crosspoint.v | 0 .../alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py | 0 .../verilog/alexforencich/lib/axis/rtl/axis_demux.v | 0 .../alexforencich/lib/axis/rtl/axis_demux_wrap.py | 0 .../verilog/alexforencich/lib/axis/rtl/axis_fifo.v | 0 .../alexforencich/lib/axis/rtl/axis_fifo_adapter.v | 0 .../alexforencich/lib/axis/rtl/axis_frame_join.v | 0 .../alexforencich/lib/axis/rtl/axis_frame_join_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_frame_len.v | 0 .../lib/axis/rtl/axis_frame_length_adjust.v | 0 .../lib/axis/rtl/axis_frame_length_adjust_fifo.v | 0 .../alexforencich/lib/axis/rtl/axis_ll_bridge.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_mux.v | 0 .../alexforencich/lib/axis/rtl/axis_mux_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_pipeline_fifo.v | 0 .../lib/axis/rtl/axis_pipeline_register.v | 0 .../alexforencich/lib/axis/rtl/axis_ram_switch.v | 0 .../alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py | 0 .../alexforencich/lib/axis/rtl/axis_rate_limit.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_register.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v | 0 .../alexforencich/lib/axis/rtl/axis_srl_register.v | 0 .../alexforencich/lib/axis/rtl/axis_stat_counter.v | 0 .../verilog/alexforencich/lib/axis/rtl/axis_switch.v | 0 .../alexforencich/lib/axis/rtl/axis_switch_wrap.py | 0 .../verilog/alexforencich/lib/axis/rtl/axis_tap.v | 0 .../alexforencich/lib/axis/rtl/ll_axis_bridge.v | 0 .../alexforencich/lib/axis/rtl/priority_encoder.v | 0 .../verilog/alexforencich/lib/axis/rtl/sync_reset.v | 0 .../lib/axis/syn/quartus/axis_async_fifo.sdc | 0 .../alexforencich/lib/axis/syn/quartus/sync_reset.sdc | 0 .../lib/axis/syn/quartus_pro/axis_async_fifo.sdc | 0 .../lib/axis/syn/quartus_pro/sync_reset.sdc | 0 .../lib/axis/syn/vivado/axis_async_fifo.tcl | 0 .../alexforencich/lib/axis/syn/vivado/sync_reset.tcl | 0 .../verilog/alexforencich/lib/axis/tb/Makefile | 0 .../alexforencich/lib/axis/tb/axis_adapter/Makefile | 0 .../lib/axis/tb/axis_adapter/test_axis_adapter.py | 0 .../alexforencich/lib/axis/tb/axis_arb_mux/Makefile | 0 .../lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py | 0 .../alexforencich/lib/axis/tb/axis_async_fifo/Makefile | 0 .../axis/tb/axis_async_fifo/test_axis_async_fifo.py | 0 .../lib/axis/tb/axis_async_fifo_adapter/Makefile | 0 .../test_axis_async_fifo_adapter.py | 0 .../alexforencich/lib/axis/tb/axis_broadcast/Makefile | 0 .../lib/axis/tb/axis_broadcast/test_axis_broadcast.py | 0 .../lib/axis/tb/axis_cobs_decode/Makefile | 0 .../axis/tb/axis_cobs_decode/test_axis_cobs_decode.py | 0 .../lib/axis/tb/axis_cobs_encode/Makefile | 0 .../axis/tb/axis_cobs_encode/test_axis_cobs_encode.py | 0 .../alexforencich/lib/axis/tb/axis_demux/Makefile | 0 .../lib/axis/tb/axis_demux/test_axis_demux.py | 0 .../verilog/alexforencich/lib/axis/tb/axis_ep.py | 0 .../alexforencich/lib/axis/tb/axis_fifo/Makefile | 0 .../lib/axis/tb/axis_fifo/test_axis_fifo.py | 0 .../lib/axis/tb/axis_fifo_adapter/Makefile | 0 .../tb/axis_fifo_adapter/test_axis_fifo_adapter.py | 0 .../lib/axis/tb/axis_frame_length_adjust/Makefile | 0 .../test_axis_frame_length_adjust.py | 0 .../lib/axis/tb/axis_frame_length_adjust_fifo/Makefile | 0 .../test_axis_frame_length_adjust_fifo.py | 0 .../alexforencich/lib/axis/tb/axis_mux/Makefile | 0 .../lib/axis/tb/axis_mux/test_axis_mux.py | 0 .../lib/axis/tb/axis_pipeline_fifo/Makefile | 0 .../tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py | 0 .../lib/axis/tb/axis_pipeline_register/Makefile | 0 .../test_axis_pipeline_register.py | 0 .../alexforencich/lib/axis/tb/axis_ram_switch/Makefile | 0 .../axis/tb/axis_ram_switch/test_axis_ram_switch.py | 0 .../alexforencich/lib/axis/tb/axis_rate_limit/Makefile | 0 .../axis/tb/axis_rate_limit/test_axis_rate_limit.py | 0 .../alexforencich/lib/axis/tb/axis_register/Makefile | 0 .../lib/axis/tb/axis_register/test_axis_register.py | 0 .../alexforencich/lib/axis/tb/axis_srl_fifo/Makefile | 0 .../lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py | 0 .../lib/axis/tb/axis_srl_register/Makefile | 0 .../tb/axis_srl_register/test_axis_srl_register.py | 0 .../alexforencich/lib/axis/tb/axis_switch/Makefile | 0 .../lib/axis/tb/axis_switch/test_axis_switch.py | 0 .../verilog/alexforencich/lib/axis/tb/ll_ep.py | 0 .../verilog/alexforencich/lib/axis/tb/test_arbiter.py | 0 .../verilog/alexforencich/lib/axis/tb/test_arbiter.v | 0 .../alexforencich/lib/axis/tb/test_arbiter_rr.py | 0 .../alexforencich/lib/axis/tb/test_arbiter_rr.v | 0 .../lib/axis/tb/test_axis_adapter_64_8.py | 0 .../alexforencich/lib/axis/tb/test_axis_adapter_64_8.v | 0 .../lib/axis/tb/test_axis_adapter_8_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_adapter_8_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_arb_mux_4.py | 0 .../alexforencich/lib/axis/tb/test_axis_arb_mux_4.v | 0 .../lib/axis/tb/test_axis_arb_mux_4_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_async_fifo.py | 0 .../alexforencich/lib/axis/tb/test_axis_async_fifo.v | 0 .../lib/axis/tb/test_axis_async_fifo_64.py | 0 .../lib/axis/tb/test_axis_async_fifo_64.v | 0 .../lib/axis/tb/test_axis_async_fifo_adapter_64_8.py | 0 .../lib/axis/tb/test_axis_async_fifo_adapter_64_8.v | 0 .../lib/axis/tb/test_axis_async_fifo_adapter_8_64.py | 0 .../lib/axis/tb/test_axis_async_fifo_adapter_8_64.v | 0 .../lib/axis/tb/test_axis_async_frame_fifo.py | 0 .../lib/axis/tb/test_axis_async_frame_fifo.v | 0 .../lib/axis/tb/test_axis_async_frame_fifo_64.py | 0 .../lib/axis/tb/test_axis_async_frame_fifo_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_broadcast_4.py | 0 .../alexforencich/lib/axis/tb/test_axis_broadcast_4.v | 0 .../alexforencich/lib/axis/tb/test_axis_cobs_decode.py | 0 .../alexforencich/lib/axis/tb/test_axis_cobs_decode.v | 0 .../alexforencich/lib/axis/tb/test_axis_cobs_encode.py | 0 .../alexforencich/lib/axis/tb/test_axis_cobs_encode.v | 0 .../lib/axis/tb/test_axis_cobs_encode_zero_frame.py | 0 .../lib/axis/tb/test_axis_cobs_encode_zero_frame.v | 0 .../lib/axis/tb/test_axis_crosspoint_4x4.py | 0 .../lib/axis/tb/test_axis_crosspoint_4x4.v | 0 .../lib/axis/tb/test_axis_crosspoint_4x4_64.py | 0 .../lib/axis/tb/test_axis_crosspoint_4x4_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_demux_4.py | 0 .../alexforencich/lib/axis/tb/test_axis_demux_4.v | 0 .../alexforencich/lib/axis/tb/test_axis_demux_4_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_demux_4_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_fifo.py | 0 .../verilog/alexforencich/lib/axis/tb/test_axis_fifo.v | 0 .../alexforencich/lib/axis/tb/test_axis_fifo_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_fifo_64.v | 0 .../lib/axis/tb/test_axis_fifo_adapter_64_8.py | 0 .../lib/axis/tb/test_axis_fifo_adapter_64_8.v | 0 .../lib/axis/tb/test_axis_fifo_adapter_8_64.py | 0 .../lib/axis/tb/test_axis_fifo_adapter_8_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_frame_fifo.py | 0 .../alexforencich/lib/axis/tb/test_axis_frame_fifo.v | 0 .../lib/axis/tb/test_axis_frame_fifo_64.py | 0 .../lib/axis/tb/test_axis_frame_fifo_64.v | 0 .../lib/axis/tb/test_axis_frame_join_4.py | 0 .../alexforencich/lib/axis/tb/test_axis_frame_join_4.v | 0 .../lib/axis/tb/test_axis_frame_len_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_frame_len_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_frame_len_8.py | 0 .../alexforencich/lib/axis/tb/test_axis_frame_len_8.v | 0 .../lib/axis/tb/test_axis_frame_length_adjust_64.py | 0 .../lib/axis/tb/test_axis_frame_length_adjust_64.v | 0 .../lib/axis/tb/test_axis_frame_length_adjust_8.py | 0 .../lib/axis/tb/test_axis_frame_length_adjust_8.v | 0 .../lib/axis/tb/test_axis_frame_length_adjust_fifo.py | 0 .../lib/axis/tb/test_axis_frame_length_adjust_fifo.v | 0 .../axis/tb/test_axis_frame_length_adjust_fifo_64.py | 0 .../axis/tb/test_axis_frame_length_adjust_fifo_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_ll_bridge.py | 0 .../alexforencich/lib/axis/tb/test_axis_ll_bridge.v | 0 .../alexforencich/lib/axis/tb/test_axis_mux_4.py | 0 .../alexforencich/lib/axis/tb/test_axis_mux_4.v | 0 .../alexforencich/lib/axis/tb/test_axis_mux_4_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_mux_4_64.v | 0 .../lib/axis/tb/test_axis_ram_switch_1x4_256_64.py | 0 .../lib/axis/tb/test_axis_ram_switch_1x4_256_64.v | 0 .../lib/axis/tb/test_axis_ram_switch_4x1_64_256.py | 0 .../lib/axis/tb/test_axis_ram_switch_4x1_64_256.v | 0 .../lib/axis/tb/test_axis_ram_switch_4x4_64_64.py | 0 .../lib/axis/tb/test_axis_ram_switch_4x4_64_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_rate_limit.py | 0 .../alexforencich/lib/axis/tb/test_axis_rate_limit.v | 0 .../lib/axis/tb/test_axis_rate_limit_64.py | 0 .../lib/axis/tb/test_axis_rate_limit_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_register.py | 0 .../alexforencich/lib/axis/tb/test_axis_register.v | 0 .../alexforencich/lib/axis/tb/test_axis_register_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_register_64.v | 0 .../alexforencich/lib/axis/tb/test_axis_srl_fifo.py | 0 .../alexforencich/lib/axis/tb/test_axis_srl_fifo.v | 0 .../alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v | 0 .../lib/axis/tb/test_axis_srl_register.py | 0 .../alexforencich/lib/axis/tb/test_axis_srl_register.v | 0 .../lib/axis/tb/test_axis_srl_register_64.py | 0 .../lib/axis/tb/test_axis_srl_register_64.v | 0 .../lib/axis/tb/test_axis_stat_counter.py | 0 .../alexforencich/lib/axis/tb/test_axis_stat_counter.v | 0 .../alexforencich/lib/axis/tb/test_axis_switch_4x4.py | 0 .../alexforencich/lib/axis/tb/test_axis_switch_4x4.v | 0 .../lib/axis/tb/test_axis_switch_4x4_64.py | 0 .../lib/axis/tb/test_axis_switch_4x4_64.v | 0 .../verilog/alexforencich/lib/axis/tb/test_axis_tap.py | 0 .../verilog/alexforencich/lib/axis/tb/test_axis_tap.v | 0 .../alexforencich/lib/axis/tb/test_axis_tap_64.py | 0 .../alexforencich/lib/axis/tb/test_axis_tap_64.v | 0 .../alexforencich/lib/axis/tb/test_ll_axis_bridge.py | 0 .../alexforencich/lib/axis/tb/test_ll_axis_bridge.v | 0 .../alexforencich/lib/axis/tb/test_priority_encoder.py | 0 .../alexforencich/lib/axis/tb/test_priority_encoder.v | 0 .../resources/verilog/alexforencich/lib/axis/tox.ini | 0 .../resources/verilog/alexforencich/lib/update-axis.sh | 0 .../resources/verilog/alexforencich/rtl/arp.v | 0 .../resources/verilog/alexforencich/rtl/arp_cache.v | 0 .../resources/verilog/alexforencich/rtl/arp_eth_rx.v | 0 .../resources/verilog/alexforencich/rtl/arp_eth_tx.v | 0 .../verilog/alexforencich/rtl/axis_baser_rx_64.v | 0 .../verilog/alexforencich/rtl/axis_baser_tx_64.v | 0 .../resources/verilog/alexforencich/rtl/axis_eth_fcs.v | 0 .../verilog/alexforencich/rtl/axis_eth_fcs_check.v | 0 .../verilog/alexforencich/rtl/axis_eth_fcs_check_64.v | 0 .../verilog/alexforencich/rtl/axis_eth_fcs_insert.v | 0 .../verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v | 0 .../resources/verilog/alexforencich/rtl/axis_gmii_rx.v | 0 .../resources/verilog/alexforencich/rtl/axis_gmii_tx.v | 0 .../verilog/alexforencich/rtl/axis_xgmii_rx_32.v | 0 .../verilog/alexforencich/rtl/axis_xgmii_rx_64.v | 0 .../verilog/alexforencich/rtl/axis_xgmii_tx_32.v | 0 .../verilog/alexforencich/rtl/axis_xgmii_tx_64.v | 0 .../resources/verilog/alexforencich/rtl/eth_arb_mux.v | 0 .../resources/verilog/alexforencich/rtl/eth_axis_rx.v | 0 .../resources/verilog/alexforencich/rtl/eth_axis_tx.v | 0 .../resources/verilog/alexforencich/rtl/eth_demux.v | 0 .../resources/verilog/alexforencich/rtl/eth_mac_10g.v | 0 .../verilog/alexforencich/rtl/eth_mac_10g_fifo.v | 0 .../resources/verilog/alexforencich/rtl/eth_mac_1g.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g_gmii.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g_rgmii.v | 0 .../verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v | 0 .../resources/verilog/alexforencich/rtl/eth_mac_mii.v | 0 .../verilog/alexforencich/rtl/eth_mac_mii_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_phy_10g.v | 0 .../verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v | 0 .../verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v | 0 .../verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v | 0 .../resources/verilog/alexforencich/rtl/eth_mux.v | 0 .../resources/verilog/alexforencich/rtl/eth_phy_10g.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g_rx.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v | 0 .../alexforencich/rtl/eth_phy_10g_rx_frame_sync.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g_rx_if.v | 0 .../alexforencich/rtl/eth_phy_10g_rx_watchdog.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g_tx.v | 0 .../verilog/alexforencich/rtl/eth_phy_10g_tx_if.v | 0 .../resources/verilog/alexforencich/rtl/gmii_phy_if.v | 0 .../resources/verilog/alexforencich/rtl/iddr.v | 0 .../resources/verilog/alexforencich/rtl/ip.v | 0 .../resources/verilog/alexforencich/rtl/ip_64.v | 0 .../resources/verilog/alexforencich/rtl/ip_arb_mux.v | 0 .../resources/verilog/alexforencich/rtl/ip_complete.v | 0 .../verilog/alexforencich/rtl/ip_complete_64.v | 0 .../resources/verilog/alexforencich/rtl/ip_demux.v | 0 .../resources/verilog/alexforencich/rtl/ip_eth_rx.v | 0 .../resources/verilog/alexforencich/rtl/ip_eth_rx_64.v | 0 .../resources/verilog/alexforencich/rtl/ip_eth_tx.v | 0 .../resources/verilog/alexforencich/rtl/ip_eth_tx_64.v | 0 .../resources/verilog/alexforencich/rtl/ip_mux.v | 0 .../resources/verilog/alexforencich/rtl/lfsr.v | 0 .../resources/verilog/alexforencich/rtl/mac_ctrl_rx.v | 0 .../resources/verilog/alexforencich/rtl/mac_ctrl_tx.v | 0 .../verilog/alexforencich/rtl/mac_pause_ctrl_rx.v | 0 .../verilog/alexforencich/rtl/mac_pause_ctrl_tx.v | 0 .../resources/verilog/alexforencich/rtl/mii_phy_if.v | 0 .../resources/verilog/alexforencich/rtl/oddr.v | 0 .../resources/verilog/alexforencich/rtl/ptp_clock.v | 0 .../verilog/alexforencich/rtl/ptp_clock_cdc.v | 0 .../resources/verilog/alexforencich/rtl/ptp_perout.v | 0 .../verilog/alexforencich/rtl/ptp_tag_insert.v | 0 .../resources/verilog/alexforencich/rtl/ptp_td_leaf.v | 0 .../resources/verilog/alexforencich/rtl/ptp_td_phc.v | 0 .../verilog/alexforencich/rtl/ptp_td_rel2tod.v | 0 .../verilog/alexforencich/rtl/ptp_ts_extract.v | 0 .../resources/verilog/alexforencich/rtl/rgmii_phy_if.v | 0 .../resources/verilog/alexforencich/rtl/ssio_ddr_in.v | 0 .../verilog/alexforencich/rtl/ssio_ddr_in_diff.v | 0 .../resources/verilog/alexforencich/rtl/ssio_ddr_out.v | 0 .../verilog/alexforencich/rtl/ssio_ddr_out_diff.v | 0 .../resources/verilog/alexforencich/rtl/ssio_sdr_in.v | 0 .../verilog/alexforencich/rtl/ssio_sdr_in_diff.v | 0 .../resources/verilog/alexforencich/rtl/ssio_sdr_out.v | 0 .../verilog/alexforencich/rtl/ssio_sdr_out_diff.v | 0 .../resources/verilog/alexforencich/rtl/udp.v | 0 .../resources/verilog/alexforencich/rtl/udp_64.v | 0 .../resources/verilog/alexforencich/rtl/udp_arb_mux.v | 0 .../verilog/alexforencich/rtl/udp_checksum_gen.v | 0 .../verilog/alexforencich/rtl/udp_checksum_gen_64.v | 0 .../resources/verilog/alexforencich/rtl/udp_complete.v | 0 .../verilog/alexforencich/rtl/udp_complete_64.v | 0 .../resources/verilog/alexforencich/rtl/udp_demux.v | 0 .../resources/verilog/alexforencich/rtl/udp_ip_rx.v | 0 .../resources/verilog/alexforencich/rtl/udp_ip_rx_64.v | 0 .../resources/verilog/alexforencich/rtl/udp_ip_tx.v | 0 .../resources/verilog/alexforencich/rtl/udp_ip_tx_64.v | 0 .../resources/verilog/alexforencich/rtl/udp_mux.v | 0 .../verilog/alexforencich/rtl/xgmii_baser_dec_64.v | 0 .../verilog/alexforencich/rtl/xgmii_baser_enc_64.v | 0 .../verilog/alexforencich/rtl/xgmii_deinterleave.v | 0 .../verilog/alexforencich/rtl/xgmii_interleave.v | 0 .../resources/verilog/alexforencich/udp_core.v | 0 .../resources/verilog/sync_reset.v | 0 .../src/Arty100TTop.scala | 0 .../src/MinimalArty100T.scala | 0 .../src/ZedboardTop.scala | 0 .../src/basic/ClockDivider.scala | 0 .../src/basic/SyncReset.scala | 0 .../src/xilinx/Axi4BlockMemory.scala | 0 .../src/xilinx/Axi4Crossbar.scala | 0 .../src/xilinx/Axi4DataWidthConverter.scala | 0 .../src/xilinx/Axi4LiteCrossbar.scala | 0 .../src/xilinx/Axi4LiteGpio.scala | 0 .../src/xilinx/Axi4LiteStreamDataFifo.scala | 0 .../src/xilinx/Axi4LiteTimer.scala | 0 .../src/xilinx/Axi4LiteUartLite.scala | 0 .../src/xilinx/Axi4ProtocolConverter.scala | 0 .../src/xilinx/Axi4QuadSpiFlash.scala | 0 .../src/xilinx/Axi4SpiFlash.scala | 0 .../src/xilinx/Axi4WiderMemory.scala | 0 .../src/xilinx/ClockingWizard.scala | 0 .../src/xilinx/FloatingPoint.scala | 0 .../src/xilinx/IOBuffer.scala | 0 .../src/xilinx/bundle/Axi4BlackboxBundles.scala | 0 .../src/xilinx/bundle/Axi4Bundles.scala | 0 .../src/xilinx/bundle/Axi4Params.scala | 0 .../test/resources/verilog/components/RamTestbench.sv | 0 .../resources/verilog/components/plusarg_file_mem.sv | 0 .../verilog/examples/Axi4MemoryForTestTestbench.sv | 0 .../verilog/examples/Axi4SpiFlashTestBench.sv | 0 .../test/resources/verilog/examples/AxiInterface.vh | 0 .../test/resources/verilog/examples/UartTestbench.sv | 0 .../test/resources/vhdl/components/SimSpiFlash.vhd | 0 384 files changed, 5 insertions(+), 5 deletions(-) rename {module-chipyard-wrapper => package-chipyard-wrapper}/src/DigitalTop.scala (100%) rename {module-chipyard-wrapper => package-chipyard-wrapper}/src/MotorArty100T.scala (100%) rename {module-chipyard-wrapper => package-chipyard-wrapper}/src/TinyRocketArty100T.scala (100%) rename {module-chipyard-wrapper => package-chipyard-wrapper}/src/UdpTinyRocketArty100T.scala (100%) rename {module-delta-soc => package-delta-soc}/resources/verilog/AsyncRam.v (100%) rename {module-delta-soc => package-delta-soc}/resources/verilog/Ram.v (100%) rename {module-delta-soc => package-delta-soc}/resources/verilog/SimSpiFlashModel.sv (100%) rename {module-delta-soc => package-delta-soc}/resources/verilog/SimUart.sv (100%) rename {module-delta-soc => package-delta-soc}/resources/verilog/SpiFlashMemCtrl.sv (100%) rename {module-delta-soc => package-delta-soc}/src/TestTiles.scala (100%) rename {module-delta-soc => package-delta-soc}/src/Tile.scala (100%) rename {module-delta-soc => package-delta-soc}/src/configs/MemorySubsystem.scala (100%) rename {module-delta-soc => package-delta-soc}/src/configs/MlpPolicyRunner.scala (100%) rename {module-delta-soc => package-delta-soc}/src/constants/Constants.scala (100%) rename {module-delta-soc => package-delta-soc}/src/constants/Instructions.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/ALU.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/CSR.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/Core.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/InstructionDecode.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/InstructionFetch.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/LoadStore.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/SimdFloatingPoint.scala (100%) rename {module-delta-soc => package-delta-soc}/src/core/SimdLoadStore.scala (100%) rename {module-delta-soc => package-delta-soc}/src/interconnect/Axi4WidthDownsizer.scala (100%) rename {module-delta-soc => package-delta-soc}/src/interconnect/Axi4WidthUpsizer.scala (100%) rename {module-delta-soc => package-delta-soc}/src/memory/AsyncRam.scala (100%) rename {module-delta-soc => package-delta-soc}/src/memory/Axi4LiteMemory.scala (100%) rename {module-delta-soc => package-delta-soc}/src/memory/Axi4Memory.scala (100%) rename {module-delta-soc => package-delta-soc}/src/memory/Axi4MemoryWithLatency.scala (100%) rename {module-delta-soc => package-delta-soc}/src/memory/Ram.scala (100%) rename {module-delta-soc => package-delta-soc}/test/EECS151TileISATestbench.sv (100%) rename {module-delta-soc => package-delta-soc}/test/EECS151TileTestbench.sv (100%) rename {module-delta-soc => package-delta-soc}/test/EECS252TileTestbench.sv (100%) rename {module-delta-soc => package-delta-soc}/test/InstructionFetchTestbench.sv (100%) rename {module-delta-soc => package-delta-soc}/test/MemorySubsystemTestbench.sv (100%) rename {module-delta-soc => package-delta-soc}/test/MlpPolicyRunnerTestbench.sv (100%) rename {module-tacit => package-tacit}/src/MadaTimer.scala (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/Arty-A7-100-Master.xdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/Arty_C_mig.ucf (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/Zedboard-Master.xdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/axis_async_fifo.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/eth_mac_fifo.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/mig.prj (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/mii_phy_if.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/constraints/sync_reset.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/Arty100TShell.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/.gitignore (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/.test_durations (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/AUTHORS (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/COPYING (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/README (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/README.md (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/axis/tox.ini (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/lib/update-axis.sh (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/arp.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/arp_cache.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/arp_eth_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/arp_eth_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_gmii_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_gmii_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_arb_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_axis_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_axis_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_demux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_10g.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_mii.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/gmii_phy_if.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/iddr.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_arb_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_complete.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_complete_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_demux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ip_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/lfsr.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/mii_phy_if.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/oddr.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_clock.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_perout.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_tag_insert.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_leaf.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_phc.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ptp_ts_extract.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/rgmii_phy_if.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_in.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_out.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_in.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_out.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_arb_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_checksum_gen.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_complete.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_complete_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_demux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_rx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_tx.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/udp_mux.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/rtl/xgmii_interleave.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/alexforencich/udp_core.v (100%) rename {module-vivado-ips => package-vivado-ips}/resources/verilog/sync_reset.v (100%) rename {module-vivado-ips => package-vivado-ips}/src/Arty100TTop.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/MinimalArty100T.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/ZedboardTop.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/basic/ClockDivider.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/basic/SyncReset.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4BlockMemory.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4Crossbar.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4DataWidthConverter.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4LiteCrossbar.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4LiteGpio.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4LiteStreamDataFifo.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4LiteTimer.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4LiteUartLite.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4ProtocolConverter.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4QuadSpiFlash.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4SpiFlash.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/Axi4WiderMemory.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/ClockingWizard.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/FloatingPoint.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/IOBuffer.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/bundle/Axi4BlackboxBundles.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/bundle/Axi4Bundles.scala (100%) rename {module-vivado-ips => package-vivado-ips}/src/xilinx/bundle/Axi4Params.scala (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/components/RamTestbench.sv (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/components/plusarg_file_mem.sv (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/examples/AxiInterface.vh (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/verilog/examples/UartTestbench.sv (100%) rename {module-vivado-ips => package-vivado-ips}/test/resources/vhdl/components/SimSpiFlash.vhd (100%) diff --git a/build.mill.scala b/build.mill.scala index 4e04fa8..83f8a94 100644 --- a/build.mill.scala +++ b/build.mill.scala @@ -56,15 +56,15 @@ trait ChiselModule extends ScalaModule with ScalafmtModule { m => object builder extends ChiselModule -object `module-vivado-ips` extends ChiselModule { m => +object `package-vivado-ips` extends ChiselModule { m => override def moduleDeps = Seq(builder) } -object `module-delta-soc` extends ChiselModule { m => - override def moduleDeps = Seq(builder, `module-vivado-ips`) +object `package-delta-soc` extends ChiselModule { m => + override def moduleDeps = Seq(builder, `package-vivado-ips`) } -object `module-chipyard-wrapper` extends ChiselModule { m => - override def moduleDeps = Seq(builder, `module-vivado-ips`) +object `package-chipyard-wrapper` extends ChiselModule { m => + override def moduleDeps = Seq(builder, `package-vivado-ips`) } diff --git a/module-chipyard-wrapper/src/DigitalTop.scala b/package-chipyard-wrapper/src/DigitalTop.scala similarity index 100% rename from module-chipyard-wrapper/src/DigitalTop.scala rename to package-chipyard-wrapper/src/DigitalTop.scala diff --git a/module-chipyard-wrapper/src/MotorArty100T.scala b/package-chipyard-wrapper/src/MotorArty100T.scala similarity index 100% rename from module-chipyard-wrapper/src/MotorArty100T.scala rename to package-chipyard-wrapper/src/MotorArty100T.scala diff --git a/module-chipyard-wrapper/src/TinyRocketArty100T.scala b/package-chipyard-wrapper/src/TinyRocketArty100T.scala similarity index 100% rename from module-chipyard-wrapper/src/TinyRocketArty100T.scala rename to package-chipyard-wrapper/src/TinyRocketArty100T.scala diff --git a/module-chipyard-wrapper/src/UdpTinyRocketArty100T.scala b/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala similarity index 100% rename from module-chipyard-wrapper/src/UdpTinyRocketArty100T.scala rename to package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala diff --git a/module-delta-soc/resources/verilog/AsyncRam.v b/package-delta-soc/resources/verilog/AsyncRam.v similarity index 100% rename from module-delta-soc/resources/verilog/AsyncRam.v rename to package-delta-soc/resources/verilog/AsyncRam.v diff --git a/module-delta-soc/resources/verilog/Ram.v b/package-delta-soc/resources/verilog/Ram.v similarity index 100% rename from module-delta-soc/resources/verilog/Ram.v rename to package-delta-soc/resources/verilog/Ram.v diff --git a/module-delta-soc/resources/verilog/SimSpiFlashModel.sv b/package-delta-soc/resources/verilog/SimSpiFlashModel.sv similarity index 100% rename from module-delta-soc/resources/verilog/SimSpiFlashModel.sv rename to package-delta-soc/resources/verilog/SimSpiFlashModel.sv diff --git a/module-delta-soc/resources/verilog/SimUart.sv b/package-delta-soc/resources/verilog/SimUart.sv similarity index 100% rename from module-delta-soc/resources/verilog/SimUart.sv rename to package-delta-soc/resources/verilog/SimUart.sv diff --git a/module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv b/package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv similarity index 100% rename from module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv rename to package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv diff --git a/module-delta-soc/src/TestTiles.scala b/package-delta-soc/src/TestTiles.scala similarity index 100% rename from module-delta-soc/src/TestTiles.scala rename to package-delta-soc/src/TestTiles.scala diff --git a/module-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala similarity index 100% rename from module-delta-soc/src/Tile.scala rename to package-delta-soc/src/Tile.scala diff --git a/module-delta-soc/src/configs/MemorySubsystem.scala b/package-delta-soc/src/configs/MemorySubsystem.scala similarity index 100% rename from module-delta-soc/src/configs/MemorySubsystem.scala rename to package-delta-soc/src/configs/MemorySubsystem.scala diff --git a/module-delta-soc/src/configs/MlpPolicyRunner.scala b/package-delta-soc/src/configs/MlpPolicyRunner.scala similarity index 100% rename from module-delta-soc/src/configs/MlpPolicyRunner.scala rename to package-delta-soc/src/configs/MlpPolicyRunner.scala diff --git a/module-delta-soc/src/constants/Constants.scala b/package-delta-soc/src/constants/Constants.scala similarity index 100% rename from module-delta-soc/src/constants/Constants.scala rename to package-delta-soc/src/constants/Constants.scala diff --git a/module-delta-soc/src/constants/Instructions.scala b/package-delta-soc/src/constants/Instructions.scala similarity index 100% rename from module-delta-soc/src/constants/Instructions.scala rename to package-delta-soc/src/constants/Instructions.scala diff --git a/module-delta-soc/src/core/ALU.scala b/package-delta-soc/src/core/ALU.scala similarity index 100% rename from module-delta-soc/src/core/ALU.scala rename to package-delta-soc/src/core/ALU.scala diff --git a/module-delta-soc/src/core/CSR.scala b/package-delta-soc/src/core/CSR.scala similarity index 100% rename from module-delta-soc/src/core/CSR.scala rename to package-delta-soc/src/core/CSR.scala diff --git a/module-delta-soc/src/core/Core.scala b/package-delta-soc/src/core/Core.scala similarity index 100% rename from module-delta-soc/src/core/Core.scala rename to package-delta-soc/src/core/Core.scala diff --git a/module-delta-soc/src/core/InstructionDecode.scala b/package-delta-soc/src/core/InstructionDecode.scala similarity index 100% rename from module-delta-soc/src/core/InstructionDecode.scala rename to package-delta-soc/src/core/InstructionDecode.scala diff --git a/module-delta-soc/src/core/InstructionFetch.scala b/package-delta-soc/src/core/InstructionFetch.scala similarity index 100% rename from module-delta-soc/src/core/InstructionFetch.scala rename to package-delta-soc/src/core/InstructionFetch.scala diff --git a/module-delta-soc/src/core/LoadStore.scala b/package-delta-soc/src/core/LoadStore.scala similarity index 100% rename from module-delta-soc/src/core/LoadStore.scala rename to package-delta-soc/src/core/LoadStore.scala diff --git a/module-delta-soc/src/core/SimdFloatingPoint.scala b/package-delta-soc/src/core/SimdFloatingPoint.scala similarity index 100% rename from module-delta-soc/src/core/SimdFloatingPoint.scala rename to package-delta-soc/src/core/SimdFloatingPoint.scala diff --git a/module-delta-soc/src/core/SimdLoadStore.scala b/package-delta-soc/src/core/SimdLoadStore.scala similarity index 100% rename from module-delta-soc/src/core/SimdLoadStore.scala rename to package-delta-soc/src/core/SimdLoadStore.scala diff --git a/module-delta-soc/src/interconnect/Axi4WidthDownsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala similarity index 100% rename from module-delta-soc/src/interconnect/Axi4WidthDownsizer.scala rename to package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala diff --git a/module-delta-soc/src/interconnect/Axi4WidthUpsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala similarity index 100% rename from module-delta-soc/src/interconnect/Axi4WidthUpsizer.scala rename to package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala diff --git a/module-delta-soc/src/memory/AsyncRam.scala b/package-delta-soc/src/memory/AsyncRam.scala similarity index 100% rename from module-delta-soc/src/memory/AsyncRam.scala rename to package-delta-soc/src/memory/AsyncRam.scala diff --git a/module-delta-soc/src/memory/Axi4LiteMemory.scala b/package-delta-soc/src/memory/Axi4LiteMemory.scala similarity index 100% rename from module-delta-soc/src/memory/Axi4LiteMemory.scala rename to package-delta-soc/src/memory/Axi4LiteMemory.scala diff --git a/module-delta-soc/src/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala similarity index 100% rename from module-delta-soc/src/memory/Axi4Memory.scala rename to package-delta-soc/src/memory/Axi4Memory.scala diff --git a/module-delta-soc/src/memory/Axi4MemoryWithLatency.scala b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala similarity index 100% rename from module-delta-soc/src/memory/Axi4MemoryWithLatency.scala rename to package-delta-soc/src/memory/Axi4MemoryWithLatency.scala diff --git a/module-delta-soc/src/memory/Ram.scala b/package-delta-soc/src/memory/Ram.scala similarity index 100% rename from module-delta-soc/src/memory/Ram.scala rename to package-delta-soc/src/memory/Ram.scala diff --git a/module-delta-soc/test/EECS151TileISATestbench.sv b/package-delta-soc/test/EECS151TileISATestbench.sv similarity index 100% rename from module-delta-soc/test/EECS151TileISATestbench.sv rename to package-delta-soc/test/EECS151TileISATestbench.sv diff --git a/module-delta-soc/test/EECS151TileTestbench.sv b/package-delta-soc/test/EECS151TileTestbench.sv similarity index 100% rename from module-delta-soc/test/EECS151TileTestbench.sv rename to package-delta-soc/test/EECS151TileTestbench.sv diff --git a/module-delta-soc/test/EECS252TileTestbench.sv b/package-delta-soc/test/EECS252TileTestbench.sv similarity index 100% rename from module-delta-soc/test/EECS252TileTestbench.sv rename to package-delta-soc/test/EECS252TileTestbench.sv diff --git a/module-delta-soc/test/InstructionFetchTestbench.sv b/package-delta-soc/test/InstructionFetchTestbench.sv similarity index 100% rename from module-delta-soc/test/InstructionFetchTestbench.sv rename to package-delta-soc/test/InstructionFetchTestbench.sv diff --git a/module-delta-soc/test/MemorySubsystemTestbench.sv b/package-delta-soc/test/MemorySubsystemTestbench.sv similarity index 100% rename from module-delta-soc/test/MemorySubsystemTestbench.sv rename to package-delta-soc/test/MemorySubsystemTestbench.sv diff --git a/module-delta-soc/test/MlpPolicyRunnerTestbench.sv b/package-delta-soc/test/MlpPolicyRunnerTestbench.sv similarity index 100% rename from module-delta-soc/test/MlpPolicyRunnerTestbench.sv rename to package-delta-soc/test/MlpPolicyRunnerTestbench.sv diff --git a/module-tacit/src/MadaTimer.scala b/package-tacit/src/MadaTimer.scala similarity index 100% rename from module-tacit/src/MadaTimer.scala rename to package-tacit/src/MadaTimer.scala diff --git a/module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc b/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc similarity index 100% rename from module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc rename to package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc diff --git a/module-vivado-ips/resources/constraints/Arty_C_mig.ucf b/package-vivado-ips/resources/constraints/Arty_C_mig.ucf similarity index 100% rename from module-vivado-ips/resources/constraints/Arty_C_mig.ucf rename to package-vivado-ips/resources/constraints/Arty_C_mig.ucf diff --git a/module-vivado-ips/resources/constraints/Zedboard-Master.xdc b/package-vivado-ips/resources/constraints/Zedboard-Master.xdc similarity index 100% rename from module-vivado-ips/resources/constraints/Zedboard-Master.xdc rename to package-vivado-ips/resources/constraints/Zedboard-Master.xdc diff --git a/module-vivado-ips/resources/constraints/axis_async_fifo.tcl b/package-vivado-ips/resources/constraints/axis_async_fifo.tcl similarity index 100% rename from module-vivado-ips/resources/constraints/axis_async_fifo.tcl rename to package-vivado-ips/resources/constraints/axis_async_fifo.tcl diff --git a/module-vivado-ips/resources/constraints/eth_mac_fifo.tcl b/package-vivado-ips/resources/constraints/eth_mac_fifo.tcl similarity index 100% rename from module-vivado-ips/resources/constraints/eth_mac_fifo.tcl rename to package-vivado-ips/resources/constraints/eth_mac_fifo.tcl diff --git a/module-vivado-ips/resources/constraints/mig.prj b/package-vivado-ips/resources/constraints/mig.prj similarity index 100% rename from module-vivado-ips/resources/constraints/mig.prj rename to package-vivado-ips/resources/constraints/mig.prj diff --git a/module-vivado-ips/resources/constraints/mii_phy_if.tcl b/package-vivado-ips/resources/constraints/mii_phy_if.tcl similarity index 100% rename from module-vivado-ips/resources/constraints/mii_phy_if.tcl rename to package-vivado-ips/resources/constraints/mii_phy_if.tcl diff --git a/module-vivado-ips/resources/constraints/sync_reset.tcl b/package-vivado-ips/resources/constraints/sync_reset.tcl similarity index 100% rename from module-vivado-ips/resources/constraints/sync_reset.tcl rename to package-vivado-ips/resources/constraints/sync_reset.tcl diff --git a/module-vivado-ips/resources/verilog/Arty100TShell.v b/package-vivado-ips/resources/verilog/Arty100TShell.v similarity index 100% rename from module-vivado-ips/resources/verilog/Arty100TShell.v rename to package-vivado-ips/resources/verilog/Arty100TShell.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/README b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/README similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/README rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/README diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_mux/test_axis_mux.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_register/test_axis_register.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_srl_register/test_axis_srl_register.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/Makefile diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_switch/test_axis_switch.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/ll_ep.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_arbiter_rr.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_64_8.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_adapter_8_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_arb_mux_4_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_async_frame_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_broadcast_4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_decode.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_cobs_encode_zero_frame.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_crosspoint_4x4_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_demux_4_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_64_8.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_fifo_adapter_8_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_join_4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_len_8.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_8.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ll_bridge.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_mux_4_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_rate_limit_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_register_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_fifo_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_srl_register_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_stat_counter.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_switch_4x4_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_axis_tap_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_ll_axis_bridge.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.py diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/test_priority_encoder.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tox.ini diff --git a/module-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh b/package-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh rename to package-vivado-ips/resources/verilog/alexforencich/lib/update-axis.sh diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/arp.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/arp.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/arp.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/arp.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/arp_cache.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/arp_eth_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_rx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_baser_tx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_check_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_eth_fcs_insert_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_gmii_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_32.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_rx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_32.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/axis_xgmii_tx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_arb_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_axis_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_demux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_10g_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v diff --git a/module-vivado-ips/resources/verilog/alexforencich/udp_core.v b/package-vivado-ips/resources/verilog/alexforencich/udp_core.v similarity index 100% rename from module-vivado-ips/resources/verilog/alexforencich/udp_core.v rename to package-vivado-ips/resources/verilog/alexforencich/udp_core.v diff --git a/module-vivado-ips/resources/verilog/sync_reset.v b/package-vivado-ips/resources/verilog/sync_reset.v similarity index 100% rename from module-vivado-ips/resources/verilog/sync_reset.v rename to package-vivado-ips/resources/verilog/sync_reset.v diff --git a/module-vivado-ips/src/Arty100TTop.scala b/package-vivado-ips/src/Arty100TTop.scala similarity index 100% rename from module-vivado-ips/src/Arty100TTop.scala rename to package-vivado-ips/src/Arty100TTop.scala diff --git a/module-vivado-ips/src/MinimalArty100T.scala b/package-vivado-ips/src/MinimalArty100T.scala similarity index 100% rename from module-vivado-ips/src/MinimalArty100T.scala rename to package-vivado-ips/src/MinimalArty100T.scala diff --git a/module-vivado-ips/src/ZedboardTop.scala b/package-vivado-ips/src/ZedboardTop.scala similarity index 100% rename from module-vivado-ips/src/ZedboardTop.scala rename to package-vivado-ips/src/ZedboardTop.scala diff --git a/module-vivado-ips/src/basic/ClockDivider.scala b/package-vivado-ips/src/basic/ClockDivider.scala similarity index 100% rename from module-vivado-ips/src/basic/ClockDivider.scala rename to package-vivado-ips/src/basic/ClockDivider.scala diff --git a/module-vivado-ips/src/basic/SyncReset.scala b/package-vivado-ips/src/basic/SyncReset.scala similarity index 100% rename from module-vivado-ips/src/basic/SyncReset.scala rename to package-vivado-ips/src/basic/SyncReset.scala diff --git a/module-vivado-ips/src/xilinx/Axi4BlockMemory.scala b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4BlockMemory.scala rename to package-vivado-ips/src/xilinx/Axi4BlockMemory.scala diff --git a/module-vivado-ips/src/xilinx/Axi4Crossbar.scala b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4Crossbar.scala rename to package-vivado-ips/src/xilinx/Axi4Crossbar.scala diff --git a/module-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala rename to package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala diff --git a/module-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala rename to package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala diff --git a/module-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4LiteGpio.scala rename to package-vivado-ips/src/xilinx/Axi4LiteGpio.scala diff --git a/module-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala rename to package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala diff --git a/module-vivado-ips/src/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4LiteTimer.scala rename to package-vivado-ips/src/xilinx/Axi4LiteTimer.scala diff --git a/module-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4LiteUartLite.scala rename to package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala diff --git a/module-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala rename to package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala diff --git a/module-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala rename to package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala diff --git a/module-vivado-ips/src/xilinx/Axi4SpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4SpiFlash.scala rename to package-vivado-ips/src/xilinx/Axi4SpiFlash.scala diff --git a/module-vivado-ips/src/xilinx/Axi4WiderMemory.scala b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala similarity index 100% rename from module-vivado-ips/src/xilinx/Axi4WiderMemory.scala rename to package-vivado-ips/src/xilinx/Axi4WiderMemory.scala diff --git a/module-vivado-ips/src/xilinx/ClockingWizard.scala b/package-vivado-ips/src/xilinx/ClockingWizard.scala similarity index 100% rename from module-vivado-ips/src/xilinx/ClockingWizard.scala rename to package-vivado-ips/src/xilinx/ClockingWizard.scala diff --git a/module-vivado-ips/src/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala similarity index 100% rename from module-vivado-ips/src/xilinx/FloatingPoint.scala rename to package-vivado-ips/src/xilinx/FloatingPoint.scala diff --git a/module-vivado-ips/src/xilinx/IOBuffer.scala b/package-vivado-ips/src/xilinx/IOBuffer.scala similarity index 100% rename from module-vivado-ips/src/xilinx/IOBuffer.scala rename to package-vivado-ips/src/xilinx/IOBuffer.scala diff --git a/module-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala similarity index 100% rename from module-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala rename to package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala diff --git a/module-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala b/package-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala similarity index 100% rename from module-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala rename to package-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala diff --git a/module-vivado-ips/src/xilinx/bundle/Axi4Params.scala b/package-vivado-ips/src/xilinx/bundle/Axi4Params.scala similarity index 100% rename from module-vivado-ips/src/xilinx/bundle/Axi4Params.scala rename to package-vivado-ips/src/xilinx/bundle/Axi4Params.scala diff --git a/module-vivado-ips/test/resources/verilog/components/RamTestbench.sv b/package-vivado-ips/test/resources/verilog/components/RamTestbench.sv similarity index 100% rename from module-vivado-ips/test/resources/verilog/components/RamTestbench.sv rename to package-vivado-ips/test/resources/verilog/components/RamTestbench.sv diff --git a/module-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv b/package-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv similarity index 100% rename from module-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv rename to package-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv diff --git a/module-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv b/package-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv similarity index 100% rename from module-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv rename to package-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv diff --git a/module-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv b/package-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv similarity index 100% rename from module-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv rename to package-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv diff --git a/module-vivado-ips/test/resources/verilog/examples/AxiInterface.vh b/package-vivado-ips/test/resources/verilog/examples/AxiInterface.vh similarity index 100% rename from module-vivado-ips/test/resources/verilog/examples/AxiInterface.vh rename to package-vivado-ips/test/resources/verilog/examples/AxiInterface.vh diff --git a/module-vivado-ips/test/resources/verilog/examples/UartTestbench.sv b/package-vivado-ips/test/resources/verilog/examples/UartTestbench.sv similarity index 100% rename from module-vivado-ips/test/resources/verilog/examples/UartTestbench.sv rename to package-vivado-ips/test/resources/verilog/examples/UartTestbench.sv diff --git a/module-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd b/package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd similarity index 100% rename from module-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd rename to package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd From a2fd7b539a64bf93b826338f2d2935216c110318 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 00:29:44 -0700 Subject: [PATCH 08/18] ADD: update README --- .github/workflows/run-vivado-flow.yaml | 4 ++-- Makefile | 16 ++++++++-------- README.md | 10 ++++++---- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index a64003e..d570ab7 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -17,9 +17,9 @@ jobs: - name: Build MemorySubsystem run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project MODULE=delta-soc CONFIG=MemorySubsystem + make project PACKAGE=delta-soc MODULE=MemorySubsystem - name: Build MlpPolicyRunner run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project MODULE=delta-soc CONFIG=MlpPolicyRunner + make project PACKAGE=delta-soc MODULE=MlpPolicyRunner diff --git a/Makefile b/Makefile index 2013128..0caffd2 100644 --- a/Makefile +++ b/Makefile @@ -1,23 +1,23 @@ BUILD_DIR = ./generated-src -MODULE = vivado-ips - -CONFIG ?= MinimalArty100T +PACKAGE ?= vivado-ips +MODULE ?= MinimalArty100T +CONFIG ?= MinimalArty100TConfig MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - $(MILL_PATH) -i module-$(MODULE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG) - + $(MILL_PATH) -i package-$(PACKAGE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(MODULE) + project: verilog - $(MILL_PATH) -i module-$(MODULE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i package-$(PACKAGE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(MODULE) bitstream: project - $(MILL_PATH) -i module-$(MODULE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG) + $(MILL_PATH) -i package-$(PACKAGE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(MODULE) test: - $(MILL_PATH) -i module-$(MODULE).Test + $(MILL_PATH) -i package-$(PACKAGE).Test clean: rm -rf $(BUILD_DIR) diff --git a/README.md b/README.md index 5ce76d1..1d9a0e6 100644 --- a/README.md +++ b/README.md @@ -1,15 +1,17 @@ # MaDa -## Install Mill +## Getting Started + +This project uses Mill as the Scala build tool. A ready-to-run script is provided as `/toolchains/mill`. To invoke mill directly, do ```bash -./scripts/install-mill.sh +./toolchains/mill ``` -## Build Example +The directory structure is organized in standalone packages. When running build flow, both the package name and the config name need to be provided: ```bash -make verilog CONFIG=ExampleArty100TShell +make verilog PACKAGE=delta-soc CONFIG=MlpPolicyRunner ``` ## Build Bitstream From 1e30338ea012ed36ed84ef967ffe58a6ca8027c3 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 01:11:48 -0700 Subject: [PATCH 09/18] UPDATE: tcl generation --- builder/src/Builder.scala | 56 +++++++++++++++---- .../src/configs/MemorySubsystem.scala | 7 +++ .../src/configs/MlpPolicyRunner.scala | 12 ++-- package-delta-soc/src/memory/Axi4Memory.scala | 20 +++---- .../src/xilinx/Axi4BlockMemory.scala | 36 +++++------- .../src/xilinx/Axi4Crossbar.scala | 47 +++++++--------- .../src/xilinx/Axi4DataWidthConverter.scala | 36 ++++-------- .../src/xilinx/Axi4LiteCrossbar.scala | 51 +++++++---------- .../src/xilinx/Axi4LiteGpio.scala | 31 ++++------ .../src/xilinx/Axi4LiteStreamDataFifo.scala | 34 ++++------- .../src/xilinx/Axi4LiteTimer.scala | 36 ++++-------- .../src/xilinx/Axi4LiteUartLite.scala | 34 ++++------- .../src/xilinx/Axi4ProtocolConverter.scala | 34 ++++------- .../src/xilinx/Axi4QuadSpiFlash.scala | 46 +++++++-------- .../src/xilinx/Axi4SpiFlash.scala | 41 +++++--------- .../src/xilinx/Axi4WiderMemory.scala | 42 +++++--------- .../src/xilinx/ClockingWizard.scala | 37 ++++-------- .../src/xilinx/FloatingPoint.scala | 34 ++++------- 18 files changed, 257 insertions(+), 377 deletions(-) diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 388c954..15e9410 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -18,6 +18,7 @@ object BuilderConfig { val simulationFilelist = "generated-src/filelist_simulation.f" val constraintsFilelist = "generated-src/filelist_constraints.f" + val vivadoTclDir = "out/vivado-tcl" val vivadoProjectDir = "out/vivado-project" } @@ -42,6 +43,42 @@ object addConstraintResource { } } +object addVivadoTclScript { + def apply(path: String, content: String): Unit = { + println(s"adding Vivado TCL script: $path") + val file = new File(BuilderConfig.vivadoTclDir + "/" + path) + val writer = new PrintWriter(new FileWriter(file)) + writer.println(content) + writer.close() + } +} + +object addVivadoIp { + def apply( + name: String, + vendor: String, + library: String, + version: String, + moduleName: String, + extra: String, + ): Unit = { + addVivadoTclScript(s"create_ip_${moduleName.toLowerCase()}.tcl", { + s""" +create_ip -name ${name} -vendor ${vendor} -library ${library} -version ${version} -module_name ${moduleName} +generate_target {instantiation_template} [get_ips ${moduleName}] +update_compile_order -fileset sources_1 +generate_target all [get_ips ${moduleName}] +catch { config_ip_cache -export [get_ips -all ${moduleName}] } +export_ip_user_files -of_objects [get_ips ${moduleName}] -no_script -sync -force -quiet +create_ip_run [get_ips ${moduleName}] +${extra} +""" + }) + } +} + + + // helper function to parse the module name from the arguments object _parseModuleName { def apply(args: Array[String]): (String, Array[String]) = { @@ -72,8 +109,7 @@ object buildVerilog extends App { constraintsFilelist.close() } new File(BuilderConfig.vivadoProjectDir).mkdirs() - new File(s"${BuilderConfig.vivadoProjectDir}/scripts").mkdirs() - + new File(BuilderConfig.vivadoTclDir).mkdirs() val (moduleName, remainingArgs) = _parseModuleName(args) @@ -101,7 +137,7 @@ object buildProject extends App { val (moduleName, remainingArgs) = _parseModuleName(args) new File(BuilderConfig.vivadoProjectDir).mkdirs() - new File(s"${BuilderConfig.vivadoProjectDir}/scripts").mkdirs() + new File(BuilderConfig.vivadoTclDir).mkdirs() /* Arty A7 100T */ // val fpgaPart = "xc7a100ticsg324-1L" @@ -133,7 +169,7 @@ object buildProject extends App { { // create a run.tcl file - val runTcl = new PrintWriter(s"${BuilderConfig.vivadoProjectDir}/scripts/create_project.tcl") + val runTcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/create_project.tcl") // create project runTcl.println(s"create_project VivadoProject ${BuilderConfig.vivadoProjectDir} -part ${fpgaPart} -force") @@ -168,7 +204,7 @@ object buildProject extends App { /* create Vivado IPs */ runTcl.println("update_ip_catalog") - val create_ip_files = new File(s"${BuilderConfig.vivadoProjectDir}/scripts").listFiles(new FileFilter { + val create_ip_files = new File(BuilderConfig.vivadoTclDir).listFiles(new FileFilter { def accept(file: File): Boolean = file.isFile && file.getName != "create_project.tcl" }).map(_.getAbsolutePath) @@ -190,7 +226,7 @@ object buildProject extends App { } - s"vivado -mode batch -source ${BuilderConfig.vivadoProjectDir}/scripts/create_project.tcl".! + s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/create_project.tcl".! } object GenerateBitstream extends App { @@ -199,9 +235,9 @@ object GenerateBitstream extends App { // { // // create a generate_bitstream.tcl file - // val run_tcl = new PrintWriter(s"${vivado_project_dir}/scripts/generate_bitstream.tcl") + // val run_tcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/scripts/generate_bitstream.tcl") - // run_tcl.println(s"open_project ${vivado_project_dir}/VivadoProject.xpr") + // run_tcl.println(s"open_project ${BuilderConfig.vivadoTclDir}/VivadoProject.xpr") // val ip_name = "clk_wiz_0" @@ -220,12 +256,12 @@ object GenerateBitstream extends App { // run_tcl.println(s"wait_on_run impl_1") // run_tcl.println(s"open_run impl_1") - // run_tcl.println(s"write_bitstream ${vivado_project_dir}/Arty100TShell.bit -force") + // run_tcl.println(s"write_bitstream ${BuilderConfig.vivadoTclDir}/Arty100TShell.bit -force") // run_tcl.close() // run_tcl.flush() // make sure the file is written to the disk // } - // s"vivado -mode batch -source ${vivado_project_dir}/scripts/generate_bitstream.tcl".! + // s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/scripts/generate_bitstream.tcl".! } diff --git a/package-delta-soc/src/configs/MemorySubsystem.scala b/package-delta-soc/src/configs/MemorySubsystem.scala index fc24158..4025e88 100644 --- a/package-delta-soc/src/configs/MemorySubsystem.scala +++ b/package-delta-soc/src/configs/MemorySubsystem.scala @@ -150,4 +150,11 @@ class MemorySubsystem extends Module { qspi_io1_buf.io.I := flash.io.io1_o qspi_io1_buf.io.T := flash.io.io1_t + addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") + + addSimulationResource("package-delta-soc/test/MemorySubsystemTestbench.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv") + addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv") + addSimulationResource("package-delta-soc/resources/verilog/Ram.v") } diff --git a/package-delta-soc/src/configs/MlpPolicyRunner.scala b/package-delta-soc/src/configs/MlpPolicyRunner.scala index 1d6331d..c3833fe 100644 --- a/package-delta-soc/src/configs/MlpPolicyRunner.scala +++ b/package-delta-soc/src/configs/MlpPolicyRunner.scala @@ -172,11 +172,11 @@ class MlpPolicyRunner extends RawModule { } - addConstraintResource("module-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") + addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") - addSimulationResource("module-delta-soc/test/MlpPolicyRunnerTestbench.sv") - addSimulationResource("module-delta-soc/resources/verilog/SimUart.sv") - addSimulationResource("module-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") - addSimulationResource("module-delta-soc/resources/verilog/SimSpiFlashModel.sv") - addSimulationResource("module-delta-soc/resources/verilog/Ram.v") + addSimulationResource("package-delta-soc/test/MlpPolicyRunnerTestbench.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv") + addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv") + addSimulationResource("package-delta-soc/resources/verilog/Ram.v") } diff --git a/package-delta-soc/src/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala index 88156ad..7d18116 100644 --- a/package-delta-soc/src/memory/Axi4Memory.scala +++ b/package-delta-soc/src/memory/Axi4Memory.scala @@ -130,22 +130,16 @@ class Axi4Memory( io.s_axi.r.bits.data := mem.io.rdata - def generate_tcl_script(): Unit = { - if (memoryFileHex != "") { - val vivado_project_dir = "out/vivado-project" - - // Get current working directory + if (memoryFileHex != "") { + addVivadoTclScript(s"add_memory_${memoryFileHex}.tcl", { val file_path = System.getProperty("user.dir") + "/firmware/" + memoryFileHex - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/add_memory_${memoryFileHex}.tcl") - // Use current directory to create paths - tcl_script.println(s"add_files -norecurse ${file_path}") - tcl_script.println(s"set_property file_type {Memory Initialization Files} [get_files ${file_path}]") - - tcl_script.close() - } + s""" +add_files -norecurse ${file_path} +set_property file_type {Memory Initialization Files} [get_files ${file_path}] +""" + }) } - generate_tcl_script() } diff --git a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala index a3c8aac..afdc8df 100644 --- a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala @@ -33,18 +33,18 @@ class Axi4BlockMemoryBlackbox( val rstb_busy = Output(Bool()) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4BlockMemoryBlackbox" - val ip_name_lower = ip_name.toLowerCase() - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name ${ip_name}") - val fillUnused = "true" - - tcl_script.println(s""" + val ipName = "Axi4BlockMemoryBlackbox" + val fillUnused = "true" + + addVivadoIp( + name="blk_mem_gen", + vendor="xilinx.com", + library="ip", + version="8.4", + moduleName=ipName, + extra=s""" set_property -dict [list \\ CONFIG.AXI_Type {AXI4} \\ CONFIG.Interface_Type {AXI4} \\ @@ -53,17 +53,7 @@ set_property -dict [list \\ CONFIG.Load_Init_File {true} \\ CONFIG.Fill_Remaining_Memory_Locations {${fillUnused}} \\ CONFIG.Coe_File {${coeFile}} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } diff --git a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala index fdd83fd..9d25080 100644 --- a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala @@ -163,24 +163,16 @@ class Axi4CrossbarBlackbox( override def desiredName: String = s"Axi4CrossbarBlackbox_s${numSlave}_m${numMaster}_w${params.dataWidth}_id${params.idWidth}" - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = desiredName - val ip_name_lower = ip_name.toLowerCase() - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.println(s""" + val ipName = desiredName + addVivadoIp( + name="axi_crossbar", + vendor="xilinx.com", + library="ip", + version="2.1", + moduleName=ipName, + extra = { + val baseConfig = s""" set_property -dict [list \\ CONFIG.PROTOCOL {AXI4} \\ CONFIG.NUM_MI {${numMaster}} \\ @@ -191,19 +183,18 @@ set_property -dict [list \\ CONFIG.S00_THREAD_ID_WIDTH {1} \\ CONFIG.S01_SINGLE_THREAD {1} \\ CONFIG.S01_THREAD_ID_WIDTH {1} \\ - ] [get_ips ${ip_name}] -""") - - for (i <- 0 until numMaster) { - tcl_script.println(s""" + ] [get_ips ${ipName}] +""" + val masterConfigs = (0 until numMaster).map { i => +s""" set_property -dict [list \\ CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_ADDR_WIDTH {${log2Ceil(deviceSizes(i))}} \\ CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_BASE_ADDR {0x${deviceAddresses(i).toString(16).reverse.padTo(16, '0').reverse}} \\ -] [get_ips ${ip_name}] -""") +] [get_ips ${ipName}] +""" + }.mkString("\n") + + baseConfig + masterConfigs } - - tcl_script.close() - } - generate_tcl_script() + ) } \ No newline at end of file diff --git a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala index 4a4d4c3..9ba1cc7 100644 --- a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala @@ -31,31 +31,19 @@ class Axi4DataWidthConverterBlackbox( val m_axi = new Axi4BlackboxBundle(m_params) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4DataWidthConverterBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "Axi4DataWidthConverterBlackbox" + addVivadoIp( + name="axi_dwidth_converter", + vendor="xilinx.com", + library="ip", + version="2.1", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.MI_DATA_WIDTH {${m_params.dataWidth}} \\ CONFIG.SI_DATA_WIDTH {${s_params.dataWidth}} \\ CONFIG.SI_ID_WIDTH {${s_params.idWidth}} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() -} \ No newline at end of file +] [get_ips ${ipName}] +""" + ) +} diff --git a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala index 33cfa86..3193733 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala @@ -49,7 +49,7 @@ class Axi4LiteCrossbar( blackbox.io.aclk := clock blackbox.io.aresetn := ~reset.asBool - + // Map the vector of Axi4Lite slaves to a single wide Axi4LiteCrossbarBlackboxBundle // this is done because in Xilinx IP, multiple AXI4 Lite interface are concatenated // into a single wide AXI4 Lite signals @@ -102,7 +102,7 @@ class Axi4LiteCrossbar( io.m_axi(i).ar.bits.addr := blackbox.io.m_axi.araddr(32*i + 31, 32*i) } blackbox.io.m_axi.arready := Cat(io.m_axi.reverse.map(_.ar.ready)) - + blackbox.io.m_axi.rdata := Cat(io.m_axi.reverse.map(_.r.bits.data)) blackbox.io.m_axi.rresp := Cat(io.m_axi.reverse.map(_.r.bits.resp.asUInt)) blackbox.io.m_axi.rvalid := Cat(io.m_axi.reverse.map(_.r.valid)) @@ -123,41 +123,30 @@ class Axi4LiteCrossbarBlackbox( }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4LiteCrossbarBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.println(s""" + val ipName = "Axi4LiteCrossbarBlackbox" + addVivadoIp( + name="axi_crossbar", + vendor="xilinx.com", + library="ip", + version="2.1", + moduleName=ipName, + extra = { + val baseConfig = s""" set_property -dict [list \\ CONFIG.PROTOCOL {AXI4LITE} \\ CONFIG.NUM_MI {${numMaster}} \\ CONFIG.NUM_SI {${numSlave}} \\ -] [get_ips ${ip_name}] -""") - - for (i <- 0 until numMaster) { - tcl_script.println(s""" +] [get_ips ${ipName}] +""" + val masterConfigs = (0 until numMaster).map { i => s""" set_property -dict [list \\ CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_ADDR_WIDTH {${log2Ceil(deviceSizes(i))}} \\ CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_BASE_ADDR {0x${deviceAddresses(i).toString(16).reverse.padTo(16, '0').reverse}} \\ -] [get_ips ${ip_name}] -""") - } +] [get_ips ${ipName}] +""" + }.mkString("\n") - tcl_script.close() - } - generate_tcl_script() + baseConfig + masterConfigs + } + ) } \ No newline at end of file diff --git a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala index 8d179b7..8a6550b 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala @@ -32,24 +32,15 @@ class Axi4LiteGpioBlackbox extends BlackBox { val gpio_io_o = Output(UInt(32.W)) val gpio_io_t = Output(UInt(32.W)) }) - - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4LiteGpioBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_gpio -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() + + + val ipName = "Axi4LiteGpioBlackbox" + addVivadoIp( + name="axi_gpio", + vendor="xilinx.com", + library="ip", + version="2.0", + moduleName=ipName, + extra = "" + ) } diff --git a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala index 1f7983e..b28b81d 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala @@ -26,30 +26,18 @@ class Axi4LiteStreamDataFifoBlackbox(width: Int) extends BlackBox { val m_axis = new Axi4StreamBlackboxBundle() }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "AXIStreamDataFifo" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "AXIStreamDataFifo" + addVivadoIp( + name="axis_data_fifo", + vendor="xilinx.com", + library="ip", + version="2.0", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.HAS_TLAST {1} \\ CONFIG.TUSER_WIDTH {1} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } diff --git a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala index 9c98fd3..99f2d0b 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala @@ -16,7 +16,7 @@ class Axi4LiteTimer extends Module { }) val blackbox = Module(new Axi4LiteTimerBlackbox()) - + blackbox.io.s_axi_aclk := clock blackbox.io.s_axi_aresetn := ~reset.asBool blackbox.io.s_axi.connectFrom(io.s_axi) @@ -43,29 +43,17 @@ class Axi4LiteTimerBlackbox extends BlackBox { val freeze = Input(Bool()) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4LiteTimerBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_timer -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.println(s""" + val ipName = "Axi4LiteTimerBlackbox" + addVivadoIp( + name="axi_timer", + vendor="xilinx.com", + library="ip", + version="2.0", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.COUNT_WIDTH {32} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala index 1289d3e..24148ae 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala @@ -32,31 +32,19 @@ class Axi4LiteUartLiteBlackbox( val tx = Output(Bool()) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4LiteUartLiteBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "Axi4LiteUartLiteBlackbox" + addVivadoIp( + name="axi_uartlite", + vendor="xilinx.com", + library="ip", + version="2.0", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.C_BAUDRATE {115200} \\ CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {${axiClockFrequency}} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } diff --git a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala index 010f7f8..eba41ae 100644 --- a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala @@ -31,32 +31,20 @@ class Axi4ProtocolConverterBlackbox( val m_axi = new Axi4LiteBlackboxBundle(m_params) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4ProtocolConverterBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "Axi4ProtocolConverterBlackbox" + addVivadoIp( + name="axi_protocol_converter", + vendor="xilinx.com", + library="ip", + version="2.1", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.ID_WIDTH {${s_params.idWidth}} \\ CONFIG.MI_PROTOCOL {AXI4LITE} \\ CONFIG.SI_PROTOCOL {AXI4} \\ CONFIG.DATA_WIDTH {${s_params.dataWidth}} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } \ No newline at end of file diff --git a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala index db84326..ab9acbd 100644 --- a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala @@ -66,7 +66,7 @@ class Axi4QuadSpiFlash extends Module { io.io2_t := blackbox.io.io2_t blackbox.io.io3_i := io.io3_i io.io3_o := blackbox.io.io3_o - io.io3_t := blackbox.io.io3_t + io.io3_t := blackbox.io.io3_t // blackbox.io.sck_i := io.sck_i // io.sck_o := blackbox.io.sck_o // io.sck_t := blackbox.io.sck_t @@ -120,19 +120,19 @@ class Axi4QuadSpiFlashBlackbox extends BlackBox { val ip2intc_irpt = Output(Bool()) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4QuadSpiFlashBlackbox" - val ip_name_lower = ip_name.toLowerCase() + val ip_name = "Axi4QuadSpiFlashBlackbox" + val ip_name_lower = ip_name.toLowerCase() + addVivadoTclScript(s"create_ip_${ip_name_lower}.tcl", { - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name}") + // HACK: add flash memory file to Vivado project + // Get current working directory + val file_path = System.getProperty("user.dir") + "/firmware/" + "firmware.flash.8.hex" // the Flash memory used on the Arty is Spansion S25FL128S // it has 8 dummy cycles for single-mode read commands // and 6 dummy cycles for quad-mode read commands - tcl_script.println(s""" + s""" +create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name} set_property -dict [list \\ CONFIG.C_SPI_MEMORY {3} \\ CONFIG.C_USE_STARTUP {0} \\ @@ -141,25 +141,17 @@ set_property -dict [list \\ CONFIG.C_USE_STARTUP {1} \\ CONFIG.C_SPI_MODE {2} \\ ] [get_ips ${ip_name}] -""") - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") +generate_target {instantiation_template} [get_ips ${ip_name}] +update_compile_order -fileset sources_1 +generate_target all [get_ips ${ip_name}] +catch { config_ip_cache -export [get_ips -all ${ip_name}] } +export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet +create_ip_run [get_ips ${ip_name}] - // HACK: add flash memory file to Vivado project - // Get current working directory - val file_path = System.getProperty("user.dir") + "/firmware/" + "firmware.flash.8.hex" - - // Use current directory to create paths - tcl_script.println(s"add_files -norecurse ${file_path}") - tcl_script.println(s"set_property file_type {Memory Initialization Files} [get_files ${file_path}]") - - tcl_script.close() - } - generate_tcl_script() +add_files -norecurse ${file_path} +set_property file_type {Memory Initialization Files} [get_files ${file_path}] +""" + }) } diff --git a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala index b7d3ff2..2ea7b03 100644 --- a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala @@ -102,37 +102,24 @@ class Axi4SpiFlashBlackbox extends BlackBox { val ip2intc_irpt = Output(Bool()) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "Axi4SpiFlashBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name}") - - // the Flash memory used on the Arty is Spansion S25FL128S - // it has 8 dummy cycles for single-mode read commands - // and 6 dummy cycles for quad-mode read commands - tcl_script.println(s""" + // the Flash memory used on the Arty is Spansion S25FL128S + // it has 8 dummy cycles for single-mode read commands + // and 6 dummy cycles for quad-mode read commands + val ipName = "Axi4SpiFlashBlackbox" + addVivadoIp( + name="axi_quad_spi", + vendor="xilinx.com", + library="ip", + version="3.2", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.C_SPI_MEMORY {3} \\ CONFIG.C_USE_STARTUP {0} \\ CONFIG.C_XIP_MODE {1} \\ CONFIG.C_XIP_PERF_MODE {0} \\ CONFIG.C_USE_STARTUP {1} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } - diff --git a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala index c5b377f..b344719 100644 --- a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala @@ -18,7 +18,7 @@ class Axi4WiderMemory( val memAddressWidth = params.addressWidth - memAlignment val blackbox = Module(new WiderBlockMemoryBlackbox(params, coeFile)) - + // implementing AXI4 state machine from https://zipcpu.com/blog/2019/05/29/demoaxi.html val sWRITE_IDLE :: sWRITE_MID :: sWRITE_LAST :: sWRITE_END :: Nil = Enum(4) val reg_w_state = RegInit(sWRITE_IDLE) @@ -83,7 +83,7 @@ class Axi4WiderMemory( } } is (sREAD_MID) { // MID state - + } is (sREAD_HOLD) { // HOLD state when (io.s_axi.r.fire) { @@ -132,18 +132,15 @@ class WiderBlockMemoryBlackbox( val douta = Output(UInt(params.dataWidth.W)) }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "WiderBlockMemoryBlackbox" - val ip_name_lower = ip_name.toLowerCase() - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name ${ip_name}") - - val fillUnused = "true" - - tcl_script.println(s""" + val ipName = "WiderBlockMemoryBlackbox" + val fillUnused = "true" + addVivadoIp( + name="blk_mem_gen", + vendor="xilinx.com", + library="ip", + version="8.4", + moduleName=ipName, + extra=s""" set_property -dict [list \\ CONFIG.Use_Byte_Write_Enable {true} \\ CONFIG.Byte_Size {8} \\ @@ -154,17 +151,8 @@ set_property -dict [list \\ CONFIG.Load_Init_File {true} \\ CONFIG.Fill_Remaining_Memory_Locations {${fillUnused}} \\ CONFIG.Coe_File {${coeFile}} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } + diff --git a/package-vivado-ips/src/xilinx/ClockingWizard.scala b/package-vivado-ips/src/xilinx/ClockingWizard.scala index f14f92a..d624aee 100644 --- a/package-vivado-ips/src/xilinx/ClockingWizard.scala +++ b/package-vivado-ips/src/xilinx/ClockingWizard.scala @@ -47,20 +47,17 @@ class ClockingWizardBlackbox( val clk_out7 = if (get_used(6)) Output(Clock()) else null }) - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "ClockingWizardBlackbox" - val ip_name_lower = ip_name.toLowerCase() - val num_out_clks = clk_freqs.length - - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "ClockingWizardBlackbox" + addVivadoIp( + name="clk_wiz", + vendor="xilinx.com", + library="ip", + version="6.0", + moduleName=ipName, + extra = s""" set_property -dict [list \\ - CONFIG.NUM_OUT_CLKS {${num_out_clks}} \\ + CONFIG.NUM_OUT_CLKS {${clk_freqs.length}} \\ CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \\ CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \\ CONFIG.MMCM_CLKOUT1_DIVIDE {40} \\ @@ -92,17 +89,7 @@ set_property -dict [list \\ CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {${get_freq(6)}} \\ CONFIG.CLKOUT7_REQUESTED_PHASE {0.0} \\ CONFIG.CLKOUT7_REQUESTED_DUTY_CYCLE {50.0} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } diff --git a/package-vivado-ips/src/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala index d512ab7..6a4827a 100644 --- a/package-vivado-ips/src/xilinx/FloatingPoint.scala +++ b/package-vivado-ips/src/xilinx/FloatingPoint.scala @@ -41,17 +41,15 @@ class FloatingPointBlackbox( val m_axis_result_tvalid = Output(Bool()) val m_axis_result_tdata = Output(UInt(32.W)) }) - - def generate_tcl_script(): Unit = { - val vivado_project_dir = "out/vivado-project" - val ip_name = "FloatingPointBlackbox" - val ip_name_lower = ip_name.toLowerCase() - val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl") - - tcl_script.println(s"create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name ${ip_name}") - - tcl_script.println(s""" + val ipName = "FloatingPointBlackbox" + addVivadoIp( + name="floating_point", + vendor="xilinx.com", + library="ip", + version="7.1", + moduleName=ipName, + extra = s""" set_property -dict [list \\ CONFIG.A_Precision_Type {Single} \\ CONFIG.Add_Sub_Value {Add} \\ @@ -68,17 +66,7 @@ set_property -dict [list \\ CONFIG.Maximum_Latency {false} \\ CONFIG.Operation_Type {FMA} \\ CONFIG.Result_Precision_Type {Single} \\ -] [get_ips ${ip_name}] -""") - - tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]") - tcl_script.println("update_compile_order -fileset sources_1") - tcl_script.println(s"generate_target all [get_ips ${ip_name}]") - tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }") - tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet") - tcl_script.println(s"create_ip_run [get_ips ${ip_name}]") - - tcl_script.close() - } - generate_tcl_script() +] [get_ips ${ipName}] +""" + ) } From 1917f307169c3057225ce092a8d91f7331728696 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 02:16:08 -0700 Subject: [PATCH 10/18] REMOVE: unused --- .gitmodules | 0 env.sh | 7 - .../Axi4MemoryForTestTestbench.sv | 0 .../{examples => }/Axi4SpiFlashTestBench.sv | 0 .../verilog/{examples => }/AxiInterface.vh | 0 .../verilog/{examples => }/UartTestbench.sv | 0 .../resources/vhdl/components/SimSpiFlash.vhd | 486 ------------------ 7 files changed, 493 deletions(-) delete mode 100644 .gitmodules delete mode 100644 env.sh rename package-vivado-ips/test/resources/verilog/{examples => }/Axi4MemoryForTestTestbench.sv (100%) rename package-vivado-ips/test/resources/verilog/{examples => }/Axi4SpiFlashTestBench.sv (100%) rename package-vivado-ips/test/resources/verilog/{examples => }/AxiInterface.vh (100%) rename package-vivado-ips/test/resources/verilog/{examples => }/UartTestbench.sv (100%) delete mode 100644 package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index e69de29..0000000 diff --git a/env.sh b/env.sh deleted file mode 100644 index 66f33fb..0000000 --- a/env.sh +++ /dev/null @@ -1,7 +0,0 @@ -TOOLCHAIN_DIR="$PWD/toolchains" - -# Add toolchains to PATH -export PATH="$TOOLCHAIN_DIR:$PATH" - -export RISCV="/scratch/tk/Documents/RISCV/" -export PATH="$RISCV/riscv64-unknown-toolchain/bin/:$PATH" diff --git a/package-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv b/package-vivado-ips/test/resources/verilog/Axi4MemoryForTestTestbench.sv similarity index 100% rename from package-vivado-ips/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv rename to package-vivado-ips/test/resources/verilog/Axi4MemoryForTestTestbench.sv diff --git a/package-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv b/package-vivado-ips/test/resources/verilog/Axi4SpiFlashTestBench.sv similarity index 100% rename from package-vivado-ips/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv rename to package-vivado-ips/test/resources/verilog/Axi4SpiFlashTestBench.sv diff --git a/package-vivado-ips/test/resources/verilog/examples/AxiInterface.vh b/package-vivado-ips/test/resources/verilog/AxiInterface.vh similarity index 100% rename from package-vivado-ips/test/resources/verilog/examples/AxiInterface.vh rename to package-vivado-ips/test/resources/verilog/AxiInterface.vh diff --git a/package-vivado-ips/test/resources/verilog/examples/UartTestbench.sv b/package-vivado-ips/test/resources/verilog/UartTestbench.sv similarity index 100% rename from package-vivado-ips/test/resources/verilog/examples/UartTestbench.sv rename to package-vivado-ips/test/resources/verilog/UartTestbench.sv diff --git a/package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd b/package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd deleted file mode 100644 index bcdcd75..0000000 --- a/package-vivado-ips/test/resources/vhdl/components/SimSpiFlash.vhd +++ /dev/null @@ -1,486 +0,0 @@ ---SimSpiFlash --- file: SimSpiFlash.vhd --- --- (c) Copyright 2008 - 2023 Advanced Micro Devices, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Advanced Micro Devices, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- AMD, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) AMD shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or AMD had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- AMD products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of AMD products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ------------------------------------------------------------------------------- --- User entered comments ------------------------------------------------------------------------------- --- This is a self-desigined Memory model for XIP mode support memories to act as slave --- for AXI QSPI in Example design --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use ieee.std_logic_misc.all; - - -entity SimSpiFlash is generic ( - C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256. - C_ADDR_WIDTH : integer := 256;-- allowed 0,16,256. - - C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating - -- Standard, Dual or Quad mode - -- in Ports as well as internal - -- functionality - C_DATA_WIDTH : integer := 8 -- allowed 8,32. -); - port ( - MODEL_CLK : in std_logic; - MODEL_RESET : in std_logic; - Core_Clk : in std_logic; - Chip_Selectn : in std_logic; - - ------------------------------- - --*SPI port interface * -- - ------------------------------- - io0_i : in std_logic; -- MOSI signal in standard SPI - io0_o : out std_logic; - io0_t : out std_logic; - ------------------------------- - io1_i : in std_logic; -- MISO signal in standard SPI - io1_o : out std_logic; - io1_t : out std_logic; - ----------------- - -- quad mode pins - ----------------- - io2_i : in std_logic; - io2_o : out std_logic; - io2_t : out std_logic; - --------------- - io3_i : in std_logic; - io3_o : out std_logic; - io3_t : out std_logic - --------------------------------- -); -end SimSpiFlash; - -architecture imp of SimSpiFlash is - - -------------------------------------------------------------------------------------- - -- below attributes are added to reduce the synth warnings in Vivado tool - attribute DowngradeIPIdentifiedWarnings: string; - attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; - -------------------------------------------------------------------------------------- - - function log2(x : natural) return integer is - variable i : integer := 0; - variable val: integer := 1; - begin - if x = 0 then return 0; - else - for j in 0 to 29 loop -- for loop for XST - if val >= x then null; - else - i := i+1; - val := val*2; - end if; - end loop; - -- Fix per CR520627 XST was ignoring this anyway and printing a - -- Warning in SRP file. This will get rid of the warning and not - -- impact simulation. - -- synthesis translate_off - assert val >= x - report "Function log2 received argument larger" & - " than its capability of 2^30. " - severity failure; - -- synthesis translate_on - return i; - end if; - end function log2; - - - constant ADDR_WIDTH : INTEGER := log2(C_FIFO_DEPTH); - constant RESET_ACTIVE : std_logic := '0'; - constant CMD_FAST_READ : std_logic_vector(7 downto 0):= X"0B"; - constant CMD_DUAL_READ : std_logic_vector(7 downto 0):= X"BB"; - constant CMD_QUAD_READ : std_logic_vector(7 downto 0):= X"EB"; - constant Wait_std : INTEGER := (C_ADDR_WIDTH + 8); - constant Wait_dual : INTEGER := (C_ADDR_WIDTH/2 + 4); - constant Wait_quad : INTEGER := (C_ADDR_WIDTH/4 + 8); - - - signal Serial_Dout_0 : std_logic := '0'; - signal Serial_Dout_1 : std_logic := '0'; - signal Serial_Dout_2 : std_logic := '0'; - signal Serial_Dout_3 : std_logic := '0'; - - signal FIFO_RD_EN : std_logic := '0'; - signal rising : std_logic := '0'; - signal falling : std_logic := '0'; - signal SCK_D : std_logic := '0'; - - signal Count_Pulse : std_logic := '0'; - signal Count_Pulse_d : std_logic := '0'; - - - signal Wait_clk : INTEGER := 0; - signal Cnt_8_Clk : std_logic_vector(2 downto 0):=(others => '1'); - - signal Counter : std_logic_vector(5 downto 0):=(others => '0'); - signal Addr_Cnt : std_logic_vector(4 downto 0):=(others => '0'); - signal Read_Addr : std_logic_vector(4 downto 0):=(others => '1'); - - - signal Data_From_Rx_FIFO : std_logic_vector(0 to C_DATA_WIDTH-1):=(others => '0'); - signal Transmit_Data : std_logic_vector(0 to C_DATA_WIDTH-1):=(others => '0'); - - signal Read_Addr_Int,Count_Int : INTEGER := 0; - - - type STATE_TYPE is ( - IDLE, -- decode command can be combined here later - WAIT_STATE, - READ - ); - TYPE mem_array IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ram : mem_array:= ( - X"01",X"02",X"03",X"04", - X"05",X"06",X"07",X"08", - X"09",X"0A",X"0B",X"0C", - X"0D",X"0E",X"0F",X"10", - X"11",X"12",X"13",X"14", - X"15",X"16",X"17",X"18", - X"03",X"02",X"01",X"00", - X"FF",X"FF",X"FF",X"FF" - ); - - - - signal spi_cntrl_ns: STATE_TYPE; - - attribute dont_touch : string; - attribute dont_touch of Serial_Dout_0 : signal is "TRUE"; - attribute dont_touch of Serial_Dout_1 : signal is "TRUE"; - attribute dont_touch of Serial_Dout_2 : signal is "TRUE"; - attribute dont_touch of Serial_Dout_3 : signal is "TRUE"; - attribute dont_touch of Count_Pulse : signal is "TRUE"; - attribute dont_touch of FIFO_RD_EN : signal is "TRUE"; - attribute dont_touch of ram : signal is "TRUE"; - - attribute dont_touch of Count_Pulse_d : signal is "TRUE"; - attribute dont_touch of Wait_clk : signal is "TRUE"; - attribute dont_touch of Counter : signal is "TRUE"; - attribute dont_touch of Addr_Cnt : signal is "TRUE"; - attribute dont_touch of Read_Addr : signal is "TRUE"; - attribute dont_touch of Data_From_Rx_FIFO : signal is "TRUE"; - attribute dont_touch of Transmit_Data : signal is "TRUE"; - attribute dont_touch of spi_cntrl_ns : signal is "TRUE"; - - begin - Rising_falling_process: process(MODEL_CLK)is - ----- - begin - ----- - if(MODEL_CLK'event and MODEL_CLK = '1') then - if(MODEL_RESET = RESET_ACTIVE) then - SCK_D <= '0'; - else - SCK_D <= Core_Clk; - end if; - end if; - end process Rising_falling_process; - - rising <= Core_Clk and (not(SCK_D)); - falling <= SCK_D and (not(Core_Clk)); - - - - COUNTER_8_Cycles_Pos_PROCESS : process(MODEL_CLK)is - begin - ----- - if(MODEL_CLK'event and MODEL_CLK = '1') then --1 - if(MODEL_RESET = RESET_ACTIVE) then - Cnt_8_Clk <= (others => '1'); - elsif (Chip_Selectn = '1') then - Cnt_8_Clk <= (others => '1'); - elsif(rising = '1') then - Cnt_8_Clk <= Cnt_8_Clk + 1; - end if; - end if; - end process COUNTER_8_Cycles_Pos_PROCESS; - - COUNTER_PROCESS : process(MODEL_CLK)is - begin - ----- - if(MODEL_CLK'event and MODEL_CLK = '1') then --1 - if(MODEL_RESET = RESET_ACTIVE) then - Counter <= (others => '1'); - elsif (Chip_Selectn = '1') then - Counter <= (others => '1'); - elsif (falling = '1') then - Counter <= Counter + 1; - end if; - end if; - end process COUNTER_PROCESS; - - Count_Int <= CONV_INTEGER(Counter); - - Wait_clk <= Wait_std WHEN (C_SPI_MODE = 0) ELSE - Wait_dual WHEN (C_SPI_MODE = 1) ELSE - Wait_quad ; - - SPI_STATE_MACHINE_P: process(MODEL_CLK) - begin - if(MODEL_CLK'event and MODEL_CLK = '0') then --1 - - -------------------------- - case spi_cntrl_ns is - -------------------------- - when IDLE => - if(Chip_Selectn = '0') then - spi_cntrl_ns <= WAIT_STATE; - else - spi_cntrl_ns <= IDLE; - end if; - io0_t <= '1'; - io1_t <= '0'; - io2_t <= '0'; - io3_t <= '0'; - ------------------------------------- - when WAIT_STATE => - if(Chip_Selectn = '0') then - if (Count_Int = Wait_clk) then - spi_cntrl_ns <= READ; - else - spi_cntrl_ns <= WAIT_STATE; - end if; - else - spi_cntrl_ns <= IDLE; - end if; - io0_t <= '1'; - io1_t <= '0'; - io2_t <= '0'; - io3_t <= '0'; - ------------------------------------- - when READ => - if(Chip_Selectn = '0') then - spi_cntrl_ns <= READ; - else - spi_cntrl_ns <= IDLE; - end if; - io0_t <= '0'; - io1_t <= '0'; - io2_t <= '0'; - io3_t <= '0'; - when others => - spi_cntrl_ns <= IDLE; - io0_t <= '1'; - io1_t <= '0'; - io2_t <= '0'; - io3_t <= '0'; - ------------------------------------- - end case; - end if; - end process SPI_STATE_MACHINE_P; - - - Quad_Read_GENERATE : if (C_SPI_MODE = 2) generate - FIFO_READ_EN_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2 - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - FIFO_RD_EN <= '0'; - elsif((spi_cntrl_ns = READ) and (falling = '1'))then - FIFO_RD_EN <= Cnt_8_Clk(0) ; - end if; - end if; - end process FIFO_READ_EN_PROCESS; - - READ_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2 - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - Read_Addr <= (others => '1'); - Data_From_Rx_FIFO <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and (falling = '1')) then - Read_Addr <= Read_Addr + 1; - Data_From_Rx_FIFO <= ram(Read_Addr_Int) ; - end if; - end if; - end process READ_PROCESS; - - Read_Addr_Int <= CONV_INTEGER(Read_Addr); - - REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then - if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then - Transmit_Data <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and ( falling = '1'))then - Transmit_Data <= Data_From_Rx_FIFO; - elsif (falling = '1') then - Transmit_Data <= Transmit_Data(4 to (C_DATA_WIDTH-1)) & "0000"; - end if; - end if; - end process REGISTER_SHIFT_PROCESS; - end generate Quad_Read_GENERATE ; - - - Dual_Read_GENERATE : if (C_SPI_MODE = 1) generate - FIFO_READ_EN_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2 - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - FIFO_RD_EN <= '0'; - elsif((spi_cntrl_ns = READ) and (falling = '1'))then - FIFO_RD_EN <= Cnt_8_Clk(0) and (not(Cnt_8_Clk(1)));--not(Cnt_8_Clk(0) or Cnt_8_Clk(1)); - end if; - end if; - end process FIFO_READ_EN_PROCESS; - - - READ_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2 - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - Read_Addr <= (others => '1'); - Data_From_Rx_FIFO <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and (falling = '1')) then - Read_Addr <= Read_Addr + 1; - Data_From_Rx_FIFO <= ram(Read_Addr_Int) ; - end if; - end if; - end process READ_PROCESS; - - Read_Addr_Int <= CONV_INTEGER(Read_Addr); - - REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then - if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then - Transmit_Data <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and (falling = '1'))then - Transmit_Data <= Data_From_Rx_FIFO; - elsif (falling = '1') then - Transmit_Data <= Transmit_Data(2 to (C_DATA_WIDTH-1)) & "00"; - end if; - end if; - end process REGISTER_SHIFT_PROCESS; - end generate Dual_Read_GENERATE ; - - - STD_Read_Process : if (C_SPI_MODE = 0) generate - FIFO_READ_EN_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2 - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - FIFO_RD_EN <= '0'; - elsif((spi_cntrl_ns = READ) and (falling = '1'))then - FIFO_RD_EN <= Cnt_8_Clk(2) and Cnt_8_Clk(1) and Cnt_8_Clk(0) ; - end if; - end if; - end process FIFO_READ_EN_PROCESS; - - - READ_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then - if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then - Read_Addr <= (others => '1'); - Data_From_Rx_FIFO <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and (falling = '1')) then - Read_Addr <= Read_Addr + 1; - Data_From_Rx_FIFO <= ram(Read_Addr_Int) ; - end if; - end if; - end process READ_PROCESS; - - Read_Addr_Int <= CONV_INTEGER(Read_Addr); - - REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is - begin - if(MODEL_CLK'event and MODEL_CLK = '1') then - if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then - Transmit_Data <= (others => '0'); - elsif ((FIFO_RD_EN = '1') and (falling = '1'))then - Transmit_Data <= Data_From_Rx_FIFO; - elsif (falling = '1') then - Transmit_Data <= Transmit_Data(1 to (C_DATA_WIDTH-1)) & '0'; - end if; - end if; - end process REGISTER_SHIFT_PROCESS; - end generate STD_Read_Process ; - - - FIFO_READ_PROCESS: process(MODEL_CLK) is - ----- - begin - ----- - if(MODEL_CLK'event and MODEL_CLK = '1') then - if((MODEL_RESET = RESET_ACTIVE)or (Chip_Selectn = '1')) then - Serial_Dout_0 <= '0';-- default values of the IO0_O - Serial_Dout_1 <= '0'; - Serial_Dout_2 <= '0'; - Serial_Dout_3 <= '0'; - elsif (falling = '1') then - --if(spi_cntrl_ns = READ_DATA)then - --Shift_Reg <= Transmit_Data;-- loading trasmit data in SR - if(C_SPI_MODE = 0) then -- standard mode - Serial_Dout_1 <= Transmit_Data(0); - elsif(C_SPI_MODE = 1) then -- dual mode - Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O - Serial_Dout_0 <= Transmit_Data(1); - elsif(C_SPI_MODE = 2) then -- quad mode - Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O - Serial_Dout_2 <= Transmit_Data(1); - Serial_Dout_1 <= Transmit_Data(2); - Serial_Dout_0 <= Transmit_Data(3); - end if; - -- end if; - end if; - end if; - end process FIFO_READ_PROCESS; - - io0_o <= Serial_Dout_0; - io1_o <= Serial_Dout_1; - io2_o <= Serial_Dout_2; - io3_o <= Serial_Dout_3; -end imp; From 238d3761d0425288dd3f3d594b3575759b35c27c Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 02:35:05 -0700 Subject: [PATCH 11/18] REFACTOR: separate out amba axi interface --- build.mill.scala | 8 ++++++-- .../xilinx/bundle => package-amba/src}/Axi4Bundles.scala | 2 ++ .../xilinx/bundle => package-amba/src}/Axi4Params.scala | 2 ++ package-delta-soc/src/TestTiles.scala | 1 + package-delta-soc/src/Tile.scala | 1 + package-delta-soc/src/configs/MemorySubsystem.scala | 2 +- package-delta-soc/src/configs/MlpPolicyRunner.scala | 4 +--- package-delta-soc/src/core/Core.scala | 1 + package-delta-soc/src/core/InstructionFetch.scala | 1 + package-delta-soc/src/core/LoadStore.scala | 1 + package-delta-soc/src/core/SimdLoadStore.scala | 1 + .../src/interconnect/Axi4WidthDownsizer.scala | 2 ++ package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala | 2 ++ package-delta-soc/src/memory/Axi4LiteMemory.scala | 2 +- package-delta-soc/src/memory/Axi4Memory.scala | 3 +-- package-delta-soc/src/memory/Axi4MemoryWithLatency.scala | 3 +-- package-vivado-ips/src/xilinx/Axi4BlockMemory.scala | 2 +- package-vivado-ips/src/xilinx/Axi4Crossbar.scala | 3 +-- .../src/xilinx/Axi4DataWidthConverter.scala | 2 +- package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala | 3 +-- package-vivado-ips/src/xilinx/Axi4LiteGpio.scala | 3 +-- .../src/xilinx/Axi4LiteStreamDataFifo.scala | 3 +-- package-vivado-ips/src/xilinx/Axi4LiteTimer.scala | 2 +- package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala | 2 +- package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala | 2 +- package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala | 2 +- package-vivado-ips/src/xilinx/Axi4SpiFlash.scala | 2 +- package-vivado-ips/src/xilinx/Axi4WiderMemory.scala | 3 +-- package-vivado-ips/src/xilinx/ClockingWizard.scala | 1 - package-vivado-ips/src/xilinx/FloatingPoint.scala | 2 -- .../src/xilinx/bundle/Axi4BlackboxBundles.scala | 2 +- 31 files changed, 38 insertions(+), 32 deletions(-) rename {package-vivado-ips/src/xilinx/bundle => package-amba/src}/Axi4Bundles.scala (99%) rename {package-vivado-ips/src/xilinx/bundle => package-amba/src}/Axi4Params.scala (95%) diff --git a/build.mill.scala b/build.mill.scala index 83f8a94..fbbcab2 100644 --- a/build.mill.scala +++ b/build.mill.scala @@ -56,12 +56,16 @@ trait ChiselModule extends ScalaModule with ScalafmtModule { m => object builder extends ChiselModule -object `package-vivado-ips` extends ChiselModule { m => +object `package-amba` extends ChiselModule { m => override def moduleDeps = Seq(builder) } +object `package-vivado-ips` extends ChiselModule { m => + override def moduleDeps = Seq(builder, `package-amba`) +} + object `package-delta-soc` extends ChiselModule { m => - override def moduleDeps = Seq(builder, `package-vivado-ips`) + override def moduleDeps = Seq(builder, `package-amba`, `package-vivado-ips`) } object `package-chipyard-wrapper` extends ChiselModule { m => diff --git a/package-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala b/package-amba/src/Axi4Bundles.scala similarity index 99% rename from package-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala rename to package-amba/src/Axi4Bundles.scala index 5dc6fac..063536d 100644 --- a/package-vivado-ips/src/xilinx/bundle/Axi4Bundles.scala +++ b/package-amba/src/Axi4Bundles.scala @@ -1,3 +1,5 @@ +package amba + /** * Axi4Bundle.scala * diff --git a/package-vivado-ips/src/xilinx/bundle/Axi4Params.scala b/package-amba/src/Axi4Params.scala similarity index 95% rename from package-vivado-ips/src/xilinx/bundle/Axi4Params.scala rename to package-amba/src/Axi4Params.scala index 23b3524..b45a307 100644 --- a/package-vivado-ips/src/xilinx/bundle/Axi4Params.scala +++ b/package-amba/src/Axi4Params.scala @@ -1,3 +1,5 @@ +package amba + import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/TestTiles.scala b/package-delta-soc/src/TestTiles.scala index 56daa8b..863b80b 100644 --- a/package-delta-soc/src/TestTiles.scala +++ b/package-delta-soc/src/TestTiles.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} class EECS151Tile extends Module { diff --git a/package-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala index 6bceba6..5bb44a9 100644 --- a/package-delta-soc/src/Tile.scala +++ b/package-delta-soc/src/Tile.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} class Tile( diff --git a/package-delta-soc/src/configs/MemorySubsystem.scala b/package-delta-soc/src/configs/MemorySubsystem.scala index 4025e88..3892026 100644 --- a/package-delta-soc/src/configs/MemorySubsystem.scala +++ b/package-delta-soc/src/configs/MemorySubsystem.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.Analog - +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} /** * diff --git a/package-delta-soc/src/configs/MlpPolicyRunner.scala b/package-delta-soc/src/configs/MlpPolicyRunner.scala index c3833fe..c0cb2d8 100644 --- a/package-delta-soc/src/configs/MlpPolicyRunner.scala +++ b/package-delta-soc/src/configs/MlpPolicyRunner.scala @@ -1,8 +1,6 @@ import chisel3._ import chisel3.util._ - - - +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} /** diff --git a/package-delta-soc/src/core/Core.scala b/package-delta-soc/src/core/Core.scala index e1ace6c..484499f 100644 --- a/package-delta-soc/src/core/Core.scala +++ b/package-delta-soc/src/core/Core.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} import CsrControlConstants._ import RiscvConstants._ diff --git a/package-delta-soc/src/core/InstructionFetch.scala b/package-delta-soc/src/core/InstructionFetch.scala index 38fa368..41a32ba 100644 --- a/package-delta-soc/src/core/InstructionFetch.scala +++ b/package-delta-soc/src/core/InstructionFetch.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4LiteBundle} import CsrControlConstants._ import Instructions._ diff --git a/package-delta-soc/src/core/LoadStore.scala b/package-delta-soc/src/core/LoadStore.scala index ba88569..171716e 100644 --- a/package-delta-soc/src/core/LoadStore.scala +++ b/package-delta-soc/src/core/LoadStore.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} import Instructions._ import ScalarControlConstants._ diff --git a/package-delta-soc/src/core/SimdLoadStore.scala b/package-delta-soc/src/core/SimdLoadStore.scala index 122c5e3..39fe5ae 100644 --- a/package-delta-soc/src/core/SimdLoadStore.scala +++ b/package-delta-soc/src/core/SimdLoadStore.scala @@ -1,5 +1,6 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} import Instructions._ import ScalarControlConstants._ diff --git a/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala index 55c656f..dee84f3 100644 --- a/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala +++ b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala @@ -1,5 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle} + class Axi4WidthDownsizer( s_params: Axi4Params = Axi4Params(dataWidth = 64), diff --git a/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala index b8727bf..0365647 100644 --- a/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala +++ b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala @@ -1,5 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle} + class Axi4WidthUpsizer( s_params: Axi4Params = Axi4Params(dataWidth = 32), diff --git a/package-delta-soc/src/memory/Axi4LiteMemory.scala b/package-delta-soc/src/memory/Axi4LiteMemory.scala index c4dd749..9ddabe7 100644 --- a/package-delta-soc/src/memory/Axi4LiteMemory.scala +++ b/package-delta-soc/src/memory/Axi4LiteMemory.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4LiteBundle} -import java.io.PrintWriter class Axi4LiteMemory( val params: Axi4Params = Axi4Params(), diff --git a/package-delta-soc/src/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala index 7d18116..1c2e4f5 100644 --- a/package-delta-soc/src/memory/Axi4Memory.scala +++ b/package-delta-soc/src/memory/Axi4Memory.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, AxResponse} class Axi4Memory( diff --git a/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala index c4b08de..e993371 100644 --- a/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala +++ b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, ChannelAx, ChannelW, ChannelR} class Axi4MemoryWithLatency( diff --git a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala index afdc8df..8035620 100644 --- a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala @@ -1,6 +1,6 @@ import chisel3._ import chisel3.util._ -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle} class Axi4BlockMemory( diff --git a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala index 9d25080..ea0a0e9 100644 --- a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} class Axi4CrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala index 9ba1cc7..a659c24 100644 --- a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala @@ -1,6 +1,6 @@ import chisel3._ import chisel3.util._ -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle} class Axi4DataWidthConverter( diff --git a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala index 3193733..55ebc05 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst, Axi4LiteBundle} class Axi4LiteCrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala index 8a6550b..546d639 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4LiteBundle} class Axi4LiteGpio extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala index b28b81d..8bd0b9d 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4StreamBundle} class Axi4LiteStreamDataFifo(width: Int) extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala index 99f2d0b..7e56ca3 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4LiteBundle} -import java.io.PrintWriter class Axi4LiteTimer extends Module { val io = IO(new Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala index 24148ae..a60adfc 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4LiteBundle} -import java.io.PrintWriter class Axi4LiteUartLite( val axiClockFrequency: Int = 100, diff --git a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala index eba41ae..6df3dcc 100644 --- a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala @@ -1,6 +1,6 @@ import chisel3._ import chisel3.util._ -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} class Axi4ProtocolConverter( diff --git a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala index ab9acbd..2e3f249 100644 --- a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} -import java.io.PrintWriter class Axi4QuadSpiFlash extends Module { val io = IO(new Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala index 2ea7b03..5084f5c 100644 --- a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala @@ -1,7 +1,7 @@ import chisel3._ import chisel3.util._ +import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} -import java.io.PrintWriter class Axi4SpiFlash extends Module { val io = IO(new Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala index b344719..5c85708 100644 --- a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala @@ -1,7 +1,6 @@ import chisel3._ import chisel3.util._ - -import java.io.PrintWriter +import amba.{Axi4Params, Axi4Bundle, AxResponse} class Axi4WiderMemory( diff --git a/package-vivado-ips/src/xilinx/ClockingWizard.scala b/package-vivado-ips/src/xilinx/ClockingWizard.scala index d624aee..f4a2478 100644 --- a/package-vivado-ips/src/xilinx/ClockingWizard.scala +++ b/package-vivado-ips/src/xilinx/ClockingWizard.scala @@ -1,7 +1,6 @@ import chisel3.{BlackBox, _} import chisel3.util._ -import java.io.PrintWriter class ClockingWizard( clk_freqs: Seq[Int] diff --git a/package-vivado-ips/src/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala index 6a4827a..e0e0543 100644 --- a/package-vivado-ips/src/xilinx/FloatingPoint.scala +++ b/package-vivado-ips/src/xilinx/FloatingPoint.scala @@ -1,8 +1,6 @@ import chisel3._ import chisel3.util._ -import java.io.PrintWriter - class FloatingPoint( val pipelineStages: Int = 1 diff --git a/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala index 8eeb810..dbbddba 100644 --- a/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala +++ b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala @@ -1,6 +1,6 @@ import chisel3._ import chisel3.util._ - +import amba.{Axi4Params, Axi4Bundle, Axi4Constants, Axi4LiteBundle, Axi4StreamBundle, AxResponse, AxSize, AxBurst} class Axi4LiteBlackboxBundle(params: Axi4Params = Axi4Params()) extends Bundle { From 4400584cd878c7ba515089ce20f7e7ce1dd955d7 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 09:54:06 -0700 Subject: [PATCH 12/18] ADD: separate things into packages --- .github/workflows/run-vivado-flow.yaml | 4 ++-- Makefile | 6 +++--- README.md | 2 +- builder/src/Builder.scala | 2 ++ package-chipyard-wrapper/src/DigitalTop.scala | 3 ++- package-chipyard-wrapper/src/MotorArty100T.scala | 2 ++ package-chipyard-wrapper/src/TinyRocketArty100T.scala | 2 ++ package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala | 2 ++ package-delta-soc/src/TestTiles.scala | 3 +++ package-delta-soc/src/Tile.scala | 3 +++ package-delta-soc/src/configs/MemorySubsystem.scala | 5 +++++ package-delta-soc/src/configs/MlpPolicyRunner.scala | 4 ++++ package-delta-soc/src/constants/Constants.scala | 1 + package-delta-soc/src/constants/Instructions.scala | 2 +- package-delta-soc/src/core/ALU.scala | 2 ++ package-delta-soc/src/core/CSR.scala | 2 ++ package-delta-soc/src/core/Core.scala | 2 ++ package-delta-soc/src/core/InstructionDecode.scala | 2 ++ package-delta-soc/src/core/InstructionFetch.scala | 2 ++ package-delta-soc/src/core/LoadStore.scala | 2 ++ package-delta-soc/src/core/SimdFloatingPoint.scala | 3 +++ package-delta-soc/src/core/SimdLoadStore.scala | 2 ++ package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala | 2 ++ package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala | 2 ++ package-delta-soc/src/memory/AsyncRam.scala | 2 ++ package-delta-soc/src/memory/Axi4LiteMemory.scala | 2 ++ package-delta-soc/src/memory/Axi4Memory.scala | 3 +++ package-delta-soc/src/memory/Axi4MemoryWithLatency.scala | 2 ++ package-delta-soc/src/memory/Ram.scala | 2 ++ package-tacit/src/MadaTimer.scala | 3 +++ package-vivado-ips/src/Arty100TTop.scala | 2 ++ package-vivado-ips/src/MinimalArty100T.scala | 2 ++ package-vivado-ips/src/ZedboardTop.scala | 2 ++ package-vivado-ips/src/basic/ClockDivider.scala | 2 ++ package-vivado-ips/src/basic/SyncReset.scala | 2 ++ package-vivado-ips/src/xilinx/Axi4BlockMemory.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4Crossbar.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4LiteGpio.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4LiteTimer.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4SpiFlash.scala | 3 +++ package-vivado-ips/src/xilinx/Axi4WiderMemory.scala | 3 +++ package-vivado-ips/src/xilinx/ClockingWizard.scala | 3 +++ package-vivado-ips/src/xilinx/FloatingPoint.scala | 3 +++ package-vivado-ips/src/xilinx/IOBuffer.scala | 2 ++ .../src/xilinx/bundle/Axi4BlackboxBundles.scala | 2 ++ 51 files changed, 124 insertions(+), 8 deletions(-) diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index d570ab7..4600782 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -17,9 +17,9 @@ jobs: - name: Build MemorySubsystem run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project PACKAGE=delta-soc MODULE=MemorySubsystem + make project PACKAGE=delta-soc MODULE=delta.MemorySubsystem - name: Build MlpPolicyRunner run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project PACKAGE=delta-soc MODULE=MlpPolicyRunner + make project PACKAGE=delta-soc MODULE=delta.MlpPolicyRunner diff --git a/Makefile b/Makefile index 0caffd2..9adbd5f 100644 --- a/Makefile +++ b/Makefile @@ -8,13 +8,13 @@ MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - $(MILL_PATH) -i package-$(PACKAGE).runMain buildVerilog --target-dir $(BUILD_DIR) --module-name $(MODULE) + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildVerilog --target-dir $(BUILD_DIR) --module-name $(MODULE) project: verilog - $(MILL_PATH) -i package-$(PACKAGE).runMain buildProject --target-dir $(BUILD_DIR) --module-name $(MODULE) + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildProject --target-dir $(BUILD_DIR) --module-name $(MODULE) bitstream: project - $(MILL_PATH) -i package-$(PACKAGE).runMain buildBitstream --target-dir $(BUILD_DIR) --module-name $(MODULE) + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildBitstream --target-dir $(BUILD_DIR) --module-name $(MODULE) test: $(MILL_PATH) -i package-$(PACKAGE).Test diff --git a/README.md b/README.md index 1d9a0e6..9e4fd7f 100644 --- a/README.md +++ b/README.md @@ -11,7 +11,7 @@ This project uses Mill as the Scala build tool. A ready-to-run script is provide The directory structure is organized in standalone packages. When running build flow, both the package name and the config name need to be provided: ```bash -make verilog PACKAGE=delta-soc CONFIG=MlpPolicyRunner +make verilog PACKAGE=delta-soc MODULE=delta.MlpPolicyRunner ``` ## Build Bitstream diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 15e9410..fb0df2d 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -1,3 +1,5 @@ +package builder + /** * Builder.scala * diff --git a/package-chipyard-wrapper/src/DigitalTop.scala b/package-chipyard-wrapper/src/DigitalTop.scala index 35b4e81..759a802 100644 --- a/package-chipyard-wrapper/src/DigitalTop.scala +++ b/package-chipyard-wrapper/src/DigitalTop.scala @@ -1,8 +1,9 @@ +package chipyardwrapper + import chisel3.{BlackBox, _} import chisel3.util._ - class DigitalTop extends BlackBox { val io = IO(new Bundle { val auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock = Input(Clock()) diff --git a/package-chipyard-wrapper/src/MotorArty100T.scala b/package-chipyard-wrapper/src/MotorArty100T.scala index 71256ad..23b20d0 100644 --- a/package-chipyard-wrapper/src/MotorArty100T.scala +++ b/package-chipyard-wrapper/src/MotorArty100T.scala @@ -1,3 +1,5 @@ +package chipyardwrapper + // import chisel3._ // import chisel3.util._ diff --git a/package-chipyard-wrapper/src/TinyRocketArty100T.scala b/package-chipyard-wrapper/src/TinyRocketArty100T.scala index 73b78fc..22706af 100644 --- a/package-chipyard-wrapper/src/TinyRocketArty100T.scala +++ b/package-chipyard-wrapper/src/TinyRocketArty100T.scala @@ -1,3 +1,5 @@ +package chipyardwrapper + import chisel3._ import chisel3.util._ diff --git a/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala b/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala index e4774ae..e60252c 100644 --- a/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala +++ b/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala @@ -1,3 +1,5 @@ +package chipyardwrapper + // import chisel3._ // import chisel3.util._ diff --git a/package-delta-soc/src/TestTiles.scala b/package-delta-soc/src/TestTiles.scala index 863b80b..e7e6af5 100644 --- a/package-delta-soc/src/TestTiles.scala +++ b/package-delta-soc/src/TestTiles.scala @@ -1,6 +1,9 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import vivadoips.{Axi4Crossbar, Axi4BlockMemory} class EECS151Tile extends Module { diff --git a/package-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala index 5bb44a9..b582817 100644 --- a/package-delta-soc/src/Tile.scala +++ b/package-delta-soc/src/Tile.scala @@ -1,6 +1,9 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import vivadoips.{Axi4Crossbar, Axi4BlockMemory, Axi4DataWidthConverter} class Tile( diff --git a/package-delta-soc/src/configs/MemorySubsystem.scala b/package-delta-soc/src/configs/MemorySubsystem.scala index 3892026..136aa5d 100644 --- a/package-delta-soc/src/configs/MemorySubsystem.scala +++ b/package-delta-soc/src/configs/MemorySubsystem.scala @@ -1,7 +1,12 @@ +package delta + import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import vivadoips.{Axi4Crossbar, Axi4DataWidthConverter, Axi4SpiFlash, Axi4LiteUartLite, Axi4LiteGpio, IOBUF} +import builder.{addConstraintResource, addSimulationResource} + /** * diff --git a/package-delta-soc/src/configs/MlpPolicyRunner.scala b/package-delta-soc/src/configs/MlpPolicyRunner.scala index c0cb2d8..4ebd9a7 100644 --- a/package-delta-soc/src/configs/MlpPolicyRunner.scala +++ b/package-delta-soc/src/configs/MlpPolicyRunner.scala @@ -1,6 +1,10 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import vivadoips.{Axi4Crossbar, Axi4DataWidthConverter, Axi4LiteTimer, Axi4LiteCrossbar, Axi4SpiFlash, Axi4QuadSpiFlash, Axi4LiteUartLite, Axi4LiteGpio, IOBUF, ClockingWizard, SyncReset, Arty100TIO} +import builder.{addConstraintResource, addSimulationResource} /** diff --git a/package-delta-soc/src/constants/Constants.scala b/package-delta-soc/src/constants/Constants.scala index 99a538e..2c485a0 100644 --- a/package-delta-soc/src/constants/Constants.scala +++ b/package-delta-soc/src/constants/Constants.scala @@ -1,3 +1,4 @@ +package delta import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/constants/Instructions.scala b/package-delta-soc/src/constants/Instructions.scala index 7fb511f..9d800f3 100644 --- a/package-delta-soc/src/constants/Instructions.scala +++ b/package-delta-soc/src/constants/Instructions.scala @@ -1,4 +1,4 @@ -// See LICENSE for license details. +package delta import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/core/ALU.scala b/package-delta-soc/src/core/ALU.scala index e9b03f6..af9ecdf 100644 --- a/package-delta-soc/src/core/ALU.scala +++ b/package-delta-soc/src/core/ALU.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/core/CSR.scala b/package-delta-soc/src/core/CSR.scala index d24707e..14d68a5 100644 --- a/package-delta-soc/src/core/CSR.scala +++ b/package-delta-soc/src/core/CSR.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/core/Core.scala b/package-delta-soc/src/core/Core.scala index 484499f..3e8b51f 100644 --- a/package-delta-soc/src/core/Core.scala +++ b/package-delta-soc/src/core/Core.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} diff --git a/package-delta-soc/src/core/InstructionDecode.scala b/package-delta-soc/src/core/InstructionDecode.scala index 824dec7..90bdfee 100644 --- a/package-delta-soc/src/core/InstructionDecode.scala +++ b/package-delta-soc/src/core/InstructionDecode.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/core/InstructionFetch.scala b/package-delta-soc/src/core/InstructionFetch.scala index 41a32ba..b61d4c3 100644 --- a/package-delta-soc/src/core/InstructionFetch.scala +++ b/package-delta-soc/src/core/InstructionFetch.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4LiteBundle} diff --git a/package-delta-soc/src/core/LoadStore.scala b/package-delta-soc/src/core/LoadStore.scala index 171716e..cb98da0 100644 --- a/package-delta-soc/src/core/LoadStore.scala +++ b/package-delta-soc/src/core/LoadStore.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} diff --git a/package-delta-soc/src/core/SimdFloatingPoint.scala b/package-delta-soc/src/core/SimdFloatingPoint.scala index 23752fc..3b18645 100644 --- a/package-delta-soc/src/core/SimdFloatingPoint.scala +++ b/package-delta-soc/src/core/SimdFloatingPoint.scala @@ -1,5 +1,8 @@ +package delta + import chisel3._ import chisel3.util._ +import vivadoips.FloatingPoint import Instructions._ import SimdControlConstants._ diff --git a/package-delta-soc/src/core/SimdLoadStore.scala b/package-delta-soc/src/core/SimdLoadStore.scala index 39fe5ae..76bce00 100644 --- a/package-delta-soc/src/core/SimdLoadStore.scala +++ b/package-delta-soc/src/core/SimdLoadStore.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} diff --git a/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala index dee84f3..10f4e45 100644 --- a/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala +++ b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle} diff --git a/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala index 0365647..22207a5 100644 --- a/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala +++ b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle} diff --git a/package-delta-soc/src/memory/AsyncRam.scala b/package-delta-soc/src/memory/AsyncRam.scala index d0f2ef9..dbc6430 100644 --- a/package-delta-soc/src/memory/AsyncRam.scala +++ b/package-delta-soc/src/memory/AsyncRam.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ diff --git a/package-delta-soc/src/memory/Axi4LiteMemory.scala b/package-delta-soc/src/memory/Axi4LiteMemory.scala index 9ddabe7..ae95fc0 100644 --- a/package-delta-soc/src/memory/Axi4LiteMemory.scala +++ b/package-delta-soc/src/memory/Axi4LiteMemory.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4LiteBundle} diff --git a/package-delta-soc/src/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala index 1c2e4f5..072d065 100644 --- a/package-delta-soc/src/memory/Axi4Memory.scala +++ b/package-delta-soc/src/memory/Axi4Memory.scala @@ -1,6 +1,9 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse} +import builder.{addVivadoTclScript} class Axi4Memory( diff --git a/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala index e993371..e71f460 100644 --- a/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala +++ b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, ChannelAx, ChannelW, ChannelR} diff --git a/package-delta-soc/src/memory/Ram.scala b/package-delta-soc/src/memory/Ram.scala index 379adc5..a7e4b3f 100644 --- a/package-delta-soc/src/memory/Ram.scala +++ b/package-delta-soc/src/memory/Ram.scala @@ -1,3 +1,5 @@ +package delta + import chisel3._ import chisel3.util._ diff --git a/package-tacit/src/MadaTimer.scala b/package-tacit/src/MadaTimer.scala index bfca9e9..d36e4df 100644 --- a/package-tacit/src/MadaTimer.scala +++ b/package-tacit/src/MadaTimer.scala @@ -1,7 +1,10 @@ +package tacit + import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode._ + class PrescalerCounter extends Module { val io = IO(new Bundle { val enable = Input(Bool()) diff --git a/package-vivado-ips/src/Arty100TTop.scala b/package-vivado-ips/src/Arty100TTop.scala index 29a82c0..6ac0be0 100644 --- a/package-vivado-ips/src/Arty100TTop.scala +++ b/package-vivado-ips/src/Arty100TTop.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ import chisel3.experimental.Analog diff --git a/package-vivado-ips/src/MinimalArty100T.scala b/package-vivado-ips/src/MinimalArty100T.scala index 6589e2d..7fed6fe 100644 --- a/package-vivado-ips/src/MinimalArty100T.scala +++ b/package-vivado-ips/src/MinimalArty100T.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ import chisel3.experimental.Analog diff --git a/package-vivado-ips/src/ZedboardTop.scala b/package-vivado-ips/src/ZedboardTop.scala index c2d9606..6565d74 100644 --- a/package-vivado-ips/src/ZedboardTop.scala +++ b/package-vivado-ips/src/ZedboardTop.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ diff --git a/package-vivado-ips/src/basic/ClockDivider.scala b/package-vivado-ips/src/basic/ClockDivider.scala index 97d976f..bc1af43 100644 --- a/package-vivado-ips/src/basic/ClockDivider.scala +++ b/package-vivado-ips/src/basic/ClockDivider.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ diff --git a/package-vivado-ips/src/basic/SyncReset.scala b/package-vivado-ips/src/basic/SyncReset.scala index f71792d..ddbd253 100644 --- a/package-vivado-ips/src/basic/SyncReset.scala +++ b/package-vivado-ips/src/basic/SyncReset.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ diff --git a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala index 8035620..3e895ba 100644 --- a/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle} +import builder.addVivadoIp class Axi4BlockMemory( diff --git a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala index ea0a0e9..d998198 100644 --- a/package-vivado-ips/src/xilinx/Axi4Crossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst} +import builder.addVivadoIp class Axi4CrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala index a659c24..055daad 100644 --- a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle} +import builder.addVivadoIp class Axi4DataWidthConverter( diff --git a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala index 55ebc05..941e51c 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst, Axi4LiteBundle} +import builder.addVivadoIp class Axi4LiteCrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala index 546d639..fb7f946 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4LiteBundle} +import builder.addVivadoIp class Axi4LiteGpio extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala index 8bd0b9d..76e9fe9 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4StreamBundle} +import builder.addVivadoIp class Axi4LiteStreamDataFifo(width: Int) extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala index 7e56ca3..b7298fb 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4LiteBundle} +import builder.addVivadoIp class Axi4LiteTimer extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala index a60adfc..99046fc 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4LiteBundle} +import builder.addVivadoIp class Axi4LiteUartLite( diff --git a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala index 6df3dcc..c0b3f66 100644 --- a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala +++ b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import builder.addVivadoIp class Axi4ProtocolConverter( diff --git a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala index 2e3f249..dbaa285 100644 --- a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import builder.{addVivadoIp, addVivadoTclScript} class Axi4QuadSpiFlash extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala index 5084f5c..a0e6bb1 100644 --- a/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} +import builder.addVivadoIp class Axi4SpiFlash extends Module { diff --git a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala index 5c85708..39a1335 100644 --- a/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala +++ b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala @@ -1,6 +1,9 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, AxResponse} +import builder.addVivadoIp class Axi4WiderMemory( diff --git a/package-vivado-ips/src/xilinx/ClockingWizard.scala b/package-vivado-ips/src/xilinx/ClockingWizard.scala index f4a2478..901681b 100644 --- a/package-vivado-ips/src/xilinx/ClockingWizard.scala +++ b/package-vivado-ips/src/xilinx/ClockingWizard.scala @@ -1,5 +1,8 @@ +package vivadoips + import chisel3.{BlackBox, _} import chisel3.util._ +import builder.addVivadoIp class ClockingWizard( diff --git a/package-vivado-ips/src/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala index e0e0543..fe2e47a 100644 --- a/package-vivado-ips/src/xilinx/FloatingPoint.scala +++ b/package-vivado-ips/src/xilinx/FloatingPoint.scala @@ -1,5 +1,8 @@ +package vivadoips + import chisel3._ import chisel3.util._ +import builder.addVivadoIp class FloatingPoint( diff --git a/package-vivado-ips/src/xilinx/IOBuffer.scala b/package-vivado-ips/src/xilinx/IOBuffer.scala index bbb631d..42c025c 100644 --- a/package-vivado-ips/src/xilinx/IOBuffer.scala +++ b/package-vivado-ips/src/xilinx/IOBuffer.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ import chisel3.experimental.Analog diff --git a/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala index dbbddba..c745974 100644 --- a/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala +++ b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala @@ -1,3 +1,5 @@ +package vivadoips + import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4Constants, Axi4LiteBundle, Axi4StreamBundle, AxResponse, AxSize, AxBurst} From c2a1e5c16cc08aacf48ec3b8a82a584e5b39df26 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 09:55:31 -0700 Subject: [PATCH 13/18] UPDATE: rename CI --- .github/workflows/{build-example.yaml => build-verilog.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename .github/workflows/{build-example.yaml => build-verilog.yaml} (93%) diff --git a/.github/workflows/build-example.yaml b/.github/workflows/build-verilog.yaml similarity index 93% rename from .github/workflows/build-example.yaml rename to .github/workflows/build-verilog.yaml index d3e5f49..a83ffde 100644 --- a/.github/workflows/build-example.yaml +++ b/.github/workflows/build-verilog.yaml @@ -1,4 +1,4 @@ -name: Build Example +name: Build Verilog on: push: From 5023c54edf90a7391db8d7ced74d0cffea475d73 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 10:00:09 -0700 Subject: [PATCH 14/18] FIX: CI --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9adbd5f..003074f 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,8 @@ BUILD_DIR = ./generated-src PACKAGE ?= vivado-ips -MODULE ?= MinimalArty100T -CONFIG ?= MinimalArty100TConfig +MODULE ?= vivadoips.MinimalArty100T +CONFIG ?= vivadoips.MinimalArty100TConfig MILL_PATH ?= ./toolchains/mill From 6ab674a30c17526f3345e7cde25686bddb8b44f1 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 10:09:06 -0700 Subject: [PATCH 15/18] ADD: config classes --- .github/workflows/run-vivado-flow.yaml | 4 +- Makefile | 11 +++--- builder/src/Builder.scala | 22 +++++------ ...Runner.scala => MlpPolicyRunnerBase.scala} | 38 ++++++++++++------- package-delta-soc/src/TestTiles.scala | 4 +- package-delta-soc/src/Tile.scala | 16 ++++++-- package-delta-soc/src/core/ALU.scala | 10 ++--- package-delta-soc/src/core/CSR.scala | 34 ++++++++--------- package-delta-soc/src/core/Core.scala | 26 ++++++++----- package-delta-soc/src/core/LoadStore.scala | 10 ++--- .../src/core/SimdFloatingPoint.scala | 33 +++++++++------- .../MemorySubsystem.scala | 0 .../src/designs/MlpPolicyRunner.scala | 16 ++++++++ .../src/xilinx/Axi4LiteGpio.scala | 13 +++++-- .../src/xilinx/Axi4LiteStreamDataFifo.scala | 10 ++--- .../src/xilinx/Axi4LiteTimer.scala | 16 ++++++-- .../src/xilinx/Axi4LiteUartLite.scala | 15 +++++--- .../src/xilinx/FloatingPoint.scala | 23 +++++++++-- package-vivado-ips/src/xilinx/IOBuffer.scala | 1 + 19 files changed, 194 insertions(+), 108 deletions(-) rename package-delta-soc/src/{configs/MlpPolicyRunner.scala => MlpPolicyRunnerBase.scala} (82%) rename package-delta-soc/src/{configs => designs}/MemorySubsystem.scala (100%) create mode 100644 package-delta-soc/src/designs/MlpPolicyRunner.scala diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml index 4600782..2a82c11 100644 --- a/.github/workflows/run-vivado-flow.yaml +++ b/.github/workflows/run-vivado-flow.yaml @@ -17,9 +17,9 @@ jobs: - name: Build MemorySubsystem run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project PACKAGE=delta-soc MODULE=delta.MemorySubsystem + make project PACKAGE=delta-soc DESIGN=delta.MemorySubsystem - name: Build MlpPolicyRunner run: | source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh - make project PACKAGE=delta-soc MODULE=delta.MlpPolicyRunner + make project PACKAGE=delta-soc DESIGN=delta.MlpPolicyRunner diff --git a/Makefile b/Makefile index 003074f..f823c74 100644 --- a/Makefile +++ b/Makefile @@ -1,20 +1,19 @@ BUILD_DIR = ./generated-src PACKAGE ?= vivado-ips -MODULE ?= vivadoips.MinimalArty100T -CONFIG ?= vivadoips.MinimalArty100TConfig +DESIGN ?= vivadoips.MinimalArty100T MILL_PATH ?= ./toolchains/mill verilog: mkdir -p $(BUILD_DIR) - $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildVerilog --target-dir $(BUILD_DIR) --module-name $(MODULE) - + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildVerilog --target-dir $(BUILD_DIR) --design-name $(DESIGN) + project: verilog - $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildProject --target-dir $(BUILD_DIR) --module-name $(MODULE) + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildProject --target-dir $(BUILD_DIR) --design-name $(DESIGN) bitstream: project - $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildBitstream --target-dir $(BUILD_DIR) --module-name $(MODULE) + $(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildBitstream --target-dir $(BUILD_DIR) --design-name $(DESIGN) test: $(MILL_PATH) -i package-$(PACKAGE).Test diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index fb0df2d..52b790e 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -90,9 +90,9 @@ object _parseModuleName { } args.sliding(2).zipWithIndex.collectFirst { - case (Array("--module-name", name), i) => (name, args.take(i) ++ args.drop(i + 2)) + case (Array("--design-name", name), i) => (name, args.take(i) ++ args.drop(i + 2)) }.getOrElse { - println("Error: Please provide the module name with --module-name flag") + println("Error: Please provide the design name with --design-name flag") System.exit(1) ("", Array.empty[String]) // This is never reached but needed for type inference } @@ -113,14 +113,14 @@ object buildVerilog extends App { new File(BuilderConfig.vivadoProjectDir).mkdirs() new File(BuilderConfig.vivadoTclDir).mkdirs() - val (moduleName, remainingArgs) = _parseModuleName(args) + val (designName, remainingArgs) = _parseModuleName(args) - val moduleClass = () => { - val module = Class.forName(moduleName) + val designClass = () => { + val design = Class.forName(designName) .getDeclaredConstructor() .newInstance() .asInstanceOf[chisel3.RawModule] - module + design } val chiselOpts = remainingArgs ++ Array("--split-verilog") val firtoolOpts = Array( @@ -129,14 +129,14 @@ object buildVerilog extends App { ) ChiselStage.emitSystemVerilogFile( - gen=moduleClass(), + gen=designClass(), args=chiselOpts, firtoolOpts=firtoolOpts ) } object buildProject extends App { - val (moduleName, remainingArgs) = _parseModuleName(args) + val (designName, remainingArgs) = _parseModuleName(args) new File(BuilderConfig.vivadoProjectDir).mkdirs() new File(BuilderConfig.vivadoTclDir).mkdirs() @@ -201,7 +201,7 @@ object buildProject extends App { runTcl.println("}") } - runTcl.println(s"set_property top ${moduleName} [current_fileset]") + runTcl.println(s"set_property top ${designName} [current_fileset]") /* create Vivado IPs */ runTcl.println("update_ip_catalog") @@ -219,7 +219,7 @@ object buildProject extends App { runTcl.println(s"update_compile_order -fileset sources_1") runTcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]") runTcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]") - runTcl.println(s"set_property top ${moduleName}Testbench [get_filesets sim_1]") + runTcl.println(s"set_property top ${designName}Testbench [get_filesets sim_1]") // run_tcl.println(s"set_property top_lib xil_defaultlib [get_filesets sim_1]") @@ -232,7 +232,7 @@ object buildProject extends App { } object GenerateBitstream extends App { - val (module_name, remaining_args) = _parseModuleName(args) + val (designName, remainingArgs) = _parseModuleName(args) // { diff --git a/package-delta-soc/src/configs/MlpPolicyRunner.scala b/package-delta-soc/src/MlpPolicyRunnerBase.scala similarity index 82% rename from package-delta-soc/src/configs/MlpPolicyRunner.scala rename to package-delta-soc/src/MlpPolicyRunnerBase.scala index 4ebd9a7..f798b01 100644 --- a/package-delta-soc/src/configs/MlpPolicyRunner.scala +++ b/package-delta-soc/src/MlpPolicyRunnerBase.scala @@ -3,7 +3,22 @@ package delta import chisel3._ import chisel3.util._ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} -import vivadoips.{Axi4Crossbar, Axi4DataWidthConverter, Axi4LiteTimer, Axi4LiteCrossbar, Axi4SpiFlash, Axi4QuadSpiFlash, Axi4LiteUartLite, Axi4LiteGpio, IOBUF, ClockingWizard, SyncReset, Arty100TIO} +import vivadoips.{ + Arty100TIO, + Axi4Crossbar, + Axi4DataWidthConverter, + Axi4LiteCrossbar, + Axi4LiteTimer, + Axi4LiteTimerConfig, + Axi4LiteUartLite, + Axi4LiteUartLiteConfig, + Axi4LiteGpio, + Axi4QuadSpiFlash, + Axi4SpiFlash, + ClockingWizard, + IOBUF, + SyncReset, +} import builder.{addConstraintResource, addSimulationResource} @@ -22,7 +37,12 @@ import builder.{addConstraintResource, addSimulationResource} * 0x0800_0000 - 0x0800_3FFF: scratchpad (16 kB) * */ -class MlpPolicyRunner extends RawModule { + +case class SoCConfig( + TileConfig: TileConfig = new TileConfig(sbusFrequency=50), +) + +class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { val io = IO(new Arty100TIO()) val systemClockFrequency = 50 @@ -52,7 +72,7 @@ class MlpPolicyRunner extends RawModule { withClockAndReset(clock, reset) { val reset_vector = RegInit(0x0800_0000.U(32.W)) - val tile = Module(new Tile(sbusFrequency=systemClockFrequency)) + val tile = Module(new Tile(config.TileConfig)) tile.io.reset_vector := reset_vector @@ -79,8 +99,8 @@ class MlpPolicyRunner extends RawModule { // val spi = Module(new Axi4SpiFlash()) val gpio = Module(new Axi4LiteGpio()) - val uart = Module(new Axi4LiteUartLite(axiClockFrequency=systemClockFrequency)) - val timer = Module(new Axi4LiteTimer()) + val uart = Module(new Axi4LiteUartLite(Axi4LiteUartLiteConfig(axiClockFrequency=systemClockFrequency))) + val timer = Module(new Axi4LiteTimer(Axi4LiteTimerConfig(timerCounterWidth=32))) pbus_crossbar.io.s_axi(0).connectFromAxi4(tile.io.pbus) @@ -173,12 +193,4 @@ class MlpPolicyRunner extends RawModule { tile.io.debug.sysresp3 := 0.U(32.W) } - - addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") - - addSimulationResource("package-delta-soc/test/MlpPolicyRunnerTestbench.sv") - addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv") - addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") - addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv") - addSimulationResource("package-delta-soc/resources/verilog/Ram.v") } diff --git a/package-delta-soc/src/TestTiles.scala b/package-delta-soc/src/TestTiles.scala index e7e6af5..7516dfd 100644 --- a/package-delta-soc/src/TestTiles.scala +++ b/package-delta-soc/src/TestTiles.scala @@ -12,7 +12,7 @@ class EECS151Tile extends Module { val debug = new DebugIO() }) - val core = Module(new Core(nVectors=1)) + val core = Module(new Core(CoreConfig(VLEN=32, ELEN=32))) // instruction memory must be a synchronous 1 cycle read delay memory val itim = Module(new Axi4MemoryWithLatency( @@ -49,7 +49,7 @@ class EECS252Tile extends Module { val debug = new DebugIO() }) - val core = Module(new Core(nVectors=2)) + val core = Module(new Core(CoreConfig(VLEN=64, ELEN=32))) val xbar = Module(new Axi4Crossbar( 2, 1, diff --git a/package-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala index b582817..a5ebc73 100644 --- a/package-delta-soc/src/Tile.scala +++ b/package-delta-soc/src/Tile.scala @@ -6,8 +6,13 @@ import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle} import vivadoips.{Axi4Crossbar, Axi4BlockMemory, Axi4DataWidthConverter} +case class TileConfig( + CoreConfig: CoreConfig = new CoreConfig(), + sbusFrequency: Int = 20, +) + class Tile( - val sbusFrequency: Int = 20, + val config: TileConfig = TileConfig() ) extends Module { val io = IO(new Bundle { val reset_vector = Input(UInt(32.W)) @@ -20,11 +25,14 @@ class Tile( dontTouch(io.reset_vector) dontTouch(io.debug) - val busWidth = 64 + val busWidth = config.CoreConfig.VLEN val core = Module(new Core( - nVectors=busWidth/32, - pipelineStages=3, + CoreConfig( + VLEN=busWidth, + ELEN=config.CoreConfig.ELEN, + pipelineStages=config.CoreConfig.pipelineStages, + ) )) val itim = Module(new Axi4Memory( diff --git a/package-delta-soc/src/core/ALU.scala b/package-delta-soc/src/core/ALU.scala index af9ecdf..72d3ae2 100644 --- a/package-delta-soc/src/core/ALU.scala +++ b/package-delta-soc/src/core/ALU.scala @@ -7,13 +7,13 @@ import Instructions._ import ScalarControlConstants._ -class ALU extends Module { +class ALU(val XLEN: Int = 32) extends Module { val io = IO(new Bundle { - val op1 = Input(UInt(32.W)) - val op2 = Input(UInt(32.W)) + val op1 = Input(UInt(XLEN.W)) + val op2 = Input(UInt(XLEN.W)) val func = Input(UInt(ALU_X.getWidth.W)) - val out = Output(UInt(32.W)) + val out = Output(UInt(XLEN.W)) }) @@ -27,7 +27,7 @@ class ALU extends Module { (io.func === ALU_XOR) -> (io.op1 ^ io.op2).asUInt, (io.func === ALU_SLT) -> (io.op1.asSInt < io.op2.asSInt).asUInt, (io.func === ALU_SLTU) -> (io.op1 < io.op2).asUInt, - (io.func === ALU_SLL) -> ((io.op1 << alu_shamt)(31, 0)).asUInt, + (io.func === ALU_SLL) -> ((io.op1 << alu_shamt)(XLEN-1, 0)).asUInt, (io.func === ALU_SRA) -> (io.op1.asSInt >> alu_shamt).asUInt, (io.func === ALU_SRL) -> (io.op1 >> alu_shamt).asUInt, (io.func === ALU_COPY) -> (io.op1).asUInt diff --git a/package-delta-soc/src/core/CSR.scala b/package-delta-soc/src/core/CSR.scala index 14d68a5..1f1c0e3 100644 --- a/package-delta-soc/src/core/CSR.scala +++ b/package-delta-soc/src/core/CSR.scala @@ -39,35 +39,35 @@ object CsrAddress { val MHARTID = 0xF14.U } -class CSR extends Module { +class CSR(val XLEN: Int = 32) extends Module { val io = IO(new Bundle { val addr = Input(UInt(12.W)) val command = Input(UInt(3.W)) - val in_data = Input(UInt(32.W)) - val out_data = Output(UInt(32.W)) + val in_data = Input(UInt(XLEN.W)) + val out_data = Output(UInt(XLEN.W)) val retire = Input(Bool()) // debug interface val debug = new Bundle { - val syscall0 = Output(UInt(32.W)) - val syscall1 = Output(UInt(32.W)) - val syscall2 = Output(UInt(32.W)) - val syscall3 = Output(UInt(32.W)) - val sysresp0 = Input(UInt(32.W)) - val sysresp1 = Input(UInt(32.W)) - val sysresp2 = Input(UInt(32.W)) - val sysresp3 = Input(UInt(32.W)) + val syscall0 = Output(UInt(XLEN.W)) + val syscall1 = Output(UInt(XLEN.W)) + val syscall2 = Output(UInt(XLEN.W)) + val syscall3 = Output(UInt(XLEN.W)) + val sysresp0 = Input(UInt(XLEN.W)) + val sysresp1 = Input(UInt(XLEN.W)) + val sysresp2 = Input(UInt(XLEN.W)) + val sysresp3 = Input(UInt(XLEN.W)) } }) - val reg_csr_syscall0 = RegInit(0.U(32.W)) - val reg_csr_syscall1 = RegInit(0.U(32.W)) - val reg_csr_syscall2 = RegInit(0.U(32.W)) - val reg_csr_syscall3 = RegInit(0.U(32.W)) - val reg_csr_mcycle = RegInit(0.U(32.W)) - val reg_csr_minstret = RegInit(0.U(32.W)) + val reg_csr_syscall0 = RegInit(0.U(XLEN.W)) + val reg_csr_syscall1 = RegInit(0.U(XLEN.W)) + val reg_csr_syscall2 = RegInit(0.U(XLEN.W)) + val reg_csr_syscall3 = RegInit(0.U(XLEN.W)) + val reg_csr_mcycle = RegInit(0.U(XLEN.W)) + val reg_csr_minstret = RegInit(0.U(XLEN.W)) switch (io.addr) { diff --git a/package-delta-soc/src/core/Core.scala b/package-delta-soc/src/core/Core.scala index 3e8b51f..e92971d 100644 --- a/package-delta-soc/src/core/Core.scala +++ b/package-delta-soc/src/core/Core.scala @@ -32,18 +32,26 @@ class DebugIO extends Bundle() { } -class Core( - nVectors: Int = 1, +case class CoreConfig( + XLEN: Int = 32, + ELEN: Int = 32, + VLEN: Int = 64, pipelineStages: Int = 1, +) + +class Core( + val config: CoreConfig = CoreConfig() ) extends Module { val io = IO(new Bundle { val reset_vector = Input(UInt(32.W)) val imem = new Axi4LiteBundle() val dmem = new Axi4Bundle() - val vdmem = new Axi4Bundle(params=Axi4Params(dataWidth=nVectors*32)) + val vdmem = new Axi4Bundle(params=Axi4Params(dataWidth=config.VLEN)) val debug = new DebugIO() }) + + val numVectors = config.VLEN / config.ELEN val exception = Wire(Bool()) exception := false.B @@ -72,9 +80,9 @@ class Core( val if_exception_target = Wire(UInt(32.W)) - val ex_wb_data = Wire(UInt(32.W)) + val ex_wb_data = Wire(UInt(config.XLEN.W)) - val ex_vwb_data = Wire(Vec(nVectors, UInt(32.W))) + val ex_vwb_data = Wire(Vec(numVectors, UInt(config.ELEN.W))) val ifu = Module(new InstructionFetch()) @@ -236,7 +244,7 @@ class Core( // Vector Register File - val vregfile = Mem(32, Vec(nVectors, UInt(32.W))) + val vregfile = Mem(32, Vec(numVectors, UInt(config.ELEN.W))) when(ex_vwb_en) { vregfile(rd_addr) := ex_vwb_data @@ -247,7 +255,7 @@ class Core( val vrd_data = vregfile(rd_addr) - val valu = Module(new SimdFloatingPoint(nVectors=nVectors, pipelineStages=pipelineStages)) + val valu = Module(new SimdFloatingPoint(ELEN=config.ELEN, VLEN=config.VLEN, pipelineStages=config.pipelineStages)) // result = a * b + c valu.io.func := ctrl.valu_func @@ -266,7 +274,7 @@ class Core( lsu.io.dmem <> io.dmem - val vlsu = Module(new SimdLoadStore(nVectors=nVectors)) + val vlsu = Module(new SimdLoadStore(nVectors=numVectors)) vlsu.io.mem_func := Mux(ifu.io.ex.valid, ctrl.vmem_func, M_X) vlsu.io.strided := ctrl.vmem_stride @@ -296,7 +304,7 @@ class Core( (ctrl.wb_sel === WB_CSR) -> csr.io.out_data )) - ex_vwb_data := MuxCase(VecInit.fill(nVectors)(0.U(32.W)), Seq( + ex_vwb_data := MuxCase(VecInit.fill(numVectors)(0.U(config.ELEN.W)), Seq( (ctrl.vwb_sel === WB_ALU) -> valu.io.out, (ctrl.vwb_sel === WB_MEM) -> vlsu.io.rdata, )) diff --git a/package-delta-soc/src/core/LoadStore.scala b/package-delta-soc/src/core/LoadStore.scala index cb98da0..be985ec 100644 --- a/package-delta-soc/src/core/LoadStore.scala +++ b/package-delta-soc/src/core/LoadStore.scala @@ -8,23 +8,23 @@ import Instructions._ import ScalarControlConstants._ -class LoadStore extends Module { +class LoadStore(val XLEN: Int = 32) extends Module { val io = IO(new Bundle { val mem_func = Input(UInt(M_X.getWidth.W)) val ctl_dmem_mask_sel = Input(UInt(MSK_X.getWidth.W)) val ctl_dmem_signed = Input(Bool()) - val addr = Input(UInt(32.W)) - val wdata = Input(UInt(32.W)) - val rdata = Output(UInt(32.W)) + val addr = Input(UInt(XLEN.W)) + val wdata = Input(UInt(XLEN.W)) + val rdata = Output(UInt(XLEN.W)) val busy = Output(Bool()) val dmem = new Axi4Bundle() }) - + assert(XLEN == 32, "Currently only 32-bit (XLEN = 32) is supported") val reg_aw_pending = RegInit(false.B) val reg_w_pending = RegInit(false.B) diff --git a/package-delta-soc/src/core/SimdFloatingPoint.scala b/package-delta-soc/src/core/SimdFloatingPoint.scala index 3b18645..0cac82c 100644 --- a/package-delta-soc/src/core/SimdFloatingPoint.scala +++ b/package-delta-soc/src/core/SimdFloatingPoint.scala @@ -2,27 +2,34 @@ package delta import chisel3._ import chisel3.util._ -import vivadoips.FloatingPoint +import vivadoips.{FloatingPoint, FloatingPointConfig} import Instructions._ import SimdControlConstants._ class SimdFloatingPoint( - nVectors: Int = 1, + val ELEN: Int = 32, + val VLEN: Int = 64, pipelineStages: Int = 1, -) extends Module { + ) extends Module { + + val numVectors = VLEN / ELEN + val io = IO(new Bundle { - val op1 = Input(Vec(nVectors, UInt(32.W))) - val op2 = Input(Vec(nVectors, UInt(32.W))) - val op3 = Input(Vec(nVectors, UInt(32.W))) + val op1 = Input(Vec(numVectors, UInt(ELEN.W))) + val op2 = Input(Vec(numVectors, UInt(ELEN.W))) + val op3 = Input(Vec(numVectors, UInt(ELEN.W))) val func = Input(UInt(SIMD_X.getWidth.W)) - val out = Output(Vec(nVectors, UInt(32.W))) + val out = Output(Vec(numVectors, UInt(ELEN.W))) val busy = Output(Bool()) }) - val fmacc = Array.fill(nVectors)(Module(new FloatingPoint(pipelineStages=pipelineStages))) + assert(ELEN == 32, "Currently only 32-bit (ELEN = 32) is supported") + assert(VLEN == 64 || VLEN == 128 || VLEN == 256, "Currently only 64-bit, 128-bit and 256-bit (VLEN = {64, 128, 256}) is supported") + + val fmacc = Array.fill(numVectors)(Module(new FloatingPoint(FloatingPointConfig(pipelineStages=pipelineStages)))) val one = 0x3F800000.U(32.W) val zero = 0x00000000.U(32.W) @@ -45,16 +52,16 @@ class SimdFloatingPoint( // EX 2 stage pipeline registers - val ex2_reg_op_a = Reg(Vec(nVectors, UInt(32.W))) - val ex2_reg_op_b = Reg(Vec(nVectors, UInt(32.W))) - val ex2_reg_op_c = Reg(Vec(nVectors, UInt(32.W))) + val ex2_reg_op_a = Reg(Vec(numVectors, UInt(ELEN.W))) + val ex2_reg_op_b = Reg(Vec(numVectors, UInt(ELEN.W))) + val ex2_reg_op_c = Reg(Vec(numVectors, UInt(ELEN.W))) val ex2_reg_op_rs2 = RegNext(io.op2) val ex2_reg_func = RegNext(io.func) val ex2_reg_valid = RegNext(input_valid) - for (i <- 0 until nVectors) { + for (i <- 0 until numVectors) { when(io.func === SIMD_ADD) { ex2_reg_op_a(i) := io.op1(i) ex2_reg_op_b(i) := one @@ -81,7 +88,7 @@ class SimdFloatingPoint( val ex2_op2_positive = ex2_reg_op_rs2.map(x => x(31) === 0.U) - for (i <- 0 until nVectors) { + for (i <- 0 until numVectors) { fmacc(i).io.a.valid := ex2_reg_valid fmacc(i).io.b.valid := ex2_reg_valid fmacc(i).io.c.valid := ex2_reg_valid diff --git a/package-delta-soc/src/configs/MemorySubsystem.scala b/package-delta-soc/src/designs/MemorySubsystem.scala similarity index 100% rename from package-delta-soc/src/configs/MemorySubsystem.scala rename to package-delta-soc/src/designs/MemorySubsystem.scala diff --git a/package-delta-soc/src/designs/MlpPolicyRunner.scala b/package-delta-soc/src/designs/MlpPolicyRunner.scala new file mode 100644 index 0000000..45294cc --- /dev/null +++ b/package-delta-soc/src/designs/MlpPolicyRunner.scala @@ -0,0 +1,16 @@ +package delta + +import chisel3._ +import chisel3.util._ +import builder.{addConstraintResource, addSimulationResource} + + +class MlpPolicyRunner extends MlpPolicyRunnerBase(new SoCConfig()) { + addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") + + addSimulationResource("package-delta-soc/test/MlpPolicyRunnerTestbench.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv") + addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv") + addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv") + addSimulationResource("package-delta-soc/resources/verilog/Ram.v") +} diff --git a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala index fb7f946..0ece24b 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala @@ -6,7 +6,12 @@ import amba.{Axi4Params, Axi4LiteBundle} import builder.addVivadoIp -class Axi4LiteGpio extends Module { +case class Axi4LiteGpioConfig( +) + +class Axi4LiteGpio( + val config: Axi4LiteGpioConfig = Axi4LiteGpioConfig() +) extends Module { val io = IO(new Bundle { val s_axi = Flipped(new Axi4LiteBundle()) val gpio_io_i = Input(UInt(32.W)) @@ -14,7 +19,7 @@ class Axi4LiteGpio extends Module { val gpio_io_t = Output(UInt(32.W)) }) - val blackbox = Module(new Axi4LiteGpioBlackbox()) + val blackbox = Module(new Axi4LiteGpioBlackbox(config)) blackbox.io.s_axi_aclk := clock blackbox.io.s_axi_aresetn := ~reset.asBool @@ -25,7 +30,9 @@ class Axi4LiteGpio extends Module { io.gpio_io_t := blackbox.io.gpio_io_t } -class Axi4LiteGpioBlackbox extends BlackBox { +class Axi4LiteGpioBlackbox( + val config: Axi4LiteGpioConfig = Axi4LiteGpioConfig() +) extends BlackBox { val io = IO(new Bundle { val s_axi_aclk = Input(Clock()) val s_axi_aresetn = Input(Bool()) diff --git a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala index 76e9fe9..ddecf32 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala @@ -6,13 +6,13 @@ import amba.{Axi4Params, Axi4StreamBundle} import builder.addVivadoIp -class Axi4LiteStreamDataFifo(width: Int) extends Module { +class Axi4LiteStreamDataFifo(params: Axi4Params = Axi4Params()) extends Module { val io = IO(new Bundle { val s_axis = Flipped(new Axi4StreamBundle()) val m_axis = new Axi4StreamBundle() }) - val blackbox = Module(new Axi4LiteStreamDataFifoBlackbox(width)) + val blackbox = Module(new Axi4LiteStreamDataFifoBlackbox(params)) blackbox.io.s_axis_aclk := clock blackbox.io.s_axis_aresetn := ~reset.asBool @@ -20,12 +20,12 @@ class Axi4LiteStreamDataFifo(width: Int) extends Module { blackbox.io.m_axis.flipConnect(io.m_axis) } -class Axi4LiteStreamDataFifoBlackbox(width: Int) extends BlackBox { +class Axi4LiteStreamDataFifoBlackbox(params: Axi4Params = Axi4Params()) extends BlackBox { val io = IO(new Bundle { val s_axis_aclk = Input(Clock()) val s_axis_aresetn = Input(Reset()) - val s_axis = Flipped(new Axi4StreamBlackboxBundle()) - val m_axis = new Axi4StreamBlackboxBundle() + val s_axis = Flipped(new Axi4StreamBlackboxBundle(params)) + val m_axis = new Axi4StreamBlackboxBundle(params) }) val ipName = "AXIStreamDataFifo" diff --git a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala index b7298fb..efd26ec 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala @@ -6,7 +6,13 @@ import amba.{Axi4Params, Axi4LiteBundle} import builder.addVivadoIp -class Axi4LiteTimer extends Module { +case class Axi4LiteTimerConfig( + timerCounterWidth: Int = 32, +) + +class Axi4LiteTimer( + val config: Axi4LiteTimerConfig = Axi4LiteTimerConfig() +) extends Module { val io = IO(new Bundle { val s_axi = Flipped(new Axi4LiteBundle()) val capturetrig0 = Input(Bool()) @@ -18,7 +24,7 @@ class Axi4LiteTimer extends Module { val freeze = Input(Bool()) }) - val blackbox = Module(new Axi4LiteTimerBlackbox()) + val blackbox = Module(new Axi4LiteTimerBlackbox(config)) blackbox.io.s_axi_aclk := clock blackbox.io.s_axi_aresetn := ~reset.asBool @@ -32,7 +38,9 @@ class Axi4LiteTimer extends Module { io.interrupt := blackbox.io.interrupt } -class Axi4LiteTimerBlackbox extends BlackBox { +class Axi4LiteTimerBlackbox( + val config: Axi4LiteTimerConfig = Axi4LiteTimerConfig() +) extends BlackBox { val io = IO(new Bundle { val s_axi_aclk = Input(Clock()) val s_axi_aresetn = Input(Bool()) @@ -55,7 +63,7 @@ class Axi4LiteTimerBlackbox extends BlackBox { moduleName=ipName, extra = s""" set_property -dict [list \\ - CONFIG.COUNT_WIDTH {32} \\ + CONFIG.COUNT_WIDTH {${config.timerCounterWidth}} \\ ] [get_ips ${ipName}] """ ) diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala index 99046fc..d57c830 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala @@ -6,8 +6,13 @@ import amba.{Axi4Params, Axi4LiteBundle} import builder.addVivadoIp +case class Axi4LiteUartLiteConfig( + axiClockFrequency: Int = 100, + baudRate: Int = 115200, +) + class Axi4LiteUartLite( - val axiClockFrequency: Int = 100, + val config: Axi4LiteUartLiteConfig = Axi4LiteUartLiteConfig() ) extends Module { val io = IO(new Bundle { val s_axi = Flipped(new Axi4LiteBundle()) @@ -15,7 +20,7 @@ class Axi4LiteUartLite( val tx = Output(Bool()) }) - val blackbox = Module(new Axi4LiteUartLiteBlackbox(axiClockFrequency=axiClockFrequency)) + val blackbox = Module(new Axi4LiteUartLiteBlackbox(config)) blackbox.io.s_axi_aclk := clock blackbox.io.s_axi_aresetn := ~reset.asBool @@ -25,7 +30,7 @@ class Axi4LiteUartLite( } class Axi4LiteUartLiteBlackbox( - val axiClockFrequency: Int = 100, + val config: Axi4LiteUartLiteConfig = Axi4LiteUartLiteConfig() ) extends BlackBox { val io = IO(new Bundle { val s_axi_aclk = Input(Clock()) @@ -44,8 +49,8 @@ class Axi4LiteUartLiteBlackbox( moduleName=ipName, extra = s""" set_property -dict [list \\ - CONFIG.C_BAUDRATE {115200} \\ - CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {${axiClockFrequency}} \\ + CONFIG.C_BAUDRATE {${config.baudRate}} \\ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {${config.axiClockFrequency}} \\ ] [get_ips ${ipName}] """ ) diff --git a/package-vivado-ips/src/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala index fe2e47a..522bd06 100644 --- a/package-vivado-ips/src/xilinx/FloatingPoint.scala +++ b/package-vivado-ips/src/xilinx/FloatingPoint.scala @@ -5,8 +5,23 @@ import chisel3.util._ import builder.addVivadoIp +/** + * Floating Point Multiplier-Adder + * + * @param pipelineStages + */ +case class FloatingPointConfig( + /** Number of pipeline stages */ + pipelineStages: Int = 1, +) + +/** + * Floating Point Multiplier-Adder + * + * @param config + */ class FloatingPoint( - val pipelineStages: Int = 1 + val config: FloatingPointConfig = FloatingPointConfig() ) extends Module { val io = IO(new Bundle { val a = Flipped(Valid(UInt(32.W))) @@ -15,7 +30,7 @@ class FloatingPoint( val result = Valid(UInt(32.W)) }) - val blackbox = Module(new FloatingPointBlackbox(pipelineStages=pipelineStages)) + val blackbox = Module(new FloatingPointBlackbox(config)) blackbox.io.aclk := clock blackbox.io.s_axis_a_tvalid := io.a.valid @@ -29,7 +44,7 @@ class FloatingPoint( } class FloatingPointBlackbox( - val pipelineStages: Int = 1 + val config: FloatingPointConfig = FloatingPointConfig() ) extends BlackBox { val io = IO(new Bundle { val aclk = Input(Clock()) @@ -56,7 +71,7 @@ set_property -dict [list \\ CONFIG.Add_Sub_Value {Add} \\ CONFIG.C_A_Exponent_Width {8} \\ CONFIG.C_A_Fraction_Width {24} \\ - CONFIG.C_Latency {${pipelineStages}} \\ + CONFIG.C_Latency {${config.pipelineStages}} \\ CONFIG.C_Mult_Usage {Full_Usage} \\ CONFIG.C_Optimization {Speed_Optimized} \\ CONFIG.C_Rate {1} \\ diff --git a/package-vivado-ips/src/xilinx/IOBuffer.scala b/package-vivado-ips/src/xilinx/IOBuffer.scala index 42c025c..3845e05 100644 --- a/package-vivado-ips/src/xilinx/IOBuffer.scala +++ b/package-vivado-ips/src/xilinx/IOBuffer.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.Analog + class IBUFG extends BlackBox { val io = IO(new Bundle { val I = Input(Bool()) From f4ddee2cca3799d0293eba45febf0060ab1cc974 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 13:12:54 -0700 Subject: [PATCH 16/18] FIX: project generation --- builder/src/Builder.scala | 35 ++- .../src/MlpPolicyRunnerBase.scala | 10 +- package-delta-soc/src/Tile.scala | 8 +- .../src/designs/MlpPolicyRunner.scala | 14 +- package-delta-soc/src/memory/Axi4Memory.scala | 2 +- .../constraints/Arty-A7-100-Master.xdc | 226 ++++++++++++++++++ .../src/xilinx/Axi4QuadSpiFlash.scala | 2 +- 7 files changed, 272 insertions(+), 25 deletions(-) diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 52b790e..2568471 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -49,6 +49,10 @@ object addVivadoTclScript { def apply(path: String, content: String): Unit = { println(s"adding Vivado TCL script: $path") val file = new File(BuilderConfig.vivadoTclDir + "/" + path) + + // ensure the directory exists + file.getParentFile.mkdirs() + val writer = new PrintWriter(new FileWriter(file)) writer.println(content) writer.close() @@ -64,7 +68,7 @@ object addVivadoIp { moduleName: String, extra: String, ): Unit = { - addVivadoTclScript(s"create_ip_${moduleName.toLowerCase()}.tcl", { + addVivadoTclScript(s"ip/create_ip_${moduleName.toLowerCase()}.tcl", { s""" create_ip -name ${name} -vendor ${vendor} -library ${library} -version ${version} -module_name ${moduleName} generate_target {instantiation_template} [get_ips ${moduleName}] @@ -153,12 +157,17 @@ object buildProject extends App { // val fpgaPart = "xc7z020clg484-1" // val boardPart = "digilentinc.com:zedboard:part0:1.1" - val chiselGeneratedSources = scala.io.Source.fromFile(new File(BuilderConfig.chiselGeneratedFilelist)) - .getLines() - .map(_.trim) - .filter(_.nonEmpty) - .map(line => s"generated-src/${line}") - .toList + // HACK: the blackboxed sources are not included in the filelist.f, so we need to instead scan for the entire generated-src directory + // val chiselGeneratedSources = scala.io.Source.fromFile(new File(BuilderConfig.chiselGeneratedFilelist)) + // .getLines() + // .map(_.trim) + // .filter(_.nonEmpty) + // .map(line => s"generated-src/${line}") + // .toList + val chiselGeneratedSources = new File("generated-src").listFiles(new FileFilter { + def accept(file: File): Boolean = file.isFile || file.isDirectory && !file.getName.endsWith(".f") + }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath)) + val simulationSources = scala.io.Source.fromFile(new File(BuilderConfig.simulationFilelist)) .getLines() .map(_.trim) @@ -201,13 +210,14 @@ object buildProject extends App { runTcl.println("}") } - runTcl.println(s"set_property top ${designName} [current_fileset]") + val designClassName = designName.split("\\.").last + runTcl.println(s"set_property top ${designClassName} [current_fileset]") /* create Vivado IPs */ runTcl.println("update_ip_catalog") - val create_ip_files = new File(BuilderConfig.vivadoTclDir).listFiles(new FileFilter { - def accept(file: File): Boolean = file.isFile && file.getName != "create_project.tcl" + val create_ip_files = new File(BuilderConfig.vivadoTclDir + "/ip").listFiles(new FileFilter { + def accept(file: File): Boolean = file.isFile }).map(_.getAbsolutePath) create_ip_files.foreach(file => { @@ -219,9 +229,10 @@ object buildProject extends App { runTcl.println(s"update_compile_order -fileset sources_1") runTcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]") runTcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]") - runTcl.println(s"set_property top ${designName}Testbench [get_filesets sim_1]") + runTcl.println(s"set_property top ${designClassName}Testbench [get_filesets sim_1]") // run_tcl.println(s"set_property top_lib xil_defaultlib [get_filesets sim_1]") + runTcl.println(s"close_project") runTcl.close() runTcl.flush() @@ -231,7 +242,7 @@ object buildProject extends App { s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/create_project.tcl".! } -object GenerateBitstream extends App { +object buildBitstream extends App { val (designName, remainingArgs) = _parseModuleName(args) diff --git a/package-delta-soc/src/MlpPolicyRunnerBase.scala b/package-delta-soc/src/MlpPolicyRunnerBase.scala index f798b01..d807603 100644 --- a/package-delta-soc/src/MlpPolicyRunnerBase.scala +++ b/package-delta-soc/src/MlpPolicyRunnerBase.scala @@ -39,14 +39,12 @@ import builder.{addConstraintResource, addSimulationResource} */ case class SoCConfig( - TileConfig: TileConfig = new TileConfig(sbusFrequency=50), + tile: TileConfig = new TileConfig(sbusFrequency=50), ) class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { val io = IO(new Arty100TIO()) - val systemClockFrequency = 50 - io := DontCare val clock = Wire(Clock()) @@ -54,7 +52,7 @@ class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { val pll_locked = Wire(Bool()) - val clk_wiz = Module(new ClockingWizard(Seq(systemClockFrequency))) + val clk_wiz = Module(new ClockingWizard(Seq(config.tile.sbusFrequency))) // clocking wizard connection clk_wiz.io.clk_in := io.CLK100MHZ clk_wiz.io.reset := ~io.ck_rst @@ -72,7 +70,7 @@ class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { withClockAndReset(clock, reset) { val reset_vector = RegInit(0x0800_0000.U(32.W)) - val tile = Module(new Tile(config.TileConfig)) + val tile = Module(new Tile(config.tile)) tile.io.reset_vector := reset_vector @@ -99,7 +97,7 @@ class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { // val spi = Module(new Axi4SpiFlash()) val gpio = Module(new Axi4LiteGpio()) - val uart = Module(new Axi4LiteUartLite(Axi4LiteUartLiteConfig(axiClockFrequency=systemClockFrequency))) + val uart = Module(new Axi4LiteUartLite(Axi4LiteUartLiteConfig(axiClockFrequency=config.tile.sbusFrequency))) val timer = Module(new Axi4LiteTimer(Axi4LiteTimerConfig(timerCounterWidth=32))) pbus_crossbar.io.s_axi(0).connectFromAxi4(tile.io.pbus) diff --git a/package-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala index a5ebc73..f05563a 100644 --- a/package-delta-soc/src/Tile.scala +++ b/package-delta-soc/src/Tile.scala @@ -7,7 +7,7 @@ import vivadoips.{Axi4Crossbar, Axi4BlockMemory, Axi4DataWidthConverter} case class TileConfig( - CoreConfig: CoreConfig = new CoreConfig(), + core: CoreConfig = new CoreConfig(), sbusFrequency: Int = 20, ) @@ -25,13 +25,13 @@ class Tile( dontTouch(io.reset_vector) dontTouch(io.debug) - val busWidth = config.CoreConfig.VLEN + val busWidth = config.core.VLEN val core = Module(new Core( CoreConfig( VLEN=busWidth, - ELEN=config.CoreConfig.ELEN, - pipelineStages=config.CoreConfig.pipelineStages, + ELEN=config.core.ELEN, + pipelineStages=config.core.pipelineStages, ) )) diff --git a/package-delta-soc/src/designs/MlpPolicyRunner.scala b/package-delta-soc/src/designs/MlpPolicyRunner.scala index 45294cc..c685c7e 100644 --- a/package-delta-soc/src/designs/MlpPolicyRunner.scala +++ b/package-delta-soc/src/designs/MlpPolicyRunner.scala @@ -5,7 +5,19 @@ import chisel3.util._ import builder.{addConstraintResource, addSimulationResource} -class MlpPolicyRunner extends MlpPolicyRunnerBase(new SoCConfig()) { +class MlpPolicyRunner extends MlpPolicyRunnerBase( + new SoCConfig( + tile = new TileConfig( + core = new CoreConfig( + XLEN = 32, + ELEN = 32, + VLEN = 64, + pipelineStages = 3, + ), + sbusFrequency = 50, + ) + ) +) { addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc") addSimulationResource("package-delta-soc/test/MlpPolicyRunnerTestbench.sv") diff --git a/package-delta-soc/src/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala index 072d065..4d819f5 100644 --- a/package-delta-soc/src/memory/Axi4Memory.scala +++ b/package-delta-soc/src/memory/Axi4Memory.scala @@ -133,7 +133,7 @@ class Axi4Memory( if (memoryFileHex != "") { - addVivadoTclScript(s"add_memory_${memoryFileHex}.tcl", { + addVivadoTclScript(s"ip/add_memory_${memoryFileHex}.tcl", { val file_path = System.getProperty("user.dir") + "/firmware/" + memoryFileHex s""" diff --git a/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc b/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc index e69de29..e4d18a4 100644 --- a/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc +++ b/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc @@ -0,0 +1,226 @@ +## This file is a general .xdc for the Arty A7-100 Rev. D and Rev. E +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { io_CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { io_CLK100MHZ }]; + +## Switches +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { io_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0] +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { io_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { io_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { io_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] + +## RGB LEDs +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { io_led0_b }]; #IO_L18N_T2_35 Sch=led0_b +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { io_led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { io_led0_r }]; #IO_L19P_T3_35 Sch=led0_r +set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { io_led1_b }]; #IO_L20P_T3_35 Sch=led1_b +set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { io_led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { io_led1_r }]; #IO_L20N_T3_35 Sch=led1_r +set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { io_led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b +set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { io_led2_g }]; #IO_L22N_T3_35 Sch=led2_g +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { io_led2_r }]; #IO_L22P_T3_35 Sch=led2_r +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { io_led3_b }]; #IO_L23P_T3_35 Sch=led3_b +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { io_led3_g }]; #IO_L24P_T3_35 Sch=led3_g +set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { io_led3_r }]; #IO_L23N_T3_35 Sch=led3_r + +## LEDs +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { io_led[0] }]; #IO_L24N_T3_35 Sch=led[4] +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { io_led[1] }]; #IO_25_35 Sch=led[5] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { io_led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { io_led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] + +## Buttons +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { io_btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { io_btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] + +## Pmod Header JA +set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { io_ja_0 }]; #IO_0_15 Sch=ja[1] +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { io_ja_1 }]; #IO_L4P_T0_15 Sch=ja[2] +set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { io_ja_2 }]; #IO_L4N_T0_15 Sch=ja[3] +set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { io_ja_3 }]; #IO_L6P_T0_15 Sch=ja[4] +set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { io_ja_4 }]; #IO_L6N_T0_VREF_15 Sch=ja[7] +set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { io_ja_5 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] +set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { io_ja_6 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { io_ja_7 }]; #IO_25_15 Sch=ja[10] + +## Pmod Header JB +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_0 }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { io_jb_1 }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] +set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_2 }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2] +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_3 }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { io_jb_4 }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { io_jb_5 }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_6 }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { io_jb_7 }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4] + +## Pmod Header JC +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { io_jc_0 }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { io_jc_1 }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { io_jc_2 }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { io_jc_3 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { io_jc_4 }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { io_jc_5 }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { io_jc_6 }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { io_jc_7 }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4] + +## Pmod Header JD +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { io_jd_0 }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] +set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { io_jd_1 }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { io_jd_2 }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] +set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { io_jd_3 }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] +set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_4 }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] +set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_5 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] +set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_6 }]; #IO_L15P_T2_DQS_35 Sch=jd[9] +set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { io_jd_7 }]; #IO_L15N_T2_DQS_35 Sch=jd[10] + +## USB-UART Interface +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { io_uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { io_uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in + +## ChipKit Outer Digital Header +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8] +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12] +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13] + +## ChipKit Inner Digital Header +#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27] +#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28] +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_29 }]; #IO_25_14 Sch=ck_io[29] +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_30 }]; #IO_0_14 Sch=ck_io[30] +#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31] +#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32] +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] +#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_io_41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41] + +## ChipKit Outer Analog Header - as Single-Ended Analog Inputs +## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs. +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { io_vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0 +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { io_vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0 +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { io_vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1 +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { io_vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1 +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { io_vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2 +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { io_vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2 +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { io_vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3 +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { io_vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3 +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { io_vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4 +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { io_vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4 +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { io_vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5 +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { io_vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5 +## ChipKit Outer Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using these ports as digital I/O. +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a0 }]; #IO_0_35 Sch=ck_a[0] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] + +## ChipKit Inner Analog Header - as Differential Analog Inputs +## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O. +## WARNING: Do not use both sets of constraints at the same time! +## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs. +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { io_vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6 +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { io_vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7 +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { io_vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8 +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { io_vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9 +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { io_vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10 +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { io_vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11 +## ChipKit Inner Analog Header - as Digital I/O +## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O. +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { io_ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] + +## ChipKit SPI +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { io_ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { io_ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { io_ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { io_ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss + +## ChipKit I2C +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { io_ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { io_scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { io_sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup + +## Misc. ChipKit Ports +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { io_ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { io_ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst + +## SMSC Ethernet PHY +set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs +# set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc +# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio +set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk +set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn +set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk +set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] +set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] +set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3] +set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { io_eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { io_eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en +set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { io_eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3] + +create_clock -period 40.000 -name io_eth_rx_clk [get_ports io_eth_rx_clk] +create_clock -period 40.000 -name io_eth_tx_clk [get_ports io_eth_tx_clk] + +## Quad SPI Flash + +# manually created clock for qspi_sck +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_sck }]; +create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10} [get_ports { io_qspi_sck }]; + +set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_1 }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_2 }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dq_3 }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] + +set_property -dict { BITSTREAM.CONFIG.SPI_BUSWIDTH {4} } [current_design] + +## Power Measurements +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { io_vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { io_vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2] +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { io_vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1] +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { io_vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1] +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { io_isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { io_isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { io_isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { io_isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] \ No newline at end of file diff --git a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala index dbaa285..6976bc8 100644 --- a/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala +++ b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala @@ -125,7 +125,7 @@ class Axi4QuadSpiFlashBlackbox extends BlackBox { val ip_name = "Axi4QuadSpiFlashBlackbox" val ip_name_lower = ip_name.toLowerCase() - addVivadoTclScript(s"create_ip_${ip_name_lower}.tcl", { + addVivadoTclScript(s"ip/create_ip_${ip_name_lower}.tcl", { // HACK: add flash memory file to Vivado project // Get current working directory From ee6cf99a456329eb9baec728f42715e9023cdc31 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 16:46:09 -0700 Subject: [PATCH 17/18] ADD: bitstream generation flow --- builder/src/Builder.scala | 44 +++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala index 2568471..36006e2 100644 --- a/builder/src/Builder.scala +++ b/builder/src/Builder.scala @@ -245,36 +245,36 @@ object buildProject extends App { object buildBitstream extends App { val (designName, remainingArgs) = _parseModuleName(args) + { + // create a generate_bitstream.tcl file + val run_tcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/generate_bitstream.tcl") - // { - // // create a generate_bitstream.tcl file - // val run_tcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/scripts/generate_bitstream.tcl") - - // run_tcl.println(s"open_project ${BuilderConfig.vivadoTclDir}/VivadoProject.xpr") - - // val ip_name = "clk_wiz_0" + run_tcl.println(s"open_project ${BuilderConfig.vivadoProjectDir}/VivadoProject.xpr") - // run_tcl.println(s"reset_run ${ip_name}_synth_1") - // run_tcl.println(s"launch_runs ${ip_name}_synth_1") + // val ip_name = "clk_wiz_0" - // run_tcl.println(s"wait_on_run ${ip_name}_synth_1") + // run_tcl.println(s"reset_run ${ip_name}_synth_1") + // run_tcl.println(s"launch_runs ${ip_name}_synth_1") - // run_tcl.println(s"reset_run synth_1") - // run_tcl.println(s"launch_runs synth_1 -jobs 8") + // run_tcl.println(s"wait_on_run ${ip_name}_synth_1") - // run_tcl.println(s"wait_on_run synth_1") + // run_tcl.println(s"reset_run synth_1") + // run_tcl.println(s"launch_runs synth_1 -jobs 8") - // run_tcl.println(s"update_compile_order -fileset sources_1") - // run_tcl.println(s"launch_runs impl_1 -to_step write_bitstream -jobs 8") - // run_tcl.println(s"wait_on_run impl_1") + // run_tcl.println(s"wait_on_run synth_1") - // run_tcl.println(s"open_run impl_1") - // run_tcl.println(s"write_bitstream ${BuilderConfig.vivadoTclDir}/Arty100TShell.bit -force") + run_tcl.println(s"update_compile_order -fileset sources_1") + run_tcl.println(s"launch_runs impl_1 -to_step write_bitstream -jobs 8") + run_tcl.println(s"wait_on_run impl_1") + run_tcl.println(s"open_run impl_1") + run_tcl.println(s"write_bitstream ${BuilderConfig.vivadoTclDir}/Arty100TShell.bit -force") - // run_tcl.close() - // run_tcl.flush() // make sure the file is written to the disk - // } + run_tcl.println(s"close_project") + + run_tcl.close() + run_tcl.flush() // make sure the file is written to the disk + } - // s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/scripts/generate_bitstream.tcl".! + s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/generate_bitstream.tcl".! } From 9399f8366ef59574bed6918b841099235b906e8d Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Fri, 9 May 2025 16:46:35 -0700 Subject: [PATCH 18/18] FIX: minor issues --- package-delta-soc/src/MlpPolicyRunnerBase.scala | 2 -- package-delta-soc/src/Tile.scala | 2 +- package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala | 3 ++- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/package-delta-soc/src/MlpPolicyRunnerBase.scala b/package-delta-soc/src/MlpPolicyRunnerBase.scala index d807603..0bc748b 100644 --- a/package-delta-soc/src/MlpPolicyRunnerBase.scala +++ b/package-delta-soc/src/MlpPolicyRunnerBase.scala @@ -130,9 +130,7 @@ class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule { dontTouch(tile.io.sbus.ar.bits.burst) - // io.qspi_sck := spi.io.sck_o.asClock io.qspi_cs := spi.io.ss_o - // spi.io.sck_i := 0.B spi.io.ss_i := 0.B val qspi_io0_buf = Module(new IOBUF()) diff --git a/package-delta-soc/src/Tile.scala b/package-delta-soc/src/Tile.scala index f05563a..c67f133 100644 --- a/package-delta-soc/src/Tile.scala +++ b/package-delta-soc/src/Tile.scala @@ -29,7 +29,7 @@ class Tile( val core = Module(new Core( CoreConfig( - VLEN=busWidth, + VLEN=config.core.VLEN, ELEN=config.core.ELEN, pipelineStages=config.core.pipelineStages, ) diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala index d57c830..b7b1079 100644 --- a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala +++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala @@ -47,10 +47,11 @@ class Axi4LiteUartLiteBlackbox( library="ip", version="2.0", moduleName=ipName, + // the "d" is not a typo down there extra = s""" set_property -dict [list \\ CONFIG.C_BAUDRATE {${config.baudRate}} \\ - CONFIG.C_S_AXI_ACLK_FREQ_HZ {${config.axiClockFrequency}} \\ + CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {${config.axiClockFrequency}} \\ ] [get_ips ${ipName}] """ )