diff --git a/.github/workflows/build-example.yaml b/.github/workflows/build-verilog.yaml
similarity index 64%
rename from .github/workflows/build-example.yaml
rename to .github/workflows/build-verilog.yaml
index c6144c8..a83ffde 100644
--- a/.github/workflows/build-example.yaml
+++ b/.github/workflows/build-verilog.yaml
@@ -1,4 +1,4 @@
-name: Build Example
+name: Build Verilog
 
 on:
   push:
@@ -16,10 +16,6 @@ jobs:
       # with:
       #   submodules: recursive
 
-    - name: Set up Toolchain
-      run: source $GITHUB_WORKSPACE/scripts/install-mill.sh
-
     - name: Run make verilog
       run: |
-        export PATH=$GITHUB_WORKSPACE/toolchains:$PATH
         make verilog
diff --git a/.github/workflows/run-vivado-flow.yaml b/.github/workflows/run-vivado-flow.yaml
new file mode 100644
index 0000000..2a82c11
--- /dev/null
+++ b/.github/workflows/run-vivado-flow.yaml
@@ -0,0 +1,25 @@
+name: Run Vivado Flow
+
+on:
+  push:
+    branches: [ "main" ]
+  pull_request:
+    branches: [ "main" ]
+
+jobs:
+  build:
+    runs-on: self-hosted
+
+    steps:
+    - name: Checkout
+      uses: actions/checkout@v4
+
+    - name: Build MemorySubsystem
+      run: |
+        source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh
+        make project PACKAGE=delta-soc DESIGN=delta.MemorySubsystem
+
+    - name: Build MlpPolicyRunner
+      run: |
+        source /ecad/tools/xilinx/Vivado/2023.2.1/settings64.sh
+        make project PACKAGE=delta-soc DESIGN=delta.MlpPolicyRunner
diff --git a/.gitignore b/.gitignore
index b372fed..eb37ad1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,7 +17,6 @@ firmware/*.section
 firmware/*.symbol
 
 # Toolchains
-toolchains/mill
 
 # Vivado
 vivado*.jou
diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index e69de29..0000000
diff --git a/ChiselProject/src/Elaborate.scala b/ChiselProject/src/Elaborate.scala
deleted file mode 100644
index 6ba4604..0000000
--- a/ChiselProject/src/Elaborate.scala
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
- * Elaborate.scala
- *
- * This file is responsible for elaborating the Chisel design into SystemVerilog. It is the main entry point for
- * generating the hardware description.
- */
-
-import circt.stage.ChiselStage
-import scala.sys.process._
-import java.io.PrintWriter
-import java.io.File
-import java.io.FileFilter
-
-// helper function to parse the module name from the arguments
-object ParseModuleName {
-  def apply(args: Array[String]): (String, Array[String]) = {
-    if (args.length < 1) {
-      println("Error: Please provide the module name as an argument")
-      System.exit(1)
-    }
-
-    args.sliding(2).zipWithIndex.collectFirst {
-      case (Array("--module-name", name), i) => (name, args.take(i) ++ args.drop(i + 2))
-    }.getOrElse {
-      println("Error: Please provide the module name with --module-name flag")
-      System.exit(1)
-      ("", Array.empty[String])  // This is never reached but needed for type inference
-    }
-  }
-}
-
-object CreateVivadoDirectory {
-  def apply(vivado_project_dir: String): Unit = {
-    new File(vivado_project_dir).mkdirs()
-    new File(s"${vivado_project_dir}/scripts").mkdirs()
-  }
-}
-
-
-
-object GenerateVerilog extends App {
-  val (module_name, remaining_args) = ParseModuleName(args)
-
-  val vivado_project_dir = "out/VivadoProject"
-  CreateVivadoDirectory(vivado_project_dir)
-
-
-  val moduleClass = () => {
-    val module = Class.forName(module_name)
-      .getDeclaredConstructor()
-      .newInstance()
-      .asInstanceOf[chisel3.RawModule]
-    module
-  }
-  
-  println(s"elaborating module: $module_name")
-  val chisel_opts = remaining_args ++ Array("--split-verilog")
-
-  val firtool_opts = Array(
-    "-disable-all-randomization",
-    "-strip-debug-info",
-  )
-
-  ChiselStage.emitSystemVerilogFile(
-    gen=moduleClass(),
-    args=chisel_opts,
-    firtoolOpts=firtool_opts
-  )
-}
-
-object GenerateProject extends App {
-  val (module_name, remaining_args) = ParseModuleName(args)
-
-  val project_source_dir = "ChiselProject/"
-  val vivado_project_dir = "out/VivadoProject"
-
-  CreateVivadoDirectory(vivado_project_dir)
-
-  /* Arty A7 100T */
-  // val fpga_part = "xc7a100ticsg324-1L"
-  // val board_part = "digilentinc.com:arty-a7-100t:part0:1.1"
-
-  /* Arty A7 35T */
-  val fpga_part = "xc7a35ticsg324-1L"
-  val board_part = "digilentinc.com:arty-a7-35:part0:1.1"
-
-  /* Zedboard */
-  // val fpga_part = "xc7z020clg484-1"
-  // val board_part = "digilentinc.com:zedboard:part0:1.1"
-
-  // get all files under the generated-src directory
-  val sources = new File("generated-src").listFiles(new FileFilter {
-    def accept(file: File): Boolean = file.isFile || file.isDirectory
-  }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
-  val verilog_sources = new File("ChiselProject/test/resources").listFiles(new FileFilter {
-    def accept(file: File): Boolean = file.isFile || file.isDirectory
-  }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
-
-  val excluded_sources = Array(
-    "ClockSourceAtFreqMHz.v",
-    "SimJTAG.v",
-    "SimTSI.v",
-    "SimUART.v",
-    "TestDriver.v",
-  )
-
-
-  // val chipyard_sources = new File("chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.WithPeripheralAXI4LiteTinyRocketConfig/gen-collateral").listFiles(new FileFilter {
-  //   def accept(file: File): Boolean = file.isFile || file.isDirectory
-  // }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
-  // // Exclude files listed in excluded_sources
-  // .filterNot(source => excluded_sources.contains(new File(source).getName))
-
-  {
-    // create a run.tcl file
-    val run_tcl = new PrintWriter(s"${vivado_project_dir}/scripts/create_project.tcl")
-
-    // create project
-    run_tcl.println(s"create_project VivadoProject ${vivado_project_dir} -part ${fpga_part} -force")
-    // run_tcl.println(s"set_property board_part $board_part [current_project]")
-    
-    // add constraints
-    run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/Arty-A7-100-Master.xdc")
-
-    run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/axis_async_fifo.tcl")
-    run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/eth_mac_fifo.tcl")
-    run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/mii_phy_if.tcl")
-    run_tcl.println(s"add_files -fileset constrs_1 -norecurse ${project_source_dir}/resources/constraints/sync_reset.tcl")
-
-
-    // add sources
-    run_tcl.print(s"add_files")
-    sources.foreach(source => {
-      run_tcl.println(s" ${source} \\")
-    })
-    run_tcl.println("")
-
-    run_tcl.print(s"add_files -fileset sim_1 {")
-    verilog_sources.foreach(source => {
-      run_tcl.println(s" ${source} \\")
-    })
-    run_tcl.println("}")
-
-    // run_tcl.print(s"add_files")
-    // chipyard_sources.foreach(source => {
-    //   run_tcl.println(s" ${source} \\")
-    // })
-    // run_tcl.println("")
-
-    run_tcl.println(s"set_property top ${module_name} [current_fileset]")
-
-    /* create Vivado IPs */
-    run_tcl.println("update_ip_catalog")
-
-    val create_ip_files = new File(s"${vivado_project_dir}/scripts").listFiles(new FileFilter {
-      def accept(file: File): Boolean = file.isFile && file.getName != "create_project.tcl"
-    }).map(_.getAbsolutePath)
-
-    create_ip_files.foreach(file => {
-      run_tcl.println(s"source ${file}")
-    })
-
-
-    // configure simulation settings    
-    run_tcl.println(s"update_compile_order -fileset sources_1")
-    run_tcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]")
-    run_tcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]")
-    run_tcl.println(s"set_property top ${module_name}Testbench [get_filesets sim_1]")
-    // run_tcl.println(s"set_property top_lib xil_defaultlib [get_filesets sim_1]")
-
-
-    run_tcl.close()
-    run_tcl.flush()
-  }
-
-
-  s"vivado -mode batch -source ${vivado_project_dir}/scripts/create_project.tcl".!
-}
-
-object GenerateBitstream extends App {
-  val (module_name, remaining_args) = ParseModuleName(args)
-
-  val vivado_project_dir = "out/VivadoProject"
-  CreateVivadoDirectory(vivado_project_dir)
-
-  // {
-  //   // create a generate_bitstream.tcl file
-  //   val run_tcl = new PrintWriter(s"${vivado_project_dir}/scripts/generate_bitstream.tcl")
-
-  //   run_tcl.println(s"open_project ${vivado_project_dir}/VivadoProject.xpr")
-
-  //   val ip_name = "clk_wiz_0"
-
-  //   run_tcl.println(s"reset_run ${ip_name}_synth_1")
-  //   run_tcl.println(s"launch_runs ${ip_name}_synth_1")
-
-  //   run_tcl.println(s"wait_on_run ${ip_name}_synth_1")
-
-  //   run_tcl.println(s"reset_run synth_1")
-  //   run_tcl.println(s"launch_runs synth_1 -jobs 8")
-
-  //   run_tcl.println(s"wait_on_run synth_1")
-
-  //   run_tcl.println(s"update_compile_order -fileset sources_1")
-  //   run_tcl.println(s"launch_runs impl_1 -to_step write_bitstream -jobs 8")
-  //   run_tcl.println(s"wait_on_run impl_1")
-
-  //   run_tcl.println(s"open_run impl_1")
-  //   run_tcl.println(s"write_bitstream ${vivado_project_dir}/Arty100TShell.bit -force")
-
-
-  //   run_tcl.close()
-  //   run_tcl.flush()   // make sure the file is written to the disk
-  // }
-
-  // s"vivado -mode batch -source ${vivado_project_dir}/scripts/generate_bitstream.tcl".!
-}
diff --git a/ChiselProject/src/generators/alexforencich/UDPCore.scala b/ChiselProject/src/generators/alexforencich/UDPCore.scala
deleted file mode 100644
index 1ff2a72..0000000
--- a/ChiselProject/src/generators/alexforencich/UDPCore.scala
+++ /dev/null
@@ -1,69 +0,0 @@
-import chisel3.{BlackBox, _}
-import chisel3.util._
-import chisel3.experimental.IntParam
-
-
-class udp_core(
-  mac_address: Long = 0x02_00_00_00_00_00L,
-  ip_address: Int = 0xC0_A8_01_80,
-  gateway_ip: Int = 0xC0_A8_01_01,
-  subnet_mask: Int = 0xFF_FF_FF_00,
-  udp_port: Int = 1234
-) extends BlackBox(Map(
-    "MAC_ADDRESS" -> IntParam(mac_address),
-    "IP_ADDRESS" -> IntParam(ip_address),
-    "GATEWAY_IP" -> IntParam(gateway_ip),
-    "SUBNET_MASK" -> IntParam(subnet_mask),
-    "UDP_PORT" -> IntParam(udp_port)
-  )) with HasBlackBoxResource {
-  val io = IO(new Bundle {
-    val clk = Input(Clock())
-    val rst = Input(Reset())
-
-    val btn = Input(UInt(4.W))
-    val sw = Input(UInt(4.W))
-    val led0_r = Output(Bool())
-    val led0_g = Output(Bool())
-    val led0_b = Output(Bool())
-    val led1_r = Output(Bool())
-    val led1_g = Output(Bool())
-    val led1_b = Output(Bool())
-    val led2_r = Output(Bool())
-    val led2_g = Output(Bool())
-    val led2_b = Output(Bool())
-    val led3_r = Output(Bool())
-    val led3_g = Output(Bool())
-    val led3_b = Output(Bool())
-    val led4 = Output(Bool())
-    val led5 = Output(Bool())
-    val led6 = Output(Bool())
-    val led7 = Output(Bool())
-
-    val phy_rx_clk = Input(Bool())
-    val phy_rxd = Input(UInt(4.W))
-    val phy_rx_dv = Input(Bool())
-    val phy_rx_er = Input(Bool())
-    val phy_tx_clk = Input(Bool())
-    val phy_txd = Output(UInt(4.W))
-    val phy_tx_en = Output(Bool())
-    val phy_col = Input(Bool())
-    val phy_crs = Input(Bool())
-    val phy_reset_n = Output(Bool())
-
-    val uart_rxd = Input(Bool())
-    val uart_txd = Output(Bool())
-    
-    val rx_fifo_udp_payload_axis_tdata = Output(UInt(8.W))
-    val rx_fifo_udp_payload_axis_tvalid = Output(Bool())
-    val rx_fifo_udp_payload_axis_tready = Input(Bool())
-    val rx_fifo_udp_payload_axis_tlast = Output(Bool())
-    val rx_fifo_udp_payload_axis_tuser = Output(Bool())
-
-    val tx_fifo_udp_payload_axis_tdata = Input(UInt(8.W))
-    val tx_fifo_udp_payload_axis_tvalid = Input(Bool())
-    val tx_fifo_udp_payload_axis_tready = Output(Bool())
-    val tx_fifo_udp_payload_axis_tlast = Input(Bool())
-    val tx_fifo_udp_payload_axis_tuser = Input(Bool())
-  })
-}
-
diff --git a/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala b/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala
deleted file mode 100644
index ef15084..0000000
--- a/ChiselProject/src/generators/xilinx/Axi4DataWidthConverter.scala
+++ /dev/null
@@ -1,61 +0,0 @@
-import chisel3._
-import chisel3.util._
-import java.io.PrintWriter
-
-
-class Axi4DataWidthConverter(
-  s_params: Axi4Params,
-  m_params: Axi4Params
-) extends Module {
-  val io = IO(new Bundle {
-    val s_axi = Flipped(new Axi4Bundle(s_params))
-    val m_axi = new Axi4Bundle(m_params)
-  })
-
-  val blackbox = Module(new Axi4DataWidthConverterBlackbox(s_params, m_params))
-
-  blackbox.io.s_axi_aclk := clock
-  blackbox.io.s_axi_aresetn := ~reset.asBool
-  blackbox.io.s_axi.connectFrom(io.s_axi)
-  blackbox.io.m_axi.connectTo(io.m_axi)
-}
-
-class Axi4DataWidthConverterBlackbox(
-  s_params: Axi4Params,
-  m_params: Axi4Params
-) extends BlackBox {
-  val io = IO(new Bundle {
-    val s_axi_aclk = Input(Clock())
-    val s_axi_aresetn = Input(Bool())
-    val s_axi = Flipped(new Axi4BlackboxBundle(s_params))
-    val m_axi = new Axi4BlackboxBundle(m_params)
-  })
-
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4DataWidthConverterBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}")
-
-    tcl_script.println(s"""
-set_property -dict [list \\
-  CONFIG.MI_DATA_WIDTH {${m_params.dataWidth}} \\
-  CONFIG.SI_DATA_WIDTH {${s_params.dataWidth}} \\
-  CONFIG.SI_ID_WIDTH {${s_params.idWidth}} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
-}
\ No newline at end of file
diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala b/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala
deleted file mode 100644
index 9757f7d..0000000
--- a/ChiselProject/src/generators/xilinx/Axi4LiteGpio.scala
+++ /dev/null
@@ -1,55 +0,0 @@
-import chisel3._
-import chisel3.util._
-
-import java.io.PrintWriter
-
-
-class Axi4LiteGpio extends Module {
-  val io = IO(new Bundle {
-    val s_axi = Flipped(new Axi4LiteBundle())
-    val gpio_io_i = Input(UInt(32.W))
-    val gpio_io_o = Output(UInt(32.W))
-    val gpio_io_t = Output(UInt(32.W))
-  })
-
-  val blackbox = Module(new Axi4LiteGpioBlackbox())
-
-  blackbox.io.s_axi_aclk := clock
-  blackbox.io.s_axi_aresetn := ~reset.asBool
-  blackbox.io.s_axi.connectFrom(io.s_axi)
-
-  blackbox.io.gpio_io_i := io.gpio_io_i
-  io.gpio_io_o := blackbox.io.gpio_io_o
-  io.gpio_io_t := blackbox.io.gpio_io_t
-}
-
-class Axi4LiteGpioBlackbox extends BlackBox {
-  val io = IO(new Bundle {
-    val s_axi_aclk = Input(Clock())
-    val s_axi_aresetn = Input(Bool())
-    val s_axi = Flipped(new Axi4LiteBlackboxBundle())
-    val gpio_io_i = Input(UInt(32.W))
-    val gpio_io_o = Output(UInt(32.W))
-    val gpio_io_t = Output(UInt(32.W))
-  })
-  
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4LiteGpioBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_gpio -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
-}
diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala b/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala
deleted file mode 100644
index c1a0472..0000000
--- a/ChiselProject/src/generators/xilinx/Axi4LiteStreamDataFifo.scala
+++ /dev/null
@@ -1,55 +0,0 @@
-import chisel3._
-import chisel3.util._
-
-import java.io.PrintWriter
-
-
-class Axi4LiteStreamDataFifo(width: Int) extends Module {
-  val io = IO(new Bundle {
-    val s_axis = Flipped(new Axi4StreamBundle())
-    val m_axis = new Axi4StreamBundle()
-  })
-
-  val blackbox = Module(new Axi4LiteStreamDataFifoBlackbox(width))
-
-  blackbox.io.s_axis_aclk := clock
-  blackbox.io.s_axis_aresetn := ~reset.asBool
-  blackbox.io.s_axis.connect(io.s_axis)
-  blackbox.io.m_axis.flipConnect(io.m_axis)
-}
-
-class Axi4LiteStreamDataFifoBlackbox(width: Int) extends BlackBox {
-  val io = IO(new Bundle {
-    val s_axis_aclk = Input(Clock())
-    val s_axis_aresetn = Input(Reset())
-    val s_axis = Flipped(new Axi4StreamBlackboxBundle())
-    val m_axis = new Axi4StreamBlackboxBundle()
-  })
-
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "AXIStreamDataFifo"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}")
-
-    tcl_script.println(s"""
-set_property -dict [list \\
-  CONFIG.HAS_TLAST {1} \\
-  CONFIG.TUSER_WIDTH {1} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
-}
diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala b/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala
deleted file mode 100644
index 3ab4193..0000000
--- a/ChiselProject/src/generators/xilinx/Axi4LiteUartLite.scala
+++ /dev/null
@@ -1,62 +0,0 @@
-import chisel3._
-import chisel3.util._
-
-import java.io.PrintWriter
-
-class Axi4LiteUartLite(
-  val axiClockFrequency: Int = 100,
-) extends Module {
-  val io = IO(new Bundle {
-    val s_axi = Flipped(new Axi4LiteBundle())
-    val rx = Input(Bool())
-    val tx = Output(Bool())
-  })
-
-  val blackbox = Module(new Axi4LiteUartLiteBlackbox(axiClockFrequency=axiClockFrequency))
-
-  blackbox.io.s_axi_aclk := clock
-  blackbox.io.s_axi_aresetn := ~reset.asBool
-  blackbox.io.s_axi.connectFrom(io.s_axi)
-  blackbox.io.rx := io.rx
-  io.tx := blackbox.io.tx
-}
-
-class Axi4LiteUartLiteBlackbox(
-  val axiClockFrequency: Int = 100,
-) extends BlackBox {
-  val io = IO(new Bundle {
-    val s_axi_aclk = Input(Clock())
-    val s_axi_aresetn = Input(Bool())
-    val s_axi = Flipped(new Axi4LiteBlackboxBundle())
-    val rx = Input(Bool())
-    val tx = Output(Bool())
-  })
-
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4LiteUartLiteBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}")
-
-    tcl_script.println(s"""
-set_property -dict [list \\
-  CONFIG.C_BAUDRATE {115200} \\
-  CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {${axiClockFrequency}} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
-}
-
diff --git a/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala b/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala
deleted file mode 100644
index 30592d4..0000000
--- a/ChiselProject/src/generators/xilinx/Axi4ProtocolConverter.scala
+++ /dev/null
@@ -1,62 +0,0 @@
-import chisel3._
-import chisel3.util._
-import java.io.PrintWriter
-
-
-class Axi4ProtocolConverter(
-  s_params: Axi4Params,
-  m_params: Axi4Params
-) extends Module {
-  val io = IO(new Bundle {
-    val s_axi = Flipped(new Axi4Bundle(s_params))
-    val m_axi = new Axi4LiteBundle()
-  })
-
-  val blackbox = Module(new Axi4ProtocolConverterBlackbox(s_params, m_params))
-
-  blackbox.io.aclk := clock
-  blackbox.io.aresetn := ~reset.asBool
-  blackbox.io.s_axi.connectFrom(io.s_axi)
-  blackbox.io.m_axi.connectTo(io.m_axi)
-}
-
-class Axi4ProtocolConverterBlackbox(
-  s_params: Axi4Params,
-  m_params: Axi4Params
-) extends BlackBox {
-  val io = IO(new Bundle {
-    val aclk = Input(Clock())
-    val aresetn = Input(Bool())
-    val s_axi = Flipped(new Axi4BlackboxBundle(s_params))
-    val m_axi = new Axi4LiteBlackboxBundle(m_params)
-  })
-
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4ProtocolConverterBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}")
-    
-    tcl_script.println(s"""
-set_property -dict [list \\
-  CONFIG.ID_WIDTH {${s_params.idWidth}} \\
-  CONFIG.MI_PROTOCOL {AXI4LITE} \\
-  CONFIG.SI_PROTOCOL {AXI4} \\
-  CONFIG.DATA_WIDTH {${s_params.dataWidth}} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
-}
\ No newline at end of file
diff --git a/ChiselProject/test/resources/verilog/TestDriver.sv b/ChiselProject/test/resources/verilog/TestDriver.sv
deleted file mode 100644
index 5407275..0000000
--- a/ChiselProject/test/resources/verilog/TestDriver.sv
+++ /dev/null
@@ -1,25 +0,0 @@
-`timescale 1ns / 1ps
-
-
-module TestDriver(
-  output logic clock,
-  output logic reset
-);
-  parameter CLOCK_FREQ = 100_000_000;
-  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
-  
-  // setup clock and reset
-  reg clock, reset;
-  initial clock = 'b0;
-  always #(CLOCK_PERIOD/2) clock = ~clock;
-
-  initial begin
-    reset = 1'b1;
-    repeat (10) @(posedge clock);
-    reset = 1'b0;
-
-    repeat (10000) @(posedge clock);
-    $finish;
-  end
-
-endmodule
diff --git a/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv b/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv
deleted file mode 100644
index 05eb236..0000000
--- a/ChiselProject/test/resources/verilog/examples/GenericTestBench.sv
+++ /dev/null
@@ -1,77 +0,0 @@
-`timescale 1ns / 1ps
-
-
-module GenericTestBench();
-  parameter CLOCK_FREQ = 100_000_000;
-  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
-  
-  // setup clock and reset
-  reg clock, reset;
-  initial clock = 'b0;
-  always #(CLOCK_PERIOD/2) clock = ~clock;
-
-  logic led;
-
-
-  wire IO0_IO;
-  wire IO1_IO;
-  wire SCK_IO;
-  wire SS_IO;
-
-
-  
-  SimSpiFlashModel #(
-    .PLUSARG("firmware.8.hex"),
-    .READONLY(0),
-    .CAPACITY_BYTES(1024)
-  ) sim_spi (
-    .sck(SCK_IO),
-    .cs_0(SS_IO),
-    .reset(reset),
-    .dq_0(IO0_IO),
-    .dq_1(IO1_IO),
-    .dq_2(),
-    .dq_3()
-  );
-
-  BiliArty100T dut(
-    .io_CLK100MHZ(clock),
-    .io_sw(4'b0),
-    .io_btn(4'b0),
-    .io_ja_0(),
-    .io_ja_1(),
-    .io_ja_2(),
-    .io_ja_3(),
-    .io_ja_4(),
-    .io_ja_5(),
-    .io_ja_6(),
-    .io_ja_7(),
-    .io_uart_txd_in(1'b0),
-    .io_uart_rxd_out(),
-    .io_ck_ioa(1'b0),
-    .io_ck_rst(~reset),
-    .io_eth_col(1'b0),
-    .io_eth_crs(1'b0),
-    .io_eth_rx_clk(1'b0),
-    .io_eth_rx_dv(1'b0),
-    .io_eth_rxd(4'b0),
-    .io_eth_rxerr(1'b0),
-    .io_eth_tx_clk(1'b0),
-    .io_qspi_cs(SS_IO),
-    .io_qspi_sck(SCK_IO),
-    .io_qspi_dq_0(IO0_IO),
-    .io_qspi_dq_1(IO1_IO),
-    .io_qspi_dq_2(),
-    .io_qspi_dq_3(),
-    .io_led(led)
-  );
-
-  initial begin
-    reset = 1'b1;
-    repeat (10) @(posedge clock);
-    reset = 1'b0;
-
-    repeat (10000) @(posedge clock);
-    $finish;
-  end
-endmodule
diff --git a/ChiselProject/test/resources/vhdl/components/SimSpiFlash.vhd b/ChiselProject/test/resources/vhdl/components/SimSpiFlash.vhd
deleted file mode 100644
index bcdcd75..0000000
--- a/ChiselProject/test/resources/vhdl/components/SimSpiFlash.vhd
+++ /dev/null
@@ -1,486 +0,0 @@
---SimSpiFlash
--- file: SimSpiFlash.vhd
---
--- (c) Copyright 2008 - 2023 Advanced Micro Devices, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Advanced Micro Devices, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- AMD, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) AMD shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or AMD had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- AMD products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of AMD products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- This is a self-desigined Memory model for XIP mode support memories to act as slave
--- for AXI QSPI in Example design
---
-------------------------------------------------------------------------------
-library ieee;
-    use ieee.std_logic_1164.all;
-    use ieee.std_logic_arith.all;
-    use ieee.std_logic_unsigned.all;
-    use ieee.numeric_std.all;
-    use ieee.std_logic_misc.all;
-
-
-entity SimSpiFlash is generic (
-  C_FIFO_DEPTH          : integer              := 256;-- allowed 0,16,256.
-  C_ADDR_WIDTH          : integer              := 256;-- allowed 0,16,256.
-
-	C_SPI_MODE            : integer range 0 to 2 := 0; -- used for differentiating
-                                                     -- Standard, Dual or Quad mode
-                                                     -- in Ports as well as internal
-                                                     -- functionality
-	C_DATA_WIDTH          : integer               := 8       -- allowed 8,32.
-);
-  port (
-    MODEL_CLK            : in  std_logic;
-    MODEL_RESET          : in  std_logic;
-    Core_Clk             : in std_logic;
-    Chip_Selectn         : in std_logic;
-
-    -------------------------------
-    --*SPI port interface      * --
-    -------------------------------
-    io0_i          : in std_logic;  -- MOSI signal in standard SPI
-    io0_o          : out std_logic;
-    io0_t          : out std_logic;
-    -------------------------------
-    io1_i          : in std_logic;  -- MISO signal in standard SPI
-    io1_o          : out std_logic;
-    io1_t          : out std_logic;
-    -----------------
-    -- quad mode pins
-    -----------------
-    io2_i          : in std_logic;
-    io2_o          : out std_logic;
-    io2_t          : out std_logic;
-    ---------------
-    io3_i          : in std_logic;
-    io3_o          : out std_logic;
-    io3_t          : out std_logic
-    ---------------------------------
-);
-end SimSpiFlash;
-
-architecture imp of SimSpiFlash is
-
-  --------------------------------------------------------------------------------------
-  -- below attributes are added to reduce the synth warnings in Vivado tool
-    attribute DowngradeIPIdentifiedWarnings: string;
-    attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-  --------------------------------------------------------------------------------------
-
-  function log2(x : natural) return integer is
-    variable i  : integer := 0;
-    variable val: integer := 1;
-  begin
-    if x = 0 then return 0;
-    else
-      for j in 0 to 29 loop -- for loop for XST
-        if val >= x then null;
-        else
-          i := i+1;
-          val := val*2;
-        end if;
-      end loop;
-    -- Fix per CR520627  XST was ignoring this anyway and printing a
-    -- Warning in SRP file. This will get rid of the warning and not
-    -- impact simulation.
-    -- synthesis translate_off
-      assert val >= x
-        report "Function log2 received argument larger" &
-              " than its capability of 2^30. "
-        severity failure;
-    -- synthesis translate_on
-      return i;
-    end if;
-  end function log2;
-
-
-  constant ADDR_WIDTH     : INTEGER   := log2(C_FIFO_DEPTH);
-  constant RESET_ACTIVE   : std_logic := '0';
-  constant CMD_FAST_READ  : std_logic_vector(7 downto 0):= X"0B";
-  constant CMD_DUAL_READ  : std_logic_vector(7 downto 0):= X"BB";
-  constant CMD_QUAD_READ  : std_logic_vector(7 downto 0):= X"EB";
-  constant Wait_std       : INTEGER   := (C_ADDR_WIDTH + 8);
-  constant Wait_dual      : INTEGER   := (C_ADDR_WIDTH/2 + 4);
-  constant Wait_quad      : INTEGER   := (C_ADDR_WIDTH/4 + 8);
-
-
-  signal Serial_Dout_0    : std_logic := '0';
-  signal Serial_Dout_1    : std_logic := '0';
-  signal Serial_Dout_2    : std_logic := '0';
-  signal Serial_Dout_3    : std_logic := '0';
-
-  signal FIFO_RD_EN       : std_logic := '0';
-  signal rising           : std_logic := '0';
-  signal falling          : std_logic := '0';
-  signal SCK_D            : std_logic := '0';
-
-  signal Count_Pulse      : std_logic := '0';
-  signal Count_Pulse_d    : std_logic := '0';
-
-
-  signal Wait_clk         : INTEGER := 0;
-  signal Cnt_8_Clk        : std_logic_vector(2 downto 0):=(others => '1');
-
-  signal Counter          : std_logic_vector(5 downto 0):=(others => '0');
-  signal Addr_Cnt         : std_logic_vector(4 downto 0):=(others => '0');
-  signal Read_Addr        : std_logic_vector(4 downto 0):=(others => '1');
-
-
-  signal Data_From_Rx_FIFO  : std_logic_vector(0 to C_DATA_WIDTH-1):=(others => '0');
-  signal Transmit_Data      : std_logic_vector(0 to C_DATA_WIDTH-1):=(others => '0');
-
-  signal Read_Addr_Int,Count_Int  : INTEGER := 0;
-
-
-  type STATE_TYPE is (
-    IDLE,       -- decode command can be combined here later
-    WAIT_STATE,
-    READ
-  );
-  TYPE mem_array IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
-  SIGNAL ram : mem_array:= (
-    X"01",X"02",X"03",X"04",
-    X"05",X"06",X"07",X"08",
-    X"09",X"0A",X"0B",X"0C",
-    X"0D",X"0E",X"0F",X"10",
-    X"11",X"12",X"13",X"14",
-    X"15",X"16",X"17",X"18",
-    X"03",X"02",X"01",X"00",
-    X"FF",X"FF",X"FF",X"FF"
-  );
-
-
-
-  signal spi_cntrl_ns: STATE_TYPE;
-
-  attribute dont_touch : string;
-  attribute dont_touch of Serial_Dout_0   : signal is "TRUE";
-  attribute dont_touch of Serial_Dout_1   : signal is "TRUE";
-  attribute dont_touch of Serial_Dout_2   : signal is "TRUE";
-  attribute dont_touch of Serial_Dout_3   : signal is "TRUE";
-  attribute dont_touch of Count_Pulse     : signal is "TRUE";
-  attribute dont_touch of FIFO_RD_EN      : signal is "TRUE";
-  attribute dont_touch of ram             : signal is "TRUE";
-
-  attribute dont_touch of Count_Pulse_d   : signal is "TRUE";
-  attribute dont_touch of Wait_clk        : signal is "TRUE";
-  attribute dont_touch of Counter         : signal is "TRUE";
-  attribute dont_touch of Addr_Cnt        : signal is "TRUE";
-  attribute dont_touch of Read_Addr       : signal is "TRUE";
-  attribute dont_touch of Data_From_Rx_FIFO : signal is "TRUE";
-  attribute dont_touch of Transmit_Data   : signal is "TRUE";
-  attribute dont_touch of spi_cntrl_ns    : signal is "TRUE";
-
-  begin
-  Rising_falling_process: process(MODEL_CLK)is
-  -----
-  begin
-  -----
-    if(MODEL_CLK'event and MODEL_CLK = '1') then
-      if(MODEL_RESET = RESET_ACTIVE) then
-        SCK_D  <= '0';
-      else
-        SCK_D <= Core_Clk;
-      end if;
-    end if;
-  end process Rising_falling_process;
-
-  rising <= Core_Clk and (not(SCK_D));
-  falling <= SCK_D and (not(Core_Clk));
-
-
-
-  COUNTER_8_Cycles_Pos_PROCESS : process(MODEL_CLK)is
-  begin
-  -----
-    if(MODEL_CLK'event and MODEL_CLK = '1') then --1
-      if(MODEL_RESET = RESET_ACTIVE) then
-        Cnt_8_Clk <= (others => '1');
-      elsif (Chip_Selectn = '1') then
-        Cnt_8_Clk <= (others => '1');
-        elsif(rising = '1') then
-        Cnt_8_Clk <= Cnt_8_Clk + 1;
-        end if;
-      end if;
-  end process COUNTER_8_Cycles_Pos_PROCESS;
-
-  COUNTER_PROCESS : process(MODEL_CLK)is
-  begin
-  -----
-    if(MODEL_CLK'event and MODEL_CLK = '1') then --1
-      if(MODEL_RESET = RESET_ACTIVE) then
-        Counter <= (others => '1');
-      elsif (Chip_Selectn = '1') then
-        Counter <= (others => '1');
-        elsif (falling = '1') then
-        Counter <= Counter + 1;
-        end if;
-      end if;
-  end process COUNTER_PROCESS;
-
-  Count_Int <= CONV_INTEGER(Counter);
-
-  Wait_clk  <= Wait_std  WHEN (C_SPI_MODE = 0) ELSE
-            Wait_dual WHEN (C_SPI_MODE = 1) ELSE
-            Wait_quad ;
-
-  SPI_STATE_MACHINE_P: process(MODEL_CLK)
-  begin
-    if(MODEL_CLK'event and MODEL_CLK = '0') then   --1
-
-      --------------------------
-      case spi_cntrl_ns is
-        --------------------------
-        when IDLE =>
-          if(Chip_Selectn = '0') then
-            spi_cntrl_ns <= WAIT_STATE;
-          else
-            spi_cntrl_ns <= IDLE;
-          end if;
-          io0_t <= '1';
-          io1_t <= '0';
-          io2_t <= '0';
-          io3_t <= '0';
-        -------------------------------------
-        when WAIT_STATE =>
-          if(Chip_Selectn = '0') then
-            if (Count_Int = Wait_clk) then
-              spi_cntrl_ns <= READ;
-            else
-              spi_cntrl_ns <= WAIT_STATE;
-            end if;
-          else
-            spi_cntrl_ns <= IDLE;
-          end if;
-          io0_t <= '1';
-          io1_t <= '0';
-          io2_t <= '0';
-          io3_t <= '0';
-        -------------------------------------
-        when READ =>
-          if(Chip_Selectn = '0') then
-            spi_cntrl_ns <= READ;
-          else
-            spi_cntrl_ns <= IDLE;
-          end if;
-          io0_t <= '0';
-          io1_t <= '0';
-          io2_t <= '0';
-          io3_t <= '0';
-        when others =>
-          spi_cntrl_ns <= IDLE;
-          io0_t <= '1';
-          io1_t <= '0';
-          io2_t <= '0';
-          io3_t <= '0';
-        -------------------------------------
-      end case;
-    end if;
-  end process SPI_STATE_MACHINE_P;
-
-
-  Quad_Read_GENERATE : if (C_SPI_MODE = 2) generate
-    FIFO_READ_EN_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2
-        if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-          FIFO_RD_EN       <= '0';
-        elsif((spi_cntrl_ns = READ) and (falling = '1'))then
-          FIFO_RD_EN <= Cnt_8_Clk(0) ;
-        end if;
-      end if;
-    end process FIFO_READ_EN_PROCESS;
-
-    READ_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2
-        if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-          Read_Addr       <= (others => '1');
-          Data_From_Rx_FIFO       <= (others => '0');
-        elsif ((FIFO_RD_EN = '1') and (falling = '1')) then
-          Read_Addr       <= Read_Addr + 1;
-          Data_From_Rx_FIFO  <= ram(Read_Addr_Int) ;
-        end if;
-      end if;
-    end process READ_PROCESS;
-
-    Read_Addr_Int <= CONV_INTEGER(Read_Addr);
-
-    REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then
-        if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then
-          Transmit_Data <= (others => '0');
-        elsif ((FIFO_RD_EN = '1') and ( falling = '1'))then
-          Transmit_Data       <= Data_From_Rx_FIFO;
-        elsif (falling = '1') then
-          Transmit_Data <= Transmit_Data(4 to (C_DATA_WIDTH-1)) & "0000";
-        end if;
-      end if;
-    end process REGISTER_SHIFT_PROCESS;
-  end generate Quad_Read_GENERATE ;
-
-
-  Dual_Read_GENERATE : if (C_SPI_MODE = 1) generate
-    FIFO_READ_EN_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2
-        if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-          FIFO_RD_EN       <= '0';
-        elsif((spi_cntrl_ns = READ) and (falling = '1'))then
-          FIFO_RD_EN <= Cnt_8_Clk(0) and (not(Cnt_8_Clk(1)));--not(Cnt_8_Clk(0) or Cnt_8_Clk(1));
-        end if;
-      end if;
-    end process FIFO_READ_EN_PROCESS;
-
-
-    READ_PROCESS : process(MODEL_CLK)is
-      begin
-        if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2
-          if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-            Read_Addr       <= (others => '1');
-            Data_From_Rx_FIFO       <= (others => '0');
-          elsif ((FIFO_RD_EN = '1') and (falling = '1')) then
-            Read_Addr       <= Read_Addr + 1;
-            Data_From_Rx_FIFO  <= ram(Read_Addr_Int) ;
-          end if;
-        end if;
-      end process READ_PROCESS;
-
-    Read_Addr_Int <= CONV_INTEGER(Read_Addr);
-
-    REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then
-        if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then
-          Transmit_Data <= (others => '0');
-        elsif ((FIFO_RD_EN = '1') and (falling = '1'))then
-          Transmit_Data       <= Data_From_Rx_FIFO;
-        elsif (falling = '1') then
-          Transmit_Data <= Transmit_Data(2 to (C_DATA_WIDTH-1)) & "00";
-        end if;
-      end if;
-    end process REGISTER_SHIFT_PROCESS;
-  end generate Dual_Read_GENERATE ;
-
-
-  STD_Read_Process : if (C_SPI_MODE = 0) generate
-    FIFO_READ_EN_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then --SPIXfer_done_int_pulse_d2
-        if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-          FIFO_RD_EN       <= '0';
-        elsif((spi_cntrl_ns = READ) and (falling = '1'))then
-          FIFO_RD_EN <= Cnt_8_Clk(2) and Cnt_8_Clk(1) and Cnt_8_Clk(0) ;
-        end if;
-      end if;
-    end process FIFO_READ_EN_PROCESS;
-
-
-    READ_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then
-        if ((MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1'))then
-          Read_Addr       <= (others => '1');
-          Data_From_Rx_FIFO       <= (others => '0');
-        elsif ((FIFO_RD_EN = '1') and (falling = '1')) then
-          Read_Addr       <= Read_Addr + 1;
-          Data_From_Rx_FIFO  <= ram(Read_Addr_Int) ;
-        end if;
-      end if;
-    end process READ_PROCESS;
-
-    Read_Addr_Int <= CONV_INTEGER(Read_Addr);
-
-    REGISTER_SHIFT_PROCESS : process(MODEL_CLK)is
-    begin
-      if(MODEL_CLK'event and MODEL_CLK = '1') then
-        if (MODEL_RESET = RESET_ACTIVE) or (Chip_Selectn = '1')then
-          Transmit_Data <= (others => '0');
-        elsif ((FIFO_RD_EN = '1') and (falling = '1'))then
-          Transmit_Data       <= Data_From_Rx_FIFO;
-        elsif (falling = '1') then
-          Transmit_Data <= Transmit_Data(1 to (C_DATA_WIDTH-1)) & '0';
-        end if;
-      end if;
-    end process REGISTER_SHIFT_PROCESS;
-  end generate STD_Read_Process ;
-
-
-  FIFO_READ_PROCESS: process(MODEL_CLK) is
-  -----
-  begin
-  -----
-    if(MODEL_CLK'event and MODEL_CLK = '1') then
-      if((MODEL_RESET = RESET_ACTIVE)or (Chip_Selectn = '1')) then
-        Serial_Dout_0 <= '0';-- default values of the IO0_O
-        Serial_Dout_1 <= '0';
-        Serial_Dout_2 <= '0';
-        Serial_Dout_3 <= '0';
-      elsif (falling = '1') then
-        --if(spi_cntrl_ns = READ_DATA)then
-          --Shift_Reg   <= Transmit_Data;-- loading trasmit data in SR
-          if(C_SPI_MODE = 0) then    -- standard mode
-            Serial_Dout_1 <= Transmit_Data(0);
-          elsif(C_SPI_MODE = 1) then -- dual mode
-            Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
-            Serial_Dout_0 <= Transmit_Data(1);
-          elsif(C_SPI_MODE = 2) then -- quad mode
-            Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
-            Serial_Dout_2 <= Transmit_Data(1);
-            Serial_Dout_1 <= Transmit_Data(2);
-            Serial_Dout_0 <= Transmit_Data(3);
-          end if;
-        -- end if;
-      end if;
-    end if;
-  end process FIFO_READ_PROCESS;
-
-	io0_o <= Serial_Dout_0;
-	io1_o <= Serial_Dout_1;
-	io2_o <= Serial_Dout_2;
-	io3_o <= Serial_Dout_3;
-end imp;
diff --git a/ChiselProject/test/src/SyncRamSpec.scala b/ChiselProject/test/src/SyncRamSpec.scala
deleted file mode 100644
index cc907e0..0000000
--- a/ChiselProject/test/src/SyncRamSpec.scala
+++ /dev/null
@@ -1,41 +0,0 @@
-import chisel3._
-import chisel3.experimental.BundleLiterals._
-import chisel3.simulator.EphemeralSimulator._
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.must.Matchers
-
-
-class SyncRamSpec extends AnyFlatSpec {
-  behavior of "SyncRam"
-  it should "do something" in {
-    simulate(new SimRam) { dut =>
-      dut.reset.poke(true.B)
-      
-      for (i <- 0 until 10) {
-        dut.clock.step()
-      }
-      dut.reset.poke(false.B)
-
-      dut.io.waddr.poke(0x00000000.U)
-      dut.io.wstrb.poke(0x0F.U)
-      dut.io.wdata.poke(0xDEADBEEFL.U)
-      dut.clock.step()
-      dut.io.waddr.poke(0x00000000.U)
-      dut.io.wstrb.poke(0x00.U)
-      dut.io.wdata.poke(0x00000000.U)
-      dut.io.raddr.poke(0x00000000.U)
-      dut.clock.step()
-      dut.io.rdata.expect(0xDEADBEEFL.U)
-
-      dut.io.waddr.poke(0x00000004.U)
-      dut.io.wstrb.poke(0x0F.U)
-      dut.io.wdata.poke(0xDEADBEEFL.U)
-      dut.clock.step()
-      dut.io.waddr.poke(0x00000000.U)
-      dut.io.wdata.poke(0x00000000.U)
-      dut.io.raddr.poke(0x00000004.U)
-      dut.clock.step()
-      dut.io.rdata.expect(0x0000BEEFL.U)
-    }
-  }
-}
\ No newline at end of file
diff --git a/Makefile b/Makefile
index d8224b9..f823c74 100644
--- a/Makefile
+++ b/Makefile
@@ -1,22 +1,22 @@
 BUILD_DIR = ./generated-src
 
-PRJ = ChiselProject
-
-CONFIG ?= MinimalArty100T
+PACKAGE ?= vivado-ips
+DESIGN ?= vivadoips.MinimalArty100T
 
+MILL_PATH ?= ./toolchains/mill
 
 verilog:
 	mkdir -p $(BUILD_DIR)
-	mill -i $(PRJ).runMain GenerateVerilog --target-dir $(BUILD_DIR) --module-name $(CONFIG)
+	$(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildVerilog --target-dir $(BUILD_DIR) --design-name $(DESIGN)
 
 project: verilog
-	mill -i $(PRJ).runMain GenerateProject --target-dir $(BUILD_DIR) --module-name $(CONFIG)
+	$(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildProject --target-dir $(BUILD_DIR) --design-name $(DESIGN)
 
 bitstream: project
-	mill -i $(PRJ).runMain GenerateBitstream --target-dir $(BUILD_DIR) --module-name $(CONFIG)
+	$(MILL_PATH) -i package-$(PACKAGE).runMain builder.buildBitstream --target-dir $(BUILD_DIR) --design-name $(DESIGN)
 
 test:
-	mill -i $(PRJ).Test
+	$(MILL_PATH) -i package-$(PACKAGE).Test
 
 clean:
 	rm -rf $(BUILD_DIR)
diff --git a/README.md b/README.md
index 5ce76d1..9e4fd7f 100644
--- a/README.md
+++ b/README.md
@@ -1,15 +1,17 @@
 # MaDa
 
-## Install Mill
+## Getting Started
+
+This project uses Mill as the Scala build tool. A ready-to-run script is provided as `/toolchains/mill`. To invoke mill directly, do
 
 ```bash
-./scripts/install-mill.sh
+./toolchains/mill
 ```
 
-## Build Example
+The directory structure is organized in standalone packages. When running build flow, both the package name and the config name need to be provided:
 
 ```bash
-make verilog CONFIG=ExampleArty100TShell
+make verilog PACKAGE=delta-soc MODULE=delta.MlpPolicyRunner
 ```
 
 ## Build Bitstream
diff --git a/build.mill.scala b/build.mill.scala
index 9c078dd..fbbcab2 100644
--- a/build.mill.scala
+++ b/build.mill.scala
@@ -17,15 +17,11 @@ import mill.bsp._
 
 
 /**
- * Main build definition for the Chisel project.
- * This object defines the project structure and its dependencies.
+ * Common configuration trait for Chisel projects
  */
-object ChiselProject extends ScalaModule with ScalafmtModule { m =>
-  // Flag to switch between Chisel 3.x and Chisel 6.x
-  val useChisel3 = false
-
+trait ChiselModule extends ScalaModule with ScalafmtModule { m =>
   // Configure Scala version based on Chisel version
-  override def scalaVersion = if (useChisel3) "2.13.10" else "2.13.15"
+  override def scalaVersion = "2.13.16"
 
   // Scala compiler options
   override def scalacOptions = Seq(
@@ -36,19 +32,13 @@ object ChiselProject extends ScalaModule with ScalafmtModule { m =>
   )
 
   // Define Chisel dependencies based on version
-  override def ivyDeps = Agg(  
-    if (useChisel3)
-      ivy"edu.berkeley.cs::chisel3:3.6.0"
-    else
-      ivy"org.chipsalliance::chisel:6.7.0"
+  override def ivyDeps = Agg(
+    ivy"org.chipsalliance::chisel:7.0.0-RC1",
   )
 
   // Add Chisel compiler plugin
   override def scalacPluginIvyDeps = Agg(
-    if (useChisel3)
-      ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"
-    else
-      ivy"org.chipsalliance:::chisel-plugin:6.7.0"
+    ivy"org.chipsalliance:::chisel-plugin:7.0.0-RC1",
   )
 
   /**
@@ -58,19 +48,27 @@ object ChiselProject extends ScalaModule with ScalafmtModule { m =>
     // Add test dependencies
     override def ivyDeps = super.ivyDeps() ++ Agg(
       ivy"org.scalatest::scalatest::3.2.19",
-      if (useChisel3)
-        ivy"edu.berkeley.cs::chiseltest:0.6.0"
-      else
-        ivy"edu.berkeley.cs::chiseltest:6.0.0"
+      ivy"edu.berkeley.cs::chiseltest:6.0.0"
     )
   }
+}
 
-  // Configure additional Maven repositories for dependency resolution
-  def repositoriesTask = Task.Anon {
-    Seq(
-      coursier.MavenRepository("https://repo.scala-sbt.org/scalasbt/maven-releases"),
-      coursier.MavenRepository("https://oss.sonatype.org/content/repositories/releases"),
-      coursier.MavenRepository("https://oss.sonatype.org/content/repositories/snapshots")
-    ) ++ super.repositoriesTask()
-  }
+
+object builder extends ChiselModule
+
+object `package-amba` extends ChiselModule { m =>
+  override def moduleDeps = Seq(builder)
+}
+
+object `package-vivado-ips` extends ChiselModule { m =>
+  override def moduleDeps = Seq(builder, `package-amba`)
+}
+
+object `package-delta-soc` extends ChiselModule { m =>
+  override def moduleDeps = Seq(builder, `package-amba`, `package-vivado-ips`)
 }
+
+object `package-chipyard-wrapper` extends ChiselModule { m =>
+  override def moduleDeps = Seq(builder, `package-vivado-ips`)
+}
+
diff --git a/builder/src/Builder.scala b/builder/src/Builder.scala
new file mode 100644
index 0000000..36006e2
--- /dev/null
+++ b/builder/src/Builder.scala
@@ -0,0 +1,280 @@
+package builder
+
+/**
+ * Builder.scala
+ *
+ * This file is responsible for elaborating the Chisel design into SystemVerilog. It is the main entry point for
+ * generating the hardware description.
+ */
+
+import circt.stage.ChiselStage
+import scala.sys.process._
+import java.io.PrintWriter
+import java.io.File
+import java.io.FileFilter
+import java.io.FileWriter
+
+
+object BuilderConfig {
+  val chiselGeneratedFilelist = "generated-src/filelist.f"
+  val simulationFilelist = "generated-src/filelist_simulation.f"
+  val constraintsFilelist = "generated-src/filelist_constraints.f"
+  
+  val vivadoTclDir = "out/vivado-tcl"
+  val vivadoProjectDir = "out/vivado-project"
+}
+
+
+object addSimulationResource {
+  def apply(path: String): Unit = {
+    println(s"adding Simulation resource: $path")
+    val filelists = new File(BuilderConfig.simulationFilelist)
+    val writer = new PrintWriter(new FileWriter(filelists, true))
+    writer.println(path)
+    writer.close()
+  }
+}
+
+object addConstraintResource {
+  def apply(path: String): Unit = {
+    println(s"adding Constraint resource: $path")
+    val filelists = new File(BuilderConfig.constraintsFilelist)
+    val writer = new PrintWriter(new FileWriter(filelists, true))
+    writer.println(path)
+    writer.close()
+  }
+}
+
+object addVivadoTclScript {
+  def apply(path: String, content: String): Unit = {
+    println(s"adding Vivado TCL script: $path")
+    val file = new File(BuilderConfig.vivadoTclDir + "/" + path)
+
+    // ensure the directory exists
+    file.getParentFile.mkdirs()
+
+    val writer = new PrintWriter(new FileWriter(file))
+    writer.println(content)
+    writer.close()
+  }
+}
+
+object addVivadoIp {
+  def apply(
+    name: String,
+    vendor: String,
+    library: String,
+    version: String,
+    moduleName: String,
+    extra: String,
+    ): Unit = {
+    addVivadoTclScript(s"ip/create_ip_${moduleName.toLowerCase()}.tcl", {
+      s"""
+create_ip -name ${name} -vendor ${vendor} -library ${library} -version ${version} -module_name ${moduleName}
+generate_target {instantiation_template} [get_ips ${moduleName}]
+update_compile_order -fileset sources_1
+generate_target all [get_ips ${moduleName}]
+catch { config_ip_cache -export [get_ips -all ${moduleName}] }
+export_ip_user_files -of_objects [get_ips ${moduleName}] -no_script -sync -force -quiet
+create_ip_run [get_ips ${moduleName}]
+${extra}
+"""
+    })
+  }
+}
+
+
+
+// helper function to parse the module name from the arguments
+object _parseModuleName {
+  def apply(args: Array[String]): (String, Array[String]) = {
+    if (args.length < 1) {
+      println("Error: Please provide the module name as an argument")
+      System.exit(1)
+    }
+
+    args.sliding(2).zipWithIndex.collectFirst {
+      case (Array("--design-name", name), i) => (name, args.take(i) ++ args.drop(i + 2))
+    }.getOrElse {
+      println("Error: Please provide the design name with --design-name flag")
+      System.exit(1)
+      ("", Array.empty[String])  // This is never reached but needed for type inference
+    }
+  }
+}
+
+
+object buildVerilog extends App {
+  {
+    val simulationFilelist = new FileWriter(new File(BuilderConfig.simulationFilelist))
+    simulationFilelist.write("")
+    simulationFilelist.close()
+
+    val constraintsFilelist = new FileWriter(new File(BuilderConfig.constraintsFilelist))
+    constraintsFilelist.write("")
+    constraintsFilelist.close()
+  }
+  new File(BuilderConfig.vivadoProjectDir).mkdirs()
+  new File(BuilderConfig.vivadoTclDir).mkdirs()
+
+  val (designName, remainingArgs) = _parseModuleName(args)
+
+  val designClass = () => {
+    val design = Class.forName(designName)
+      .getDeclaredConstructor()
+      .newInstance()
+      .asInstanceOf[chisel3.RawModule]
+    design
+  }
+  val chiselOpts = remainingArgs ++ Array("--split-verilog")
+  val firtoolOpts = Array(
+    "-disable-all-randomization",
+    "-strip-debug-info",
+  )
+
+  ChiselStage.emitSystemVerilogFile(
+    gen=designClass(),
+    args=chiselOpts,
+    firtoolOpts=firtoolOpts
+  )
+}
+
+object buildProject extends App {
+  val (designName, remainingArgs) = _parseModuleName(args)
+
+  new File(BuilderConfig.vivadoProjectDir).mkdirs()
+  new File(BuilderConfig.vivadoTclDir).mkdirs()
+
+  /* Arty A7 100T */
+  // val fpgaPart = "xc7a100ticsg324-1L"
+  // val boardPart = "digilentinc.com:arty-a7-100t:part0:1.1"
+
+  /* Arty A7 35T */
+  val fpgaPart = "xc7a35ticsg324-1L"
+  val boardPart = "digilentinc.com:arty-a7-35:part0:1.1"
+
+  /* Zedboard */
+  // val fpgaPart = "xc7z020clg484-1"
+  // val boardPart = "digilentinc.com:zedboard:part0:1.1"
+
+  // HACK: the blackboxed sources are not included in the filelist.f, so we need to instead scan for the entire generated-src directory
+  // val chiselGeneratedSources = scala.io.Source.fromFile(new File(BuilderConfig.chiselGeneratedFilelist))
+  //   .getLines()
+  //   .map(_.trim)
+  //   .filter(_.nonEmpty)
+  //   .map(line => s"generated-src/${line}")
+  //   .toList
+  val chiselGeneratedSources = new File("generated-src").listFiles(new FileFilter {
+    def accept(file: File): Boolean = file.isFile || file.isDirectory && !file.getName.endsWith(".f")
+  }).flatMap(file => if (file.isDirectory) file.listFiles().map(_.getAbsolutePath) else Array(file.getAbsolutePath))
+
+  val simulationSources = scala.io.Source.fromFile(new File(BuilderConfig.simulationFilelist))
+    .getLines()
+    .map(_.trim)
+    .filter(_.nonEmpty)
+  val constraintResources = scala.io.Source.fromFile(new File(BuilderConfig.constraintsFilelist))
+    .getLines()
+    .map(_.trim)
+    .filter(_.nonEmpty)
+
+
+  {
+    // create a run.tcl file
+    val runTcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/create_project.tcl")
+
+    // create project
+    runTcl.println(s"create_project VivadoProject ${BuilderConfig.vivadoProjectDir} -part ${fpgaPart} -force")
+    // run_tcl.println(s"set_property board_part $board_part [current_project]")
+    
+    // add constraints
+    if (constraintResources.nonEmpty) {
+      runTcl.print(s"add_files -fileset constrs_1 {")
+      constraintResources.foreach(filepath => {
+        runTcl.println(s" ${filepath} \\")
+      })
+      runTcl.println("}")
+    }
+
+    // add sources
+    runTcl.print(s"add_files")
+    chiselGeneratedSources.foreach(filepath => {
+      runTcl.println(s" ${filepath} \\")
+    })
+    runTcl.println("")
+
+    if (simulationSources.nonEmpty) {
+      runTcl.print(s"add_files -fileset sim_1 {")
+      simulationSources.foreach(filepath => {
+        runTcl.println(s" ${filepath} \\")
+      })
+      runTcl.println("}")
+    }
+
+    val designClassName = designName.split("\\.").last
+    runTcl.println(s"set_property top ${designClassName} [current_fileset]")
+
+    /* create Vivado IPs */
+    runTcl.println("update_ip_catalog")
+
+    val create_ip_files = new File(BuilderConfig.vivadoTclDir + "/ip").listFiles(new FileFilter {
+      def accept(file: File): Boolean = file.isFile
+    }).map(_.getAbsolutePath)
+
+    create_ip_files.foreach(file => {
+      runTcl.println(s"source ${file}")
+    })
+
+
+    // configure simulation settings    
+    runTcl.println(s"update_compile_order -fileset sources_1")
+    runTcl.println(s"set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]")
+    runTcl.println(s"set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]")
+    runTcl.println(s"set_property top ${designClassName}Testbench [get_filesets sim_1]")
+    // run_tcl.println(s"set_property top_lib xil_defaultlib [get_filesets sim_1]")
+
+    runTcl.println(s"close_project")
+
+    runTcl.close()
+    runTcl.flush()
+  }
+
+
+  s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/create_project.tcl".!
+}
+
+object buildBitstream extends App {
+  val (designName, remainingArgs) = _parseModuleName(args)
+
+  {
+    // create a generate_bitstream.tcl file
+    val run_tcl = new PrintWriter(s"${BuilderConfig.vivadoTclDir}/generate_bitstream.tcl")
+
+    run_tcl.println(s"open_project ${BuilderConfig.vivadoProjectDir}/VivadoProject.xpr")
+
+    // val ip_name = "clk_wiz_0"
+
+    // run_tcl.println(s"reset_run ${ip_name}_synth_1")
+    // run_tcl.println(s"launch_runs ${ip_name}_synth_1")
+
+    // run_tcl.println(s"wait_on_run ${ip_name}_synth_1")
+
+    // run_tcl.println(s"reset_run synth_1")
+    // run_tcl.println(s"launch_runs synth_1 -jobs 8")
+
+    // run_tcl.println(s"wait_on_run synth_1")
+
+    run_tcl.println(s"update_compile_order -fileset sources_1")
+    run_tcl.println(s"launch_runs impl_1 -to_step write_bitstream -jobs 8")
+    run_tcl.println(s"wait_on_run impl_1")
+
+    run_tcl.println(s"open_run impl_1")
+    run_tcl.println(s"write_bitstream ${BuilderConfig.vivadoTclDir}/Arty100TShell.bit -force")
+
+    run_tcl.println(s"close_project")
+    
+    run_tcl.close()
+    run_tcl.flush()   // make sure the file is written to the disk
+  }
+
+  s"vivado -mode batch -source ${BuilderConfig.vivadoTclDir}/generate_bitstream.tcl".!
+}
diff --git a/env.sh b/env.sh
deleted file mode 100644
index 66f33fb..0000000
--- a/env.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-TOOLCHAIN_DIR="$PWD/toolchains"
-
-# Add toolchains to PATH
-export PATH="$TOOLCHAIN_DIR:$PATH"
-
-export RISCV="/scratch/tk/Documents/RISCV/"
-export PATH="$RISCV/riscv64-unknown-toolchain/bin/:$PATH"
diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4Bundles.scala b/package-amba/src/Axi4Bundles.scala
similarity index 99%
rename from ChiselProject/src/generators/xilinx/bundle/Axi4Bundles.scala
rename to package-amba/src/Axi4Bundles.scala
index 5dc6fac..063536d 100644
--- a/ChiselProject/src/generators/xilinx/bundle/Axi4Bundles.scala
+++ b/package-amba/src/Axi4Bundles.scala
@@ -1,3 +1,5 @@
+package amba
+
 /**
   * Axi4Bundle.scala
   * 
diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4Params.scala b/package-amba/src/Axi4Params.scala
similarity index 95%
rename from ChiselProject/src/generators/xilinx/bundle/Axi4Params.scala
rename to package-amba/src/Axi4Params.scala
index 23b3524..b45a307 100644
--- a/ChiselProject/src/generators/xilinx/bundle/Axi4Params.scala
+++ b/package-amba/src/Axi4Params.scala
@@ -1,3 +1,5 @@
+package amba
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/chipyard/DigitalTop.scala b/package-chipyard-wrapper/src/DigitalTop.scala
similarity index 97%
rename from ChiselProject/src/generators/chipyard/DigitalTop.scala
rename to package-chipyard-wrapper/src/DigitalTop.scala
index 35b4e81..759a802 100644
--- a/ChiselProject/src/generators/chipyard/DigitalTop.scala
+++ b/package-chipyard-wrapper/src/DigitalTop.scala
@@ -1,8 +1,9 @@
+package chipyardwrapper
+
 import chisel3.{BlackBox, _}
 import chisel3.util._
 
 
-
 class DigitalTop extends BlackBox {
   val io = IO(new Bundle {
     val auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock = Input(Clock())
diff --git a/ChiselProject/src/examples/MotorArty100T.scala b/package-chipyard-wrapper/src/MotorArty100T.scala
similarity index 99%
rename from ChiselProject/src/examples/MotorArty100T.scala
rename to package-chipyard-wrapper/src/MotorArty100T.scala
index 71256ad..23b20d0 100644
--- a/ChiselProject/src/examples/MotorArty100T.scala
+++ b/package-chipyard-wrapper/src/MotorArty100T.scala
@@ -1,3 +1,5 @@
+package chipyardwrapper
+
 // import chisel3._
 // import chisel3.util._
 
diff --git a/ChiselProject/src/examples/TinyRocketArty100T.scala b/package-chipyard-wrapper/src/TinyRocketArty100T.scala
similarity index 97%
rename from ChiselProject/src/examples/TinyRocketArty100T.scala
rename to package-chipyard-wrapper/src/TinyRocketArty100T.scala
index 73b78fc..22706af 100644
--- a/ChiselProject/src/examples/TinyRocketArty100T.scala
+++ b/package-chipyard-wrapper/src/TinyRocketArty100T.scala
@@ -1,3 +1,5 @@
+package chipyardwrapper
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/examples/UdpTinyRocketArty100T.scala b/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala
similarity index 99%
rename from ChiselProject/src/examples/UdpTinyRocketArty100T.scala
rename to package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala
index e4774ae..e60252c 100644
--- a/ChiselProject/src/examples/UdpTinyRocketArty100T.scala
+++ b/package-chipyard-wrapper/src/UdpTinyRocketArty100T.scala
@@ -1,3 +1,5 @@
+package chipyardwrapper
+
 // import chisel3._
 // import chisel3.util._
 
diff --git a/ChiselProject/resources/verilog/AsyncRam.v b/package-delta-soc/resources/verilog/AsyncRam.v
similarity index 100%
rename from ChiselProject/resources/verilog/AsyncRam.v
rename to package-delta-soc/resources/verilog/AsyncRam.v
diff --git a/ChiselProject/resources/verilog/Ram.v b/package-delta-soc/resources/verilog/Ram.v
similarity index 100%
rename from ChiselProject/resources/verilog/Ram.v
rename to package-delta-soc/resources/verilog/Ram.v
diff --git a/ChiselProject/test/resources/verilog/components/SimSpiFlashModel.sv b/package-delta-soc/resources/verilog/SimSpiFlashModel.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/components/SimSpiFlashModel.sv
rename to package-delta-soc/resources/verilog/SimSpiFlashModel.sv
diff --git a/ChiselProject/test/resources/verilog/components/SimUart.sv b/package-delta-soc/resources/verilog/SimUart.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/components/SimUart.sv
rename to package-delta-soc/resources/verilog/SimUart.sv
diff --git a/ChiselProject/test/resources/verilog/components/SpiFlashMemCtrl.sv b/package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/components/SpiFlashMemCtrl.sv
rename to package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv
diff --git a/ChiselProject/src/examples/MlpPolicyRunner.scala b/package-delta-soc/src/MlpPolicyRunnerBase.scala
similarity index 81%
rename from ChiselProject/src/examples/MlpPolicyRunner.scala
rename to package-delta-soc/src/MlpPolicyRunnerBase.scala
index cad2908..0bc748b 100644
--- a/ChiselProject/src/examples/MlpPolicyRunner.scala
+++ b/package-delta-soc/src/MlpPolicyRunnerBase.scala
@@ -1,8 +1,25 @@
+package delta
+
 import chisel3._
 import chisel3.util._
-
-
-
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import vivadoips.{
+  Arty100TIO,
+  Axi4Crossbar,
+  Axi4DataWidthConverter,
+  Axi4LiteCrossbar,
+  Axi4LiteTimer,
+  Axi4LiteTimerConfig,
+  Axi4LiteUartLite,
+  Axi4LiteUartLiteConfig,
+  Axi4LiteGpio,
+  Axi4QuadSpiFlash,
+  Axi4SpiFlash,
+  ClockingWizard,
+  IOBUF,
+  SyncReset,
+}
+import builder.{addConstraintResource, addSimulationResource}
 
 
 /**
@@ -20,10 +37,13 @@ import chisel3.util._
   * 0x0800_0000 - 0x0800_3FFF: scratchpad (16 kB)
   * 
   */
-class MlpPolicyRunner extends RawModule {
-  val io = IO(new Arty100TIO())
 
-  val systemClockFrequency = 50
+case class SoCConfig(
+  tile: TileConfig = new TileConfig(sbusFrequency=50),
+)
+
+class MlpPolicyRunnerBase(val config: SoCConfig) extends RawModule {
+  val io = IO(new Arty100TIO())
 
   io := DontCare
 
@@ -32,7 +52,7 @@ class MlpPolicyRunner extends RawModule {
   
   val pll_locked = Wire(Bool())
 
-  val clk_wiz = Module(new ClockingWizard(Seq(systemClockFrequency)))
+  val clk_wiz = Module(new ClockingWizard(Seq(config.tile.sbusFrequency)))
   // clocking wizard connection
   clk_wiz.io.clk_in := io.CLK100MHZ
   clk_wiz.io.reset := ~io.ck_rst
@@ -50,7 +70,7 @@ class MlpPolicyRunner extends RawModule {
   withClockAndReset(clock, reset) {
     val reset_vector = RegInit(0x0800_0000.U(32.W))
 
-    val tile = Module(new Tile(sbusFrequency=systemClockFrequency))
+    val tile = Module(new Tile(config.tile))
 
     tile.io.reset_vector := reset_vector
 
@@ -77,8 +97,8 @@ class MlpPolicyRunner extends RawModule {
     // val spi = Module(new Axi4SpiFlash())
 
     val gpio = Module(new Axi4LiteGpio())
-    val uart = Module(new Axi4LiteUartLite(axiClockFrequency=systemClockFrequency))
-    val timer = Module(new Axi4LiteTimer())
+    val uart = Module(new Axi4LiteUartLite(Axi4LiteUartLiteConfig(axiClockFrequency=config.tile.sbusFrequency)))
+    val timer = Module(new Axi4LiteTimer(Axi4LiteTimerConfig(timerCounterWidth=32)))
 
     pbus_crossbar.io.s_axi(0).connectFromAxi4(tile.io.pbus)
 
@@ -110,9 +130,7 @@ class MlpPolicyRunner extends RawModule {
     dontTouch(tile.io.sbus.ar.bits.burst)
 
 
-    // io.qspi_sck := spi.io.sck_o.asClock
     io.qspi_cs := spi.io.ss_o
-    // spi.io.sck_i := 0.B
     spi.io.ss_i := 0.B
 
     val qspi_io0_buf = Module(new IOBUF())
diff --git a/ChiselProject/src/generators/delta/TestTiles.scala b/package-delta-soc/src/TestTiles.scala
similarity index 89%
rename from ChiselProject/src/generators/delta/TestTiles.scala
rename to package-delta-soc/src/TestTiles.scala
index 56daa8b..7516dfd 100644
--- a/ChiselProject/src/generators/delta/TestTiles.scala
+++ b/package-delta-soc/src/TestTiles.scala
@@ -1,5 +1,9 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import vivadoips.{Axi4Crossbar, Axi4BlockMemory}
 
 
 class EECS151Tile extends Module {
@@ -8,7 +12,7 @@ class EECS151Tile extends Module {
     val debug = new DebugIO()
   })
 
-  val core = Module(new Core(nVectors=1))
+  val core = Module(new Core(CoreConfig(VLEN=32, ELEN=32)))
 
   // instruction memory must be a synchronous 1 cycle read delay memory
   val itim = Module(new Axi4MemoryWithLatency(
@@ -45,7 +49,7 @@ class EECS252Tile extends Module {
     val debug = new DebugIO()
   })
 
-  val core = Module(new Core(nVectors=2))
+  val core = Module(new Core(CoreConfig(VLEN=64, ELEN=32)))
 
   val xbar = Module(new Axi4Crossbar(
     2, 1,
diff --git a/ChiselProject/src/generators/delta/Tile.scala b/package-delta-soc/src/Tile.scala
similarity index 84%
rename from ChiselProject/src/generators/delta/Tile.scala
rename to package-delta-soc/src/Tile.scala
index 6bceba6..c67f133 100644
--- a/ChiselProject/src/generators/delta/Tile.scala
+++ b/package-delta-soc/src/Tile.scala
@@ -1,9 +1,18 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import vivadoips.{Axi4Crossbar, Axi4BlockMemory, Axi4DataWidthConverter}
+
 
+case class TileConfig(
+  core: CoreConfig = new CoreConfig(),
+  sbusFrequency: Int = 20,
+)
 
 class Tile(
-  val sbusFrequency: Int = 20,
+  val config: TileConfig = TileConfig()
 ) extends Module {
   val io = IO(new Bundle {
     val reset_vector = Input(UInt(32.W))
@@ -16,11 +25,14 @@ class Tile(
   dontTouch(io.reset_vector)
   dontTouch(io.debug)
 
-  val busWidth = 64
+  val busWidth = config.core.VLEN
 
   val core = Module(new Core(
-    nVectors=busWidth/32,
-    pipelineStages=3,
+    CoreConfig(
+      VLEN=config.core.VLEN,
+      ELEN=config.core.ELEN,
+      pipelineStages=config.core.pipelineStages,
+    )
   ))
 
   val itim = Module(new Axi4Memory(
diff --git a/ChiselProject/src/generators/delta/constants/Constants.scala b/package-delta-soc/src/constants/Constants.scala
similarity index 99%
rename from ChiselProject/src/generators/delta/constants/Constants.scala
rename to package-delta-soc/src/constants/Constants.scala
index 99a538e..2c485a0 100644
--- a/ChiselProject/src/generators/delta/constants/Constants.scala
+++ b/package-delta-soc/src/constants/Constants.scala
@@ -1,3 +1,4 @@
+package delta
 
 import chisel3._
 import chisel3.util._
diff --git a/ChiselProject/src/generators/delta/constants/Instructions.scala b/package-delta-soc/src/constants/Instructions.scala
similarity index 99%
rename from ChiselProject/src/generators/delta/constants/Instructions.scala
rename to package-delta-soc/src/constants/Instructions.scala
index 7fb511f..9d800f3 100644
--- a/ChiselProject/src/generators/delta/constants/Instructions.scala
+++ b/package-delta-soc/src/constants/Instructions.scala
@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+package delta
 
 import chisel3._
 import chisel3.util._
diff --git a/ChiselProject/src/generators/delta/core/ALU.scala b/package-delta-soc/src/core/ALU.scala
similarity index 84%
rename from ChiselProject/src/generators/delta/core/ALU.scala
rename to package-delta-soc/src/core/ALU.scala
index e9b03f6..72d3ae2 100644
--- a/ChiselProject/src/generators/delta/core/ALU.scala
+++ b/package-delta-soc/src/core/ALU.scala
@@ -1,3 +1,5 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 
@@ -5,13 +7,13 @@ import Instructions._
 import ScalarControlConstants._
 
 
-class ALU extends Module {
+class ALU(val XLEN: Int = 32) extends Module {
   val io = IO(new Bundle {
-    val op1 = Input(UInt(32.W))
-    val op2 = Input(UInt(32.W))
+    val op1 = Input(UInt(XLEN.W))
+    val op2 = Input(UInt(XLEN.W))
     val func = Input(UInt(ALU_X.getWidth.W))
 
-    val out = Output(UInt(32.W))
+    val out = Output(UInt(XLEN.W))
   })
 
 
@@ -25,7 +27,7 @@ class ALU extends Module {
                   (io.func === ALU_XOR)  -> (io.op1 ^ io.op2).asUInt,
                   (io.func === ALU_SLT)  -> (io.op1.asSInt < io.op2.asSInt).asUInt,
                   (io.func === ALU_SLTU) -> (io.op1 < io.op2).asUInt,
-                  (io.func === ALU_SLL)  -> ((io.op1 << alu_shamt)(31, 0)).asUInt,
+                  (io.func === ALU_SLL)  -> ((io.op1 << alu_shamt)(XLEN-1, 0)).asUInt,
                   (io.func === ALU_SRA)  -> (io.op1.asSInt >> alu_shamt).asUInt,
                   (io.func === ALU_SRL)  -> (io.op1 >> alu_shamt).asUInt,
                   (io.func === ALU_COPY) -> (io.op1).asUInt
diff --git a/ChiselProject/src/generators/delta/core/CSR.scala b/package-delta-soc/src/core/CSR.scala
similarity index 81%
rename from ChiselProject/src/generators/delta/core/CSR.scala
rename to package-delta-soc/src/core/CSR.scala
index d24707e..1f1c0e3 100644
--- a/ChiselProject/src/generators/delta/core/CSR.scala
+++ b/package-delta-soc/src/core/CSR.scala
@@ -1,3 +1,5 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 
@@ -37,35 +39,35 @@ object CsrAddress {
   val MHARTID   = 0xF14.U
 }
 
-class CSR extends Module {
+class CSR(val XLEN: Int = 32) extends Module {
   val io = IO(new Bundle {
     val addr = Input(UInt(12.W))
     val command = Input(UInt(3.W))
-    val in_data = Input(UInt(32.W))
-    val out_data = Output(UInt(32.W))
+    val in_data = Input(UInt(XLEN.W))
+    val out_data = Output(UInt(XLEN.W))
     
     val retire = Input(Bool())
 
     // debug interface
     val debug = new Bundle {
-      val syscall0 = Output(UInt(32.W))
-      val syscall1 = Output(UInt(32.W))
-      val syscall2 = Output(UInt(32.W))
-      val syscall3 = Output(UInt(32.W))
-      val sysresp0 = Input(UInt(32.W))
-      val sysresp1 = Input(UInt(32.W))
-      val sysresp2 = Input(UInt(32.W))
-      val sysresp3 = Input(UInt(32.W))
+      val syscall0 = Output(UInt(XLEN.W))
+      val syscall1 = Output(UInt(XLEN.W))
+      val syscall2 = Output(UInt(XLEN.W))
+      val syscall3 = Output(UInt(XLEN.W))
+      val sysresp0 = Input(UInt(XLEN.W))
+      val sysresp1 = Input(UInt(XLEN.W))
+      val sysresp2 = Input(UInt(XLEN.W))
+      val sysresp3 = Input(UInt(XLEN.W))
     }
   })
 
 
-  val reg_csr_syscall0 = RegInit(0.U(32.W))
-  val reg_csr_syscall1 = RegInit(0.U(32.W))
-  val reg_csr_syscall2 = RegInit(0.U(32.W))
-  val reg_csr_syscall3 = RegInit(0.U(32.W))
-  val reg_csr_mcycle = RegInit(0.U(32.W))
-  val reg_csr_minstret = RegInit(0.U(32.W))
+  val reg_csr_syscall0 = RegInit(0.U(XLEN.W))
+  val reg_csr_syscall1 = RegInit(0.U(XLEN.W))
+  val reg_csr_syscall2 = RegInit(0.U(XLEN.W))
+  val reg_csr_syscall3 = RegInit(0.U(XLEN.W))
+  val reg_csr_mcycle = RegInit(0.U(XLEN.W))
+  val reg_csr_minstret = RegInit(0.U(XLEN.W))
   
 
   switch (io.addr) {
diff --git a/ChiselProject/src/generators/delta/core/Core.scala b/package-delta-soc/src/core/Core.scala
similarity index 92%
rename from ChiselProject/src/generators/delta/core/Core.scala
rename to package-delta-soc/src/core/Core.scala
index e1ace6c..e92971d 100644
--- a/ChiselProject/src/generators/delta/core/Core.scala
+++ b/package-delta-soc/src/core/Core.scala
@@ -1,5 +1,8 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
 
 import CsrControlConstants._
 import RiscvConstants._
@@ -29,18 +32,26 @@ class DebugIO extends Bundle() {
 }
 
 
-class Core(
-  nVectors: Int = 1,
+case class CoreConfig(
+  XLEN: Int = 32,
+  ELEN: Int = 32,
+  VLEN: Int = 64,
   pipelineStages: Int = 1,
+)
+
+class Core(
+  val config: CoreConfig = CoreConfig()
 ) extends Module {
   val io = IO(new Bundle {
     val reset_vector = Input(UInt(32.W))
 
     val imem = new Axi4LiteBundle()
     val dmem = new Axi4Bundle()
-    val vdmem = new Axi4Bundle(params=Axi4Params(dataWidth=nVectors*32))
+    val vdmem = new Axi4Bundle(params=Axi4Params(dataWidth=config.VLEN))
     val debug = new DebugIO()
   })
+
+  val numVectors = config.VLEN / config.ELEN
   
   val exception = Wire(Bool())
   exception := false.B
@@ -69,9 +80,9 @@ class Core(
   val if_exception_target = Wire(UInt(32.W))
 
 
-  val ex_wb_data = Wire(UInt(32.W))
+  val ex_wb_data = Wire(UInt(config.XLEN.W))
 
-  val ex_vwb_data = Wire(Vec(nVectors, UInt(32.W)))
+  val ex_vwb_data = Wire(Vec(numVectors, UInt(config.ELEN.W)))
 
 
   val ifu = Module(new InstructionFetch())
@@ -233,7 +244,7 @@ class Core(
 
 
   // Vector Register File
-  val vregfile = Mem(32, Vec(nVectors, UInt(32.W)))
+  val vregfile = Mem(32, Vec(numVectors, UInt(config.ELEN.W)))
 
   when(ex_vwb_en) {
     vregfile(rd_addr) := ex_vwb_data
@@ -244,7 +255,7 @@ class Core(
   val vrd_data = vregfile(rd_addr)
 
 
-  val valu = Module(new SimdFloatingPoint(nVectors=nVectors, pipelineStages=pipelineStages))
+  val valu = Module(new SimdFloatingPoint(ELEN=config.ELEN, VLEN=config.VLEN, pipelineStages=config.pipelineStages))
   // result = a * b + c
 
   valu.io.func := ctrl.valu_func
@@ -263,7 +274,7 @@ class Core(
   lsu.io.dmem <> io.dmem
 
 
-  val vlsu = Module(new SimdLoadStore(nVectors=nVectors))
+  val vlsu = Module(new SimdLoadStore(nVectors=numVectors))
 
   vlsu.io.mem_func := Mux(ifu.io.ex.valid, ctrl.vmem_func, M_X)
   vlsu.io.strided := ctrl.vmem_stride
@@ -293,7 +304,7 @@ class Core(
               (ctrl.wb_sel === WB_CSR) -> csr.io.out_data
   ))
 
-  ex_vwb_data := MuxCase(VecInit.fill(nVectors)(0.U(32.W)), Seq(
+  ex_vwb_data := MuxCase(VecInit.fill(numVectors)(0.U(config.ELEN.W)), Seq(
               (ctrl.vwb_sel === WB_ALU) -> valu.io.out,
               (ctrl.vwb_sel === WB_MEM) -> vlsu.io.rdata,
   ))
diff --git a/ChiselProject/src/generators/delta/core/InstructionDecode.scala b/package-delta-soc/src/core/InstructionDecode.scala
similarity index 99%
rename from ChiselProject/src/generators/delta/core/InstructionDecode.scala
rename to package-delta-soc/src/core/InstructionDecode.scala
index 824dec7..90bdfee 100644
--- a/ChiselProject/src/generators/delta/core/InstructionDecode.scala
+++ b/package-delta-soc/src/core/InstructionDecode.scala
@@ -1,3 +1,5 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/delta/core/InstructionFetch.scala b/package-delta-soc/src/core/InstructionFetch.scala
similarity index 98%
rename from ChiselProject/src/generators/delta/core/InstructionFetch.scala
rename to package-delta-soc/src/core/InstructionFetch.scala
index 38fa368..b61d4c3 100644
--- a/ChiselProject/src/generators/delta/core/InstructionFetch.scala
+++ b/package-delta-soc/src/core/InstructionFetch.scala
@@ -1,5 +1,8 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4LiteBundle}
 
 import CsrControlConstants._
 import Instructions._
diff --git a/ChiselProject/src/generators/delta/core/LoadStore.scala b/package-delta-soc/src/core/LoadStore.scala
similarity index 94%
rename from ChiselProject/src/generators/delta/core/LoadStore.scala
rename to package-delta-soc/src/core/LoadStore.scala
index ba88569..be985ec 100644
--- a/ChiselProject/src/generators/delta/core/LoadStore.scala
+++ b/package-delta-soc/src/core/LoadStore.scala
@@ -1,27 +1,30 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst}
 
 import Instructions._
 import ScalarControlConstants._
 
 
-class LoadStore extends Module {
+class LoadStore(val XLEN: Int = 32) extends Module {
   val io = IO(new Bundle {
     val mem_func = Input(UInt(M_X.getWidth.W))
 
     val ctl_dmem_mask_sel = Input(UInt(MSK_X.getWidth.W))
     val ctl_dmem_signed = Input(Bool())
 
-    val addr = Input(UInt(32.W))
-    val wdata = Input(UInt(32.W))
-    val rdata = Output(UInt(32.W))
+    val addr = Input(UInt(XLEN.W))
+    val wdata = Input(UInt(XLEN.W))
+    val rdata = Output(UInt(XLEN.W))
 
     val busy = Output(Bool())
     
     val dmem = new Axi4Bundle()
   })
 
-  
+  assert(XLEN == 32, "Currently only 32-bit (XLEN = 32) is supported")
 
   val reg_aw_pending = RegInit(false.B)
   val reg_w_pending = RegInit(false.B)
diff --git a/ChiselProject/src/generators/delta/core/SimdFloatingPoint.scala b/package-delta-soc/src/core/SimdFloatingPoint.scala
similarity index 68%
rename from ChiselProject/src/generators/delta/core/SimdFloatingPoint.scala
rename to package-delta-soc/src/core/SimdFloatingPoint.scala
index 23752fc..0cac82c 100644
--- a/ChiselProject/src/generators/delta/core/SimdFloatingPoint.scala
+++ b/package-delta-soc/src/core/SimdFloatingPoint.scala
@@ -1,25 +1,35 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import vivadoips.{FloatingPoint, FloatingPointConfig}
 
 import Instructions._
 import SimdControlConstants._
 
 
 class SimdFloatingPoint(
-  nVectors: Int = 1,
+  val ELEN: Int = 32,
+  val VLEN: Int = 64,
   pipelineStages: Int = 1,
-) extends Module {
+  ) extends Module {
+  
+  val numVectors = VLEN / ELEN
+
   val io = IO(new Bundle {
-    val op1 = Input(Vec(nVectors, UInt(32.W)))
-    val op2 = Input(Vec(nVectors, UInt(32.W)))
-    val op3 = Input(Vec(nVectors, UInt(32.W)))
+    val op1 = Input(Vec(numVectors, UInt(ELEN.W)))
+    val op2 = Input(Vec(numVectors, UInt(ELEN.W)))
+    val op3 = Input(Vec(numVectors, UInt(ELEN.W)))
     val func = Input(UInt(SIMD_X.getWidth.W))
 
-    val out = Output(Vec(nVectors, UInt(32.W)))
+    val out = Output(Vec(numVectors, UInt(ELEN.W)))
     val busy = Output(Bool())
   })
 
-  val fmacc = Array.fill(nVectors)(Module(new FloatingPoint(pipelineStages=pipelineStages)))
+  assert(ELEN == 32, "Currently only 32-bit (ELEN = 32) is supported")
+  assert(VLEN == 64 || VLEN == 128 || VLEN == 256, "Currently only 64-bit, 128-bit and 256-bit (VLEN = {64, 128, 256}) is supported")
+
+  val fmacc = Array.fill(numVectors)(Module(new FloatingPoint(FloatingPointConfig(pipelineStages=pipelineStages))))
 
   val one = 0x3F800000.U(32.W)
   val zero = 0x00000000.U(32.W)
@@ -42,16 +52,16 @@ class SimdFloatingPoint(
 
 
   // EX 2 stage pipeline registers
-  val ex2_reg_op_a = Reg(Vec(nVectors, UInt(32.W)))
-  val ex2_reg_op_b = Reg(Vec(nVectors, UInt(32.W)))
-  val ex2_reg_op_c = Reg(Vec(nVectors, UInt(32.W)))
+  val ex2_reg_op_a = Reg(Vec(numVectors, UInt(ELEN.W)))
+  val ex2_reg_op_b = Reg(Vec(numVectors, UInt(ELEN.W)))
+  val ex2_reg_op_c = Reg(Vec(numVectors, UInt(ELEN.W)))
   
   val ex2_reg_op_rs2 = RegNext(io.op2)
   val ex2_reg_func = RegNext(io.func)
   val ex2_reg_valid = RegNext(input_valid)
 
 
-  for (i <- 0 until nVectors) {
+  for (i <- 0 until numVectors) {
     when(io.func === SIMD_ADD) {
       ex2_reg_op_a(i) := io.op1(i)
       ex2_reg_op_b(i) := one
@@ -78,7 +88,7 @@ class SimdFloatingPoint(
 
   val ex2_op2_positive = ex2_reg_op_rs2.map(x => x(31) === 0.U)
 
-  for (i <- 0 until nVectors) {
+  for (i <- 0 until numVectors) {
     fmacc(i).io.a.valid := ex2_reg_valid
     fmacc(i).io.b.valid := ex2_reg_valid
     fmacc(i).io.c.valid := ex2_reg_valid
diff --git a/ChiselProject/src/generators/delta/core/SimdLoadStore.scala b/package-delta-soc/src/core/SimdLoadStore.scala
similarity index 97%
rename from ChiselProject/src/generators/delta/core/SimdLoadStore.scala
rename to package-delta-soc/src/core/SimdLoadStore.scala
index 122c5e3..76bce00 100644
--- a/ChiselProject/src/generators/delta/core/SimdLoadStore.scala
+++ b/package-delta-soc/src/core/SimdLoadStore.scala
@@ -1,5 +1,8 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst}
 
 import Instructions._
 import ScalarControlConstants._
diff --git a/ChiselProject/src/examples/MemorySubsystem.scala b/package-delta-soc/src/designs/MemorySubsystem.scala
similarity index 82%
rename from ChiselProject/src/examples/MemorySubsystem.scala
rename to package-delta-soc/src/designs/MemorySubsystem.scala
index a1dc120..136aa5d 100644
--- a/ChiselProject/src/examples/MemorySubsystem.scala
+++ b/package-delta-soc/src/designs/MemorySubsystem.scala
@@ -1,6 +1,11 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.Analog
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import vivadoips.{Axi4Crossbar, Axi4DataWidthConverter, Axi4SpiFlash, Axi4LiteUartLite, Axi4LiteGpio, IOBUF}
+import builder.{addConstraintResource, addSimulationResource}
 
 
 /**
@@ -132,12 +137,10 @@ class MemorySubsystem extends Module {
   flash.io.s_axi := DontCare
   flash.io.io0_i := false.B
   flash.io.io1_i := true.B
-  // flash.io.sck_i := false.B
   flash.io.ss_i := false.B
 
-  // io.qspi_sck := flash.io.sck_o.asClock
+  io.qspi_sck := DontCare
   io.qspi_cs := flash.io.ss_o
-  // flash.io.sck_i := 0.B
   flash.io.ss_i := 0.B
 
   val qspi_io0_buf = Module(new IOBUF())
@@ -152,4 +155,11 @@ class MemorySubsystem extends Module {
   qspi_io1_buf.io.I := flash.io.io1_o
   qspi_io1_buf.io.T := flash.io.io1_t
 
+  addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc")
+
+  addSimulationResource("package-delta-soc/test/MemorySubsystemTestbench.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/Ram.v")
 }
diff --git a/package-delta-soc/src/designs/MlpPolicyRunner.scala b/package-delta-soc/src/designs/MlpPolicyRunner.scala
new file mode 100644
index 0000000..c685c7e
--- /dev/null
+++ b/package-delta-soc/src/designs/MlpPolicyRunner.scala
@@ -0,0 +1,28 @@
+package delta
+
+import chisel3._
+import chisel3.util._
+import builder.{addConstraintResource, addSimulationResource}
+
+
+class MlpPolicyRunner extends MlpPolicyRunnerBase(
+  new SoCConfig(
+    tile = new TileConfig(
+      core = new CoreConfig(
+        XLEN = 32,
+        ELEN = 32,
+        VLEN = 64,
+        pipelineStages = 3,
+      ),
+      sbusFrequency = 50,
+    )
+  )
+) {
+  addConstraintResource("package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc")
+
+  addSimulationResource("package-delta-soc/test/MlpPolicyRunnerTestbench.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SimUart.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SpiFlashMemCtrl.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/SimSpiFlashModel.sv")
+  addSimulationResource("package-delta-soc/resources/verilog/Ram.v")
+}
diff --git a/ChiselProject/src/generators/interconnect/Axi4WidthDownsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala
similarity index 97%
rename from ChiselProject/src/generators/interconnect/Axi4WidthDownsizer.scala
rename to package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala
index 55c656f..10f4e45 100644
--- a/ChiselProject/src/generators/interconnect/Axi4WidthDownsizer.scala
+++ b/package-delta-soc/src/interconnect/Axi4WidthDownsizer.scala
@@ -1,5 +1,9 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle}
+
 
 class Axi4WidthDownsizer(
   s_params: Axi4Params = Axi4Params(dataWidth = 64),
diff --git a/ChiselProject/src/generators/interconnect/Axi4WidthUpsizer.scala b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala
similarity index 97%
rename from ChiselProject/src/generators/interconnect/Axi4WidthUpsizer.scala
rename to package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala
index b8727bf..22207a5 100644
--- a/ChiselProject/src/generators/interconnect/Axi4WidthUpsizer.scala
+++ b/package-delta-soc/src/interconnect/Axi4WidthUpsizer.scala
@@ -1,5 +1,9 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle}
+
 
 class Axi4WidthUpsizer(
   s_params: Axi4Params = Axi4Params(dataWidth = 32),
diff --git a/ChiselProject/src/generators/delta/memory/AsyncRam.scala b/package-delta-soc/src/memory/AsyncRam.scala
similarity index 98%
rename from ChiselProject/src/generators/delta/memory/AsyncRam.scala
rename to package-delta-soc/src/memory/AsyncRam.scala
index d0f2ef9..dbc6430 100644
--- a/ChiselProject/src/generators/delta/memory/AsyncRam.scala
+++ b/package-delta-soc/src/memory/AsyncRam.scala
@@ -1,3 +1,5 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/delta/memory/Axi4LiteMemory.scala b/package-delta-soc/src/memory/Axi4LiteMemory.scala
similarity index 88%
rename from ChiselProject/src/generators/delta/memory/Axi4LiteMemory.scala
rename to package-delta-soc/src/memory/Axi4LiteMemory.scala
index c4dd749..ae95fc0 100644
--- a/ChiselProject/src/generators/delta/memory/Axi4LiteMemory.scala
+++ b/package-delta-soc/src/memory/Axi4LiteMemory.scala
@@ -1,7 +1,9 @@
+package delta
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4LiteBundle}
 
-import java.io.PrintWriter
 
 class Axi4LiteMemory(
   val params: Axi4Params = Axi4Params(),
diff --git a/ChiselProject/src/generators/delta/memory/Axi4Memory.scala b/package-delta-soc/src/memory/Axi4Memory.scala
similarity index 88%
rename from ChiselProject/src/generators/delta/memory/Axi4Memory.scala
rename to package-delta-soc/src/memory/Axi4Memory.scala
index ce3b477..4d819f5 100644
--- a/ChiselProject/src/generators/delta/memory/Axi4Memory.scala
+++ b/package-delta-soc/src/memory/Axi4Memory.scala
@@ -1,7 +1,9 @@
+package delta
+
 import chisel3._
 import chisel3.util._
-
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle, AxResponse}
+import builder.{addVivadoTclScript}
 
 
 class Axi4Memory(
@@ -130,22 +132,16 @@ class Axi4Memory(
   io.s_axi.r.bits.data := mem.io.rdata
 
 
-  def generate_tcl_script(): Unit = {
-    if (memoryFileHex != "") {
-      val vivado_project_dir = "out/VivadoProject"
-      
-      // Get current working directory
+  if (memoryFileHex != "") {
+    addVivadoTclScript(s"ip/add_memory_${memoryFileHex}.tcl", {
       val file_path = System.getProperty("user.dir") + "/firmware/" + memoryFileHex
-      val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/add_memory_${memoryFileHex}.tcl")
       
-      // Use current directory to create paths
-      tcl_script.println(s"add_files -norecurse ${file_path}")
-      tcl_script.println(s"set_property file_type {Memory Initialization Files} [get_files ${file_path}]")
-
-      tcl_script.close()
-    }
+      s"""
+add_files -norecurse ${file_path}
+set_property file_type {Memory Initialization Files} [get_files ${file_path}]
+"""
+    })
   }
-  generate_tcl_script()
 }
 
 
diff --git a/ChiselProject/src/generators/delta/memory/Axi4MemoryWithLatency.scala b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala
similarity index 96%
rename from ChiselProject/src/generators/delta/memory/Axi4MemoryWithLatency.scala
rename to package-delta-soc/src/memory/Axi4MemoryWithLatency.scala
index c4b08de..e71f460 100644
--- a/ChiselProject/src/generators/delta/memory/Axi4MemoryWithLatency.scala
+++ b/package-delta-soc/src/memory/Axi4MemoryWithLatency.scala
@@ -1,7 +1,8 @@
+package delta
+
 import chisel3._
 import chisel3.util._
-
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle, ChannelAx, ChannelW, ChannelR}
 
 
 class Axi4MemoryWithLatency(
diff --git a/ChiselProject/src/generators/delta/memory/Ram.scala b/package-delta-soc/src/memory/Ram.scala
similarity index 98%
rename from ChiselProject/src/generators/delta/memory/Ram.scala
rename to package-delta-soc/src/memory/Ram.scala
index 379adc5..a7e4b3f 100644
--- a/ChiselProject/src/generators/delta/memory/Ram.scala
+++ b/package-delta-soc/src/memory/Ram.scala
@@ -1,3 +1,5 @@
+package delta
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/test/resources/verilog/examples/EECS151TileISATestbench.sv b/package-delta-soc/test/EECS151TileISATestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/EECS151TileISATestbench.sv
rename to package-delta-soc/test/EECS151TileISATestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/EECS151TileTestbench.sv b/package-delta-soc/test/EECS151TileTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/EECS151TileTestbench.sv
rename to package-delta-soc/test/EECS151TileTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/EECS252TileTestbench.sv b/package-delta-soc/test/EECS252TileTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/EECS252TileTestbench.sv
rename to package-delta-soc/test/EECS252TileTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/InstructionFetchTestbench.sv b/package-delta-soc/test/InstructionFetchTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/InstructionFetchTestbench.sv
rename to package-delta-soc/test/InstructionFetchTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/MemorySubsystemTestbench.sv b/package-delta-soc/test/MemorySubsystemTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/MemorySubsystemTestbench.sv
rename to package-delta-soc/test/MemorySubsystemTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv b/package-delta-soc/test/MlpPolicyRunnerTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/MlpPolicyRunnerTestbench.sv
rename to package-delta-soc/test/MlpPolicyRunnerTestbench.sv
diff --git a/ChiselProject/src/generators/tacit/MadaTimer.scala b/package-tacit/src/MadaTimer.scala
similarity index 99%
rename from ChiselProject/src/generators/tacit/MadaTimer.scala
rename to package-tacit/src/MadaTimer.scala
index bfca9e9..d36e4df 100644
--- a/ChiselProject/src/generators/tacit/MadaTimer.scala
+++ b/package-tacit/src/MadaTimer.scala
@@ -1,7 +1,10 @@
+package tacit
+
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.decode._
 
+
 class PrescalerCounter extends Module {
   val io = IO(new Bundle {
     val enable = Input(Bool())
diff --git a/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc b/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc
similarity index 86%
rename from ChiselProject/resources/constraints/Arty-A7-100-Master.xdc
rename to package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc
index 664d463..e4d18a4 100644
--- a/ChiselProject/resources/constraints/Arty-A7-100-Master.xdc
+++ b/package-vivado-ips/resources/constraints/Arty-A7-100-Master.xdc
@@ -121,57 +121,57 @@ set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { io_ck_
 ## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
 ## WARNING: Do not use both sets of constraints at the same time!
 ## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
-#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L1N_T0_AD4N_35 	   Sch=ck_an_n[0] ChipKit pin=A0
-#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L1P_T0_AD4P_35 	   Sch=ck_an_p[0] ChipKit pin=A0
-#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
-#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
-#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L7N_T1_AD6N_35 	   Sch=ck_an_n[2] ChipKit pin=A2
-#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L7P_T1_AD6P_35 	   Sch=ck_an_p[2] ChipKit pin=A2
-#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
-#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
-#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35   Sch=ck_an_n[4] ChipKit pin=A4
-#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35   Sch=ck_an_p[4] ChipKit pin=A4
-#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15 	   Sch=ck_an_n[5] ChipKit pin=A5
-#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15 	   Sch=ck_an_p[5] ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { io_vaux4_n  }]; #IO_L1N_T0_AD4N_35 	   Sch=ck_an_n[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { io_vaux4_p  }]; #IO_L1P_T0_AD4P_35 	   Sch=ck_an_p[0] ChipKit pin=A0
+#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { io_vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { io_vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
+#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { io_vaux6_n  }]; #IO_L7N_T1_AD6N_35 	   Sch=ck_an_n[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { io_vaux6_p  }]; #IO_L7P_T1_AD6P_35 	   Sch=ck_an_p[2] ChipKit pin=A2
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { io_vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { io_vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { io_vaux15_n }]; #IO_L10N_T1_AD15N_35   Sch=ck_an_n[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { io_vaux15_p }]; #IO_L10P_T1_AD15P_35   Sch=ck_an_p[4] ChipKit pin=A4
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { io_vaux0_n  }]; #IO_L1N_T0_AD0N_15 	   Sch=ck_an_n[5] ChipKit pin=A5
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { io_vaux0_p  }]; #IO_L1P_T0_AD0P_15 	   Sch=ck_an_p[5] ChipKit pin=A5
 ## ChipKit Outer Analog Header - as Digital I/O
 ## NOTE: The following constraints should be used when using these ports as digital I/O.
-#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
-#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
-#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
-#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
-#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
-#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a0 }]; #IO_0_35 Sch=ck_a[0]
+#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
+#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
+#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
 
 ## ChipKit Inner Analog Header - as Differential Analog Inputs
 ## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
 ## WARNING: Do not use both sets of constraints at the same time!
 ## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
-#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
-#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
-#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
-#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
-#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
-#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { io_vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { io_vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { io_vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { io_vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { io_vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { io_vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
 ## ChipKit Inner Analog Header - as Digital I/O
 ## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
-#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
-#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
-#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
-#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
-#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
-#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
+#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a6  }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a7  }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a8  }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a9  }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
+#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
+#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { io_ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
 
 ## ChipKit SPI
-#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
-#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
-#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
-#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { io_ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { io_ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { io_ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { io_ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
 
 ## ChipKit I2C
-#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
-#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
-#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
-#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { io_ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { io_ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { io_scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { io_sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
 
 ## Misc. ChipKit Ports
 set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { io_ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
@@ -216,11 +216,11 @@ set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { io_qsp
 set_property -dict { BITSTREAM.CONFIG.SPI_BUSWIDTH {4} } [current_design]
 
 ## Power Measurements 
-#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
-#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
-#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
-#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
-#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
-#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
-#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
-#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
\ No newline at end of file
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { io_vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { io_vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
+#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { io_vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
+#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { io_vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { io_isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { io_isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { io_isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { io_isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
\ No newline at end of file
diff --git a/ChiselProject/resources/constraints/Arty_C_mig.ucf b/package-vivado-ips/resources/constraints/Arty_C_mig.ucf
similarity index 100%
rename from ChiselProject/resources/constraints/Arty_C_mig.ucf
rename to package-vivado-ips/resources/constraints/Arty_C_mig.ucf
diff --git a/ChiselProject/resources/constraints/Zedboard-Master.xdc b/package-vivado-ips/resources/constraints/Zedboard-Master.xdc
similarity index 100%
rename from ChiselProject/resources/constraints/Zedboard-Master.xdc
rename to package-vivado-ips/resources/constraints/Zedboard-Master.xdc
diff --git a/ChiselProject/resources/constraints/axis_async_fifo.tcl b/package-vivado-ips/resources/constraints/axis_async_fifo.tcl
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rename from ChiselProject/resources/constraints/axis_async_fifo.tcl
rename to package-vivado-ips/resources/constraints/axis_async_fifo.tcl
diff --git a/ChiselProject/resources/constraints/eth_mac_fifo.tcl b/package-vivado-ips/resources/constraints/eth_mac_fifo.tcl
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rename from ChiselProject/resources/constraints/eth_mac_fifo.tcl
rename to package-vivado-ips/resources/constraints/eth_mac_fifo.tcl
diff --git a/ChiselProject/resources/constraints/mig.prj b/package-vivado-ips/resources/constraints/mig.prj
similarity index 100%
rename from ChiselProject/resources/constraints/mig.prj
rename to package-vivado-ips/resources/constraints/mig.prj
diff --git a/ChiselProject/resources/constraints/mii_phy_if.tcl b/package-vivado-ips/resources/constraints/mii_phy_if.tcl
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rename from ChiselProject/resources/constraints/mii_phy_if.tcl
rename to package-vivado-ips/resources/constraints/mii_phy_if.tcl
diff --git a/ChiselProject/resources/constraints/sync_reset.tcl b/package-vivado-ips/resources/constraints/sync_reset.tcl
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rename from ChiselProject/resources/constraints/sync_reset.tcl
rename to package-vivado-ips/resources/constraints/sync_reset.tcl
diff --git a/ChiselProject/resources/verilog/Arty100TShell.v b/package-vivado-ips/resources/verilog/Arty100TShell.v
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rename from ChiselProject/resources/verilog/Arty100TShell.v
rename to package-vivado-ips/resources/verilog/Arty100TShell.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.github/workflows/regression-tests.yml
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.gitignore b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.gitignore
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.gitignore
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/.test_durations b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/.test_durations
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/.test_durations
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/AUTHORS b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/AUTHORS
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/AUTHORS
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/COPYING b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/COPYING
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/COPYING
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/README b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/README
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/README
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/README
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/README.md b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md
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rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/README.md
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/arbiter.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_adapter.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_arb_mux_wrap.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v
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rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_async_fifo_adapter.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_broadcast_wrap.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_decode.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_cobs_encode.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_crosspoint_wrap.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_demux_wrap.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_fifo_adapter.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join.v
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_join_wrap.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_len.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust.v
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_frame_length_adjust_fifo.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ll_bridge.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_mux_wrap.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_fifo.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_pipeline_register.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_ram_switch_wrap.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_rate_limit.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_register.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_fifo.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_srl_register.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_stat_counter.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_switch_wrap.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/axis_tap.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/ll_axis_bridge.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/priority_encoder.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/rtl/sync_reset.v
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/axis_async_fifo.sdc
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus/sync_reset.sdc
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/quartus_pro/sync_reset.sdc
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/axis_async_fifo.tcl
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/syn/vivado/sync_reset.tcl
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/Makefile
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_adapter/test_axis_adapter.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/Makefile
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_broadcast/test_axis_broadcast.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_decode/test_axis_cobs_decode.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py
similarity index 100%
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rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_cobs_encode/test_axis_cobs_encode.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_demux/test_axis_demux.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_ep.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/Makefile
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo/test_axis_fifo.py
similarity index 100%
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
similarity index 100%
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rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/Makefile
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py
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diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
rename to package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile
diff --git a/ChiselProject/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/package-vivado-ips/resources/verilog/alexforencich/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py
similarity index 100%
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rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_gmii_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_1g_rgmii_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_mii_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_fifo.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mac_phy_10g_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_ber_mon.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_frame_sync.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_if.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_rx_watchdog.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/eth_phy_10g_tx_if.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/gmii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/gmii_phy_if.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/gmii_phy_if.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/iddr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/iddr.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/iddr.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_arb_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_arb_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_complete.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_complete.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_complete_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_complete_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_complete_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_demux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_demux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_demux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_rx_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_eth_tx_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ip_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ip_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ip_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/lfsr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/lfsr.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/lfsr.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_ctrl_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mac_pause_ctrl_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/mii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/mii_phy_if.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/mii_phy_if.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/oddr.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/oddr.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/oddr.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_clock_cdc.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_perout.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_perout.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_perout.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_tag_insert.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_tag_insert.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_tag_insert.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_leaf.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_leaf.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_leaf.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_phc.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_phc.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_phc.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_td_rel2tod.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ptp_ts_extract.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ptp_ts_extract.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ptp_ts_extract.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/rgmii_phy_if.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/rgmii_phy_if.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/rgmii_phy_if.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_in_diff.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_ddr_out_diff.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_in_diff.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/ssio_sdr_out_diff.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_arb_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_arb_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_arb_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_checksum_gen_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_complete.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_complete.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_complete_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_complete_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_complete_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_demux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_demux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_demux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_rx_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_ip_tx_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/udp_mux.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/udp_mux.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/udp_mux.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_dec_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_baser_enc_64.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_deinterleave.v
diff --git a/ChiselProject/resources/verilog/alexforencich/rtl/xgmii_interleave.v b/package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/rtl/xgmii_interleave.v
rename to package-vivado-ips/resources/verilog/alexforencich/rtl/xgmii_interleave.v
diff --git a/ChiselProject/resources/verilog/alexforencich/udp_core.v b/package-vivado-ips/resources/verilog/alexforencich/udp_core.v
similarity index 100%
rename from ChiselProject/resources/verilog/alexforencich/udp_core.v
rename to package-vivado-ips/resources/verilog/alexforencich/udp_core.v
diff --git a/ChiselProject/resources/verilog/sync_reset.v b/package-vivado-ips/resources/verilog/sync_reset.v
similarity index 100%
rename from ChiselProject/resources/verilog/sync_reset.v
rename to package-vivado-ips/resources/verilog/sync_reset.v
diff --git a/ChiselProject/src/top/Arty100TTop.scala b/package-vivado-ips/src/Arty100TTop.scala
similarity index 98%
rename from ChiselProject/src/top/Arty100TTop.scala
rename to package-vivado-ips/src/Arty100TTop.scala
index 29a82c0..6ac0be0 100644
--- a/ChiselProject/src/top/Arty100TTop.scala
+++ b/package-vivado-ips/src/Arty100TTop.scala
@@ -1,3 +1,5 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.Analog
diff --git a/ChiselProject/src/examples/MinimalArty100T.scala b/package-vivado-ips/src/MinimalArty100T.scala
similarity index 97%
rename from ChiselProject/src/examples/MinimalArty100T.scala
rename to package-vivado-ips/src/MinimalArty100T.scala
index 6589e2d..7fed6fe 100644
--- a/ChiselProject/src/examples/MinimalArty100T.scala
+++ b/package-vivado-ips/src/MinimalArty100T.scala
@@ -1,3 +1,5 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.Analog
diff --git a/ChiselProject/src/top/ZedboardTop.scala b/package-vivado-ips/src/ZedboardTop.scala
similarity index 98%
rename from ChiselProject/src/top/ZedboardTop.scala
rename to package-vivado-ips/src/ZedboardTop.scala
index c2d9606..6565d74 100644
--- a/ChiselProject/src/top/ZedboardTop.scala
+++ b/package-vivado-ips/src/ZedboardTop.scala
@@ -1,3 +1,5 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/basic/ClockDivider.scala b/package-vivado-ips/src/basic/ClockDivider.scala
similarity index 96%
rename from ChiselProject/src/generators/basic/ClockDivider.scala
rename to package-vivado-ips/src/basic/ClockDivider.scala
index 97d976f..bc1af43 100644
--- a/ChiselProject/src/generators/basic/ClockDivider.scala
+++ b/package-vivado-ips/src/basic/ClockDivider.scala
@@ -1,3 +1,5 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/basic/SyncReset.scala b/package-vivado-ips/src/basic/SyncReset.scala
similarity index 97%
rename from ChiselProject/src/generators/basic/SyncReset.scala
rename to package-vivado-ips/src/basic/SyncReset.scala
index f71792d..ddbd253 100644
--- a/ChiselProject/src/generators/basic/SyncReset.scala
+++ b/package-vivado-ips/src/basic/SyncReset.scala
@@ -1,3 +1,5 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 
diff --git a/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala
similarity index 54%
rename from ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala
rename to package-vivado-ips/src/xilinx/Axi4BlockMemory.scala
index 33b1778..3e895ba 100644
--- a/ChiselProject/src/generators/xilinx/Axi4BlockMemory.scala
+++ b/package-vivado-ips/src/xilinx/Axi4BlockMemory.scala
@@ -1,6 +1,9 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle}
+import builder.addVivadoIp
 
 
 class Axi4BlockMemory(
@@ -33,18 +36,18 @@ class Axi4BlockMemoryBlackbox(
     val rstb_busy = Output(Bool())
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4BlockMemoryBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name ${ip_name}")
 
-    val fillUnused = "true"
 
-    tcl_script.println(s"""
+  val ipName = "Axi4BlockMemoryBlackbox"
+  val fillUnused = "true"
+  
+  addVivadoIp(
+    name="blk_mem_gen",
+    vendor="xilinx.com",
+    library="ip",
+    version="8.4",
+    moduleName=ipName,
+    extra=s"""
 set_property -dict [list \\
   CONFIG.AXI_Type {AXI4} \\
   CONFIG.Interface_Type {AXI4} \\
@@ -53,17 +56,7 @@ set_property -dict [list \\
   CONFIG.Load_Init_File {true} \\
   CONFIG.Fill_Remaining_Memory_Locations {${fillUnused}} \\
   CONFIG.Coe_File {${coeFile}} \\
-] [get_ips ${ip_name}]
-""")
-    
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+] [get_ips ${ipName}]
+"""
+  )
 }
diff --git a/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala
similarity index 88%
rename from ChiselProject/src/generators/xilinx/Axi4Crossbar.scala
rename to package-vivado-ips/src/xilinx/Axi4Crossbar.scala
index 2404790..d998198 100644
--- a/ChiselProject/src/generators/xilinx/Axi4Crossbar.scala
+++ b/package-vivado-ips/src/xilinx/Axi4Crossbar.scala
@@ -1,7 +1,9 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
-
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst}
+import builder.addVivadoIp
 
 
 class Axi4CrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle {
@@ -163,24 +165,16 @@ class Axi4CrossbarBlackbox(
 
   override def desiredName: String = s"Axi4CrossbarBlackbox_s${numSlave}_m${numMaster}_w${params.dataWidth}_id${params.idWidth}"
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = desiredName
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
 
-    tcl_script.println(s"""
+  val ipName = desiredName
+  addVivadoIp(
+    name="axi_crossbar",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.1",
+    moduleName=ipName,
+    extra = {
+      val baseConfig = s"""
 set_property -dict [list \\
   CONFIG.PROTOCOL {AXI4} \\
   CONFIG.NUM_MI {${numMaster}} \\
@@ -191,19 +185,18 @@ set_property -dict [list \\
   CONFIG.S00_THREAD_ID_WIDTH {1} \\
   CONFIG.S01_SINGLE_THREAD {1} \\
   CONFIG.S01_THREAD_ID_WIDTH {1} \\
-  ] [get_ips ${ip_name}]
-""")
-
-    for (i <- 0 until numMaster) {
-      tcl_script.println(s"""
+  ] [get_ips ${ipName}]
+"""
+      val masterConfigs = (0 until numMaster).map { i =>
+s"""
 set_property -dict [list \\
   CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_ADDR_WIDTH {${log2Ceil(deviceSizes(i))}} \\
   CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_BASE_ADDR {0x${deviceAddresses(i).toString(16).reverse.padTo(16, '0').reverse}} \\
-] [get_ips ${ip_name}]
-""")
+] [get_ips ${ipName}]
+"""
+      }.mkString("\n")
+  
+      baseConfig + masterConfigs
     }
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+  )
 }
\ No newline at end of file
diff --git a/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala
new file mode 100644
index 0000000..055daad
--- /dev/null
+++ b/package-vivado-ips/src/xilinx/Axi4DataWidthConverter.scala
@@ -0,0 +1,52 @@
+package vivadoips
+
+import chisel3._
+import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle}
+import builder.addVivadoIp
+
+
+class Axi4DataWidthConverter(
+  s_params: Axi4Params,
+  m_params: Axi4Params
+) extends Module {
+  val io = IO(new Bundle {
+    val s_axi = Flipped(new Axi4Bundle(s_params))
+    val m_axi = new Axi4Bundle(m_params)
+  })
+
+  val blackbox = Module(new Axi4DataWidthConverterBlackbox(s_params, m_params))
+
+  blackbox.io.s_axi_aclk := clock
+  blackbox.io.s_axi_aresetn := ~reset.asBool
+  blackbox.io.s_axi.connectFrom(io.s_axi)
+  blackbox.io.m_axi.connectTo(io.m_axi)
+}
+
+class Axi4DataWidthConverterBlackbox(
+  s_params: Axi4Params,
+  m_params: Axi4Params
+) extends BlackBox {
+  val io = IO(new Bundle {
+    val s_axi_aclk = Input(Clock())
+    val s_axi_aresetn = Input(Bool())
+    val s_axi = Flipped(new Axi4BlackboxBundle(s_params))
+    val m_axi = new Axi4BlackboxBundle(m_params)
+  })
+
+  val ipName = "Axi4DataWidthConverterBlackbox"
+  addVivadoIp(
+    name="axi_dwidth_converter",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.1",
+    moduleName=ipName,
+    extra = s"""
+set_property -dict [list \\
+  CONFIG.MI_DATA_WIDTH {${m_params.dataWidth}} \\
+  CONFIG.SI_DATA_WIDTH {${s_params.dataWidth}} \\
+  CONFIG.SI_ID_WIDTH {${s_params.idWidth}} \\
+] [get_ips ${ipName}]
+"""
+  )
+}
diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala
similarity index 82%
rename from ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala
rename to package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala
index a21fa0d..941e51c 100644
--- a/ChiselProject/src/generators/xilinx/Axi4LiteCrossbar.scala
+++ b/package-vivado-ips/src/xilinx/Axi4LiteCrossbar.scala
@@ -1,7 +1,9 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
-
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle, AxResponse, AxSize, AxBurst, Axi4LiteBundle}
+import builder.addVivadoIp
 
 
 class Axi4LiteCrossbarBlackboxBundle(n: Int, params: Axi4Params = Axi4Params()) extends Bundle {
@@ -49,7 +51,7 @@ class Axi4LiteCrossbar(
 
   blackbox.io.aclk := clock
   blackbox.io.aresetn := ~reset.asBool
-  
+
   // Map the vector of Axi4Lite slaves to a single wide Axi4LiteCrossbarBlackboxBundle
   // this is done because in Xilinx IP, multiple AXI4 Lite interface are concatenated
   // into a single wide AXI4 Lite signals
@@ -102,7 +104,7 @@ class Axi4LiteCrossbar(
     io.m_axi(i).ar.bits.addr := blackbox.io.m_axi.araddr(32*i + 31, 32*i)
   }
   blackbox.io.m_axi.arready := Cat(io.m_axi.reverse.map(_.ar.ready))
-  
+
   blackbox.io.m_axi.rdata := Cat(io.m_axi.reverse.map(_.r.bits.data))
   blackbox.io.m_axi.rresp := Cat(io.m_axi.reverse.map(_.r.bits.resp.asUInt))
   blackbox.io.m_axi.rvalid := Cat(io.m_axi.reverse.map(_.r.valid))
@@ -123,41 +125,30 @@ class Axi4LiteCrossbarBlackbox(
   })
 
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4LiteCrossbarBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name ${ip_name}")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.println(s"""
+  val ipName = "Axi4LiteCrossbarBlackbox"
+  addVivadoIp(
+    name="axi_crossbar",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.1",
+    moduleName=ipName,
+    extra = {
+      val baseConfig = s"""
 set_property -dict [list \\
   CONFIG.PROTOCOL {AXI4LITE} \\
   CONFIG.NUM_MI {${numMaster}} \\
   CONFIG.NUM_SI {${numSlave}} \\
-] [get_ips ${ip_name}]
-""")
-
-    for (i <- 0 until numMaster) {
-      tcl_script.println(s"""
+] [get_ips ${ipName}]
+"""
+      val masterConfigs = (0 until numMaster).map { i => s"""
 set_property -dict [list \\
   CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_ADDR_WIDTH {${log2Ceil(deviceSizes(i))}} \\
   CONFIG.M${i.toString().reverse.padTo(2, '0').reverse}_A00_BASE_ADDR {0x${deviceAddresses(i).toString(16).reverse.padTo(16, '0').reverse}} \\
-] [get_ips ${ip_name}]
-""")
-    }
+] [get_ips ${ipName}]
+"""
+      }.mkString("\n")
 
-    tcl_script.close()
-  }
-  generate_tcl_script()
+      baseConfig + masterConfigs
+    }
+  )
 }
\ No newline at end of file
diff --git a/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala
new file mode 100644
index 0000000..0ece24b
--- /dev/null
+++ b/package-vivado-ips/src/xilinx/Axi4LiteGpio.scala
@@ -0,0 +1,55 @@
+package vivadoips
+
+import chisel3._
+import chisel3.util._
+import amba.{Axi4Params, Axi4LiteBundle}
+import builder.addVivadoIp
+
+
+case class Axi4LiteGpioConfig(
+)
+
+class Axi4LiteGpio(
+  val config: Axi4LiteGpioConfig = Axi4LiteGpioConfig()
+) extends Module {
+  val io = IO(new Bundle {
+    val s_axi = Flipped(new Axi4LiteBundle())
+    val gpio_io_i = Input(UInt(32.W))
+    val gpio_io_o = Output(UInt(32.W))
+    val gpio_io_t = Output(UInt(32.W))
+  })
+
+  val blackbox = Module(new Axi4LiteGpioBlackbox(config))
+
+  blackbox.io.s_axi_aclk := clock
+  blackbox.io.s_axi_aresetn := ~reset.asBool
+  blackbox.io.s_axi.connectFrom(io.s_axi)
+
+  blackbox.io.gpio_io_i := io.gpio_io_i
+  io.gpio_io_o := blackbox.io.gpio_io_o
+  io.gpio_io_t := blackbox.io.gpio_io_t
+}
+
+class Axi4LiteGpioBlackbox(
+  val config: Axi4LiteGpioConfig = Axi4LiteGpioConfig()
+) extends BlackBox {
+  val io = IO(new Bundle {
+    val s_axi_aclk = Input(Clock())
+    val s_axi_aresetn = Input(Bool())
+    val s_axi = Flipped(new Axi4LiteBlackboxBundle())
+    val gpio_io_i = Input(UInt(32.W))
+    val gpio_io_o = Output(UInt(32.W))
+    val gpio_io_t = Output(UInt(32.W))
+  })
+
+
+  val ipName = "Axi4LiteGpioBlackbox"
+  addVivadoIp(
+    name="axi_gpio",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.0",
+    moduleName=ipName,
+    extra = ""
+  )
+}
diff --git a/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala
new file mode 100644
index 0000000..ddecf32
--- /dev/null
+++ b/package-vivado-ips/src/xilinx/Axi4LiteStreamDataFifo.scala
@@ -0,0 +1,45 @@
+package vivadoips
+
+import chisel3._
+import chisel3.util._
+import amba.{Axi4Params, Axi4StreamBundle}
+import builder.addVivadoIp
+
+
+class Axi4LiteStreamDataFifo(params: Axi4Params = Axi4Params()) extends Module {
+  val io = IO(new Bundle {
+    val s_axis = Flipped(new Axi4StreamBundle())
+    val m_axis = new Axi4StreamBundle()
+  })
+
+  val blackbox = Module(new Axi4LiteStreamDataFifoBlackbox(params))
+
+  blackbox.io.s_axis_aclk := clock
+  blackbox.io.s_axis_aresetn := ~reset.asBool
+  blackbox.io.s_axis.connect(io.s_axis)
+  blackbox.io.m_axis.flipConnect(io.m_axis)
+}
+
+class Axi4LiteStreamDataFifoBlackbox(params: Axi4Params = Axi4Params()) extends BlackBox {
+  val io = IO(new Bundle {
+    val s_axis_aclk = Input(Clock())
+    val s_axis_aresetn = Input(Reset())
+    val s_axis = Flipped(new Axi4StreamBlackboxBundle(params))
+    val m_axis = new Axi4StreamBlackboxBundle(params)
+  })
+
+  val ipName = "AXIStreamDataFifo"
+  addVivadoIp(
+    name="axis_data_fifo",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.0",
+    moduleName=ipName,
+    extra = s"""
+set_property -dict [list \\
+  CONFIG.HAS_TLAST {1} \\
+  CONFIG.TUSER_WIDTH {1} \\
+] [get_ips ${ipName}]
+"""
+  )
+}
diff --git a/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala
similarity index 50%
rename from ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala
rename to package-vivado-ips/src/xilinx/Axi4LiteTimer.scala
index 861454c..efd26ec 100644
--- a/ChiselProject/src/generators/xilinx/Axi4LiteTimer.scala
+++ b/package-vivado-ips/src/xilinx/Axi4LiteTimer.scala
@@ -1,9 +1,18 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4LiteBundle}
+import builder.addVivadoIp
+
 
-import java.io.PrintWriter
+case class Axi4LiteTimerConfig(
+  timerCounterWidth: Int = 32,
+)
 
-class Axi4LiteTimer extends Module {
+class Axi4LiteTimer(
+  val config: Axi4LiteTimerConfig = Axi4LiteTimerConfig()
+) extends Module {
   val io = IO(new Bundle {
     val s_axi = Flipped(new Axi4LiteBundle())
     val capturetrig0 = Input(Bool())
@@ -15,8 +24,8 @@ class Axi4LiteTimer extends Module {
     val freeze = Input(Bool())
   })
 
-  val blackbox = Module(new Axi4LiteTimerBlackbox())
-  
+  val blackbox = Module(new Axi4LiteTimerBlackbox(config))
+
   blackbox.io.s_axi_aclk := clock
   blackbox.io.s_axi_aresetn := ~reset.asBool
   blackbox.io.s_axi.connectFrom(io.s_axi)
@@ -29,7 +38,9 @@ class Axi4LiteTimer extends Module {
   io.interrupt := blackbox.io.interrupt
 }
 
-class Axi4LiteTimerBlackbox extends BlackBox {
+class Axi4LiteTimerBlackbox(
+  val config: Axi4LiteTimerConfig = Axi4LiteTimerConfig()
+) extends BlackBox {
   val io = IO(new Bundle {
     val s_axi_aclk = Input(Clock())
     val s_axi_aresetn = Input(Bool())
@@ -43,29 +54,17 @@ class Axi4LiteTimerBlackbox extends BlackBox {
     val freeze = Input(Bool())
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4LiteTimerBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-
-    tcl_script.println(s"create_ip -name axi_timer -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}")
-    
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.println(s"""
+  val ipName = "Axi4LiteTimerBlackbox"
+  addVivadoIp(
+    name="axi_timer",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.0",
+    moduleName=ipName,
+    extra = s"""
 set_property -dict [list \\
-  CONFIG.COUNT_WIDTH {32} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+  CONFIG.COUNT_WIDTH {${config.timerCounterWidth}} \\
+] [get_ips ${ipName}]
+"""
+  )
 }
diff --git a/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala
new file mode 100644
index 0000000..b7b1079
--- /dev/null
+++ b/package-vivado-ips/src/xilinx/Axi4LiteUartLite.scala
@@ -0,0 +1,59 @@
+package vivadoips
+
+import chisel3._
+import chisel3.util._
+import amba.{Axi4Params, Axi4LiteBundle}
+import builder.addVivadoIp
+
+
+case class Axi4LiteUartLiteConfig(
+  axiClockFrequency: Int = 100,
+  baudRate: Int = 115200,
+)
+
+class Axi4LiteUartLite(
+  val config: Axi4LiteUartLiteConfig = Axi4LiteUartLiteConfig()
+) extends Module {
+  val io = IO(new Bundle {
+    val s_axi = Flipped(new Axi4LiteBundle())
+    val rx = Input(Bool())
+    val tx = Output(Bool())
+  })
+
+  val blackbox = Module(new Axi4LiteUartLiteBlackbox(config))
+
+  blackbox.io.s_axi_aclk := clock
+  blackbox.io.s_axi_aresetn := ~reset.asBool
+  blackbox.io.s_axi.connectFrom(io.s_axi)
+  blackbox.io.rx := io.rx
+  io.tx := blackbox.io.tx
+}
+
+class Axi4LiteUartLiteBlackbox(
+  val config: Axi4LiteUartLiteConfig = Axi4LiteUartLiteConfig()
+) extends BlackBox {
+  val io = IO(new Bundle {
+    val s_axi_aclk = Input(Clock())
+    val s_axi_aresetn = Input(Bool())
+    val s_axi = Flipped(new Axi4LiteBlackboxBundle())
+    val rx = Input(Bool())
+    val tx = Output(Bool())
+  })
+
+  val ipName = "Axi4LiteUartLiteBlackbox"
+  addVivadoIp(
+    name="axi_uartlite",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.0",
+    moduleName=ipName,
+    // the "d" is not a typo down there
+    extra = s"""
+set_property -dict [list \\
+  CONFIG.C_BAUDRATE {${config.baudRate}} \\
+  CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {${config.axiClockFrequency}} \\
+] [get_ips ${ipName}]
+"""
+  )
+}
+
diff --git a/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala
new file mode 100644
index 0000000..c0b3f66
--- /dev/null
+++ b/package-vivado-ips/src/xilinx/Axi4ProtocolConverter.scala
@@ -0,0 +1,53 @@
+package vivadoips
+
+import chisel3._
+import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import builder.addVivadoIp
+
+
+class Axi4ProtocolConverter(
+  s_params: Axi4Params,
+  m_params: Axi4Params
+) extends Module {
+  val io = IO(new Bundle {
+    val s_axi = Flipped(new Axi4Bundle(s_params))
+    val m_axi = new Axi4LiteBundle()
+  })
+
+  val blackbox = Module(new Axi4ProtocolConverterBlackbox(s_params, m_params))
+
+  blackbox.io.aclk := clock
+  blackbox.io.aresetn := ~reset.asBool
+  blackbox.io.s_axi.connectFrom(io.s_axi)
+  blackbox.io.m_axi.connectTo(io.m_axi)
+}
+
+class Axi4ProtocolConverterBlackbox(
+  s_params: Axi4Params,
+  m_params: Axi4Params
+) extends BlackBox {
+  val io = IO(new Bundle {
+    val aclk = Input(Clock())
+    val aresetn = Input(Bool())
+    val s_axi = Flipped(new Axi4BlackboxBundle(s_params))
+    val m_axi = new Axi4LiteBlackboxBundle(m_params)
+  })
+
+  val ipName = "Axi4ProtocolConverterBlackbox"
+  addVivadoIp(
+    name="axi_protocol_converter",
+    vendor="xilinx.com",
+    library="ip",
+    version="2.1",
+    moduleName=ipName,
+    extra = s"""
+set_property -dict [list \\
+  CONFIG.ID_WIDTH {${s_params.idWidth}} \\
+  CONFIG.MI_PROTOCOL {AXI4LITE} \\
+  CONFIG.SI_PROTOCOL {AXI4} \\
+  CONFIG.DATA_WIDTH {${s_params.dataWidth}} \\
+] [get_ips ${ipName}]
+"""
+  )
+}
\ No newline at end of file
diff --git a/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala
similarity index 76%
rename from ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala
rename to package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala
index 53fc6b0..6976bc8 100644
--- a/ChiselProject/src/generators/xilinx/Axi4QuadSpiFlash.scala
+++ b/package-vivado-ips/src/xilinx/Axi4QuadSpiFlash.scala
@@ -1,7 +1,10 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import builder.{addVivadoIp, addVivadoTclScript}
 
-import java.io.PrintWriter
 
 class Axi4QuadSpiFlash extends Module {
   val io = IO(new Bundle {
@@ -66,7 +69,7 @@ class Axi4QuadSpiFlash extends Module {
   io.io2_t := blackbox.io.io2_t
   blackbox.io.io3_i := io.io3_i
   io.io3_o := blackbox.io.io3_o
-  io.io3_t := blackbox.io.io3_t 
+  io.io3_t := blackbox.io.io3_t
   // blackbox.io.sck_i := io.sck_i
   // io.sck_o := blackbox.io.sck_o
   // io.sck_t := blackbox.io.sck_t
@@ -120,19 +123,19 @@ class Axi4QuadSpiFlashBlackbox extends BlackBox {
     val ip2intc_irpt = Output(Bool())
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4QuadSpiFlashBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
+  val ip_name = "Axi4QuadSpiFlashBlackbox"
+  val ip_name_lower = ip_name.toLowerCase()
+  addVivadoTclScript(s"ip/create_ip_${ip_name_lower}.tcl", {
 
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name}")
+      // HACK: add flash memory file to Vivado project
+      // Get current working directory
+      val file_path = System.getProperty("user.dir") + "/firmware/" + "firmware.flash.8.hex"
 
     // the Flash memory used on the Arty is Spansion S25FL128S
     // it has 8 dummy cycles for single-mode read commands
     // and 6 dummy cycles for quad-mode read commands
-    tcl_script.println(s"""
+    s"""
+create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name}
 set_property -dict [list \\
   CONFIG.C_SPI_MEMORY {3} \\
   CONFIG.C_USE_STARTUP {0} \\
@@ -141,25 +144,17 @@ set_property -dict [list \\
   CONFIG.C_USE_STARTUP {1} \\
   CONFIG.C_SPI_MODE {2} \\
 ] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
 
-    // HACK: add flash memory file to Vivado project
-      // Get current working directory
-      val file_path = System.getProperty("user.dir") + "/firmware/" + "firmware.flash.8.hex"
-      
-      // Use current directory to create paths
-      tcl_script.println(s"add_files -norecurse ${file_path}")
-      tcl_script.println(s"set_property file_type {Memory Initialization Files} [get_files ${file_path}]")
+generate_target {instantiation_template} [get_ips ${ip_name}]
+update_compile_order -fileset sources_1
+generate_target all [get_ips ${ip_name}]
+catch { config_ip_cache -export [get_ips -all ${ip_name}] }
+export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet
+create_ip_run [get_ips ${ip_name}]
 
-    tcl_script.close()
-  }
-  generate_tcl_script()
+add_files -norecurse ${file_path}
+set_property file_type {Memory Initialization Files} [get_files ${file_path}]
+"""
+  })
 }
 
diff --git a/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala
similarity index 73%
rename from ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala
rename to package-vivado-ips/src/xilinx/Axi4SpiFlash.scala
index 9f0a0de..a0e6bb1 100644
--- a/ChiselProject/src/generators/xilinx/Axi4SpiFlash.scala
+++ b/package-vivado-ips/src/xilinx/Axi4SpiFlash.scala
@@ -1,7 +1,10 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
+import amba.{Axi4Params, Axi4Bundle, Axi4LiteBundle}
+import builder.addVivadoIp
 
-import java.io.PrintWriter
 
 class Axi4SpiFlash extends Module {
   val io = IO(new Bundle {
@@ -102,37 +105,24 @@ class Axi4SpiFlashBlackbox extends BlackBox {
     val ip2intc_irpt = Output(Bool())
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "Axi4SpiFlashBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name axi_quad_spi -vendor xilinx.com -library ip -version 3.2 -module_name ${ip_name}")
-
-    // the Flash memory used on the Arty is Spansion S25FL128S
-    // it has 8 dummy cycles for single-mode read commands
-    // and 6 dummy cycles for quad-mode read commands
-    tcl_script.println(s"""
+  // the Flash memory used on the Arty is Spansion S25FL128S
+  // it has 8 dummy cycles for single-mode read commands
+  // and 6 dummy cycles for quad-mode read commands
+  val ipName = "Axi4SpiFlashBlackbox"
+  addVivadoIp(
+    name="axi_quad_spi",
+    vendor="xilinx.com",
+    library="ip",
+    version="3.2",
+    moduleName=ipName,
+    extra = s"""
 set_property -dict [list \\
   CONFIG.C_SPI_MEMORY {3} \\
   CONFIG.C_USE_STARTUP {0} \\
   CONFIG.C_XIP_MODE {1} \\
   CONFIG.C_XIP_PERF_MODE {0} \\
   CONFIG.C_USE_STARTUP {1} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+] [get_ips ${ipName}]
+"""
+  )
 }
-
diff --git a/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala
similarity index 81%
rename from ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala
rename to package-vivado-ips/src/xilinx/Axi4WiderMemory.scala
index f71dada..39a1335 100644
--- a/ChiselProject/src/generators/xilinx/Axi4WiderMemory.scala
+++ b/package-vivado-ips/src/xilinx/Axi4WiderMemory.scala
@@ -1,7 +1,9 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
-
-import java.io.PrintWriter
+import amba.{Axi4Params, Axi4Bundle, AxResponse}
+import builder.addVivadoIp
 
 
 class Axi4WiderMemory(
@@ -18,7 +20,7 @@ class Axi4WiderMemory(
   val memAddressWidth = params.addressWidth - memAlignment
 
   val blackbox = Module(new WiderBlockMemoryBlackbox(params, coeFile))
-  
+
   // implementing AXI4 state machine from https://zipcpu.com/blog/2019/05/29/demoaxi.html
   val sWRITE_IDLE :: sWRITE_MID :: sWRITE_LAST :: sWRITE_END :: Nil = Enum(4)
   val reg_w_state = RegInit(sWRITE_IDLE)
@@ -83,7 +85,7 @@ class Axi4WiderMemory(
       }
     }
     is (sREAD_MID) {  // MID state
-      
+
     }
     is (sREAD_HOLD) {  // HOLD state
       when (io.s_axi.r.fire) {
@@ -132,18 +134,15 @@ class WiderBlockMemoryBlackbox(
     val douta = Output(UInt(params.dataWidth.W))
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "WiderBlockMemoryBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name ${ip_name}")
-
-    val fillUnused = "true"
-
-    tcl_script.println(s"""
+  val ipName = "WiderBlockMemoryBlackbox"
+  val fillUnused = "true"
+  addVivadoIp(
+    name="blk_mem_gen",
+    vendor="xilinx.com",
+    library="ip",
+    version="8.4",
+    moduleName=ipName,
+    extra=s"""
 set_property -dict [list \\
   CONFIG.Use_Byte_Write_Enable {true} \\
   CONFIG.Byte_Size {8} \\
@@ -154,17 +153,8 @@ set_property -dict [list \\
   CONFIG.Load_Init_File {true} \\
   CONFIG.Fill_Remaining_Memory_Locations {${fillUnused}} \\
   CONFIG.Coe_File {${coeFile}} \\
-] [get_ips ${ip_name}]
-""")
-    
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+] [get_ips ${ipName}]
+"""
+  )
 }
+
diff --git a/ChiselProject/src/generators/xilinx/ClockingWizard.scala b/package-vivado-ips/src/xilinx/ClockingWizard.scala
similarity index 74%
rename from ChiselProject/src/generators/xilinx/ClockingWizard.scala
rename to package-vivado-ips/src/xilinx/ClockingWizard.scala
index 4fd2b18..901681b 100644
--- a/ChiselProject/src/generators/xilinx/ClockingWizard.scala
+++ b/package-vivado-ips/src/xilinx/ClockingWizard.scala
@@ -1,7 +1,9 @@
+package vivadoips
+
 import chisel3.{BlackBox, _}
 import chisel3.util._
+import builder.addVivadoIp
 
-import java.io.PrintWriter
 
 class ClockingWizard(
   clk_freqs: Seq[Int]
@@ -47,20 +49,17 @@ class ClockingWizardBlackbox(
     val clk_out7 = if (get_used(6)) Output(Clock()) else null
   })
 
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "ClockingWizardBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val num_out_clks = clk_freqs.length
-    
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-    
-    tcl_script.println(s"create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ${ip_name}")
 
-    tcl_script.println(s"""
+  val ipName = "ClockingWizardBlackbox"
+  addVivadoIp(
+    name="clk_wiz",
+    vendor="xilinx.com",
+    library="ip",
+    version="6.0",
+    moduleName=ipName,
+    extra = s"""
 set_property -dict [list \\
-  CONFIG.NUM_OUT_CLKS {${num_out_clks}} \\
+  CONFIG.NUM_OUT_CLKS {${clk_freqs.length}} \\
   CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \\
   CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \\
   CONFIG.MMCM_CLKOUT1_DIVIDE {40} \\
@@ -92,17 +91,7 @@ set_property -dict [list \\
   CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {${get_freq(6)}} \\
   CONFIG.CLKOUT7_REQUESTED_PHASE {0.0} \\
   CONFIG.CLKOUT7_REQUESTED_DUTY_CYCLE {50.0} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+] [get_ips ${ipName}]
+"""
+  )
 }
diff --git a/ChiselProject/src/generators/xilinx/FloatingPoint.scala b/package-vivado-ips/src/xilinx/FloatingPoint.scala
similarity index 58%
rename from ChiselProject/src/generators/xilinx/FloatingPoint.scala
rename to package-vivado-ips/src/xilinx/FloatingPoint.scala
index 6bfc778..522bd06 100644
--- a/ChiselProject/src/generators/xilinx/FloatingPoint.scala
+++ b/package-vivado-ips/src/xilinx/FloatingPoint.scala
@@ -1,11 +1,27 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
+import builder.addVivadoIp
 
-import java.io.PrintWriter
 
+/**
+  * Floating Point Multiplier-Adder
+  *
+  * @param pipelineStages
+  */
+case class FloatingPointConfig(
+  /** Number of pipeline stages */
+  pipelineStages: Int = 1,
+)
 
+/**
+  * Floating Point Multiplier-Adder
+  *
+  * @param config
+  */
 class FloatingPoint(
-  val pipelineStages: Int = 1
+  val config: FloatingPointConfig = FloatingPointConfig()
 ) extends Module {
   val io = IO(new Bundle {
     val a = Flipped(Valid(UInt(32.W)))
@@ -14,7 +30,7 @@ class FloatingPoint(
     val result = Valid(UInt(32.W))
   })
 
-  val blackbox = Module(new FloatingPointBlackbox(pipelineStages=pipelineStages))
+  val blackbox = Module(new FloatingPointBlackbox(config))
 
   blackbox.io.aclk := clock
   blackbox.io.s_axis_a_tvalid := io.a.valid
@@ -28,7 +44,7 @@ class FloatingPoint(
 }
 
 class FloatingPointBlackbox(
-  val pipelineStages: Int = 1
+  val config: FloatingPointConfig = FloatingPointConfig()
 ) extends BlackBox {
   val io = IO(new Bundle {
     val aclk = Input(Clock())
@@ -41,23 +57,21 @@ class FloatingPointBlackbox(
     val m_axis_result_tvalid = Output(Bool())
     val m_axis_result_tdata = Output(UInt(32.W))
   })
-  
-  def generate_tcl_script(): Unit = {
-    val vivado_project_dir = "out/VivadoProject"
-    val ip_name = "FloatingPointBlackbox"
-    val ip_name_lower = ip_name.toLowerCase()
-
-    val tcl_script = new PrintWriter(s"${vivado_project_dir}/scripts/create_ip_${ip_name_lower}.tcl")
-
-    tcl_script.println(s"create_ip -name floating_point -vendor xilinx.com -library ip -version 7.1 -module_name ${ip_name}")
 
-    tcl_script.println(s"""
+  val ipName = "FloatingPointBlackbox"
+  addVivadoIp(
+    name="floating_point",
+    vendor="xilinx.com",
+    library="ip",
+    version="7.1",
+    moduleName=ipName,
+    extra = s"""
 set_property -dict [list \\
   CONFIG.A_Precision_Type {Single} \\
   CONFIG.Add_Sub_Value {Add} \\
   CONFIG.C_A_Exponent_Width {8} \\
   CONFIG.C_A_Fraction_Width {24} \\
-  CONFIG.C_Latency {${pipelineStages}} \\
+  CONFIG.C_Latency {${config.pipelineStages}} \\
   CONFIG.C_Mult_Usage {Full_Usage} \\
   CONFIG.C_Optimization {Speed_Optimized} \\
   CONFIG.C_Rate {1} \\
@@ -68,17 +82,7 @@ set_property -dict [list \\
   CONFIG.Maximum_Latency {false} \\
   CONFIG.Operation_Type {FMA} \\
   CONFIG.Result_Precision_Type {Single} \\
-] [get_ips ${ip_name}]
-""")
-
-    tcl_script.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
-    tcl_script.println("update_compile_order -fileset sources_1")
-    tcl_script.println(s"generate_target all [get_ips ${ip_name}]")
-    tcl_script.println(s"catch { config_ip_cache -export [get_ips -all ${ip_name}] }")
-    tcl_script.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
-    tcl_script.println(s"create_ip_run [get_ips ${ip_name}]")
-
-    tcl_script.close()
-  }
-  generate_tcl_script()
+] [get_ips ${ipName}]
+"""
+  )
 }
diff --git a/ChiselProject/src/generators/xilinx/IOBuffer.scala b/package-vivado-ips/src/xilinx/IOBuffer.scala
similarity index 96%
rename from ChiselProject/src/generators/xilinx/IOBuffer.scala
rename to package-vivado-ips/src/xilinx/IOBuffer.scala
index bbb631d..3845e05 100644
--- a/ChiselProject/src/generators/xilinx/IOBuffer.scala
+++ b/package-vivado-ips/src/xilinx/IOBuffer.scala
@@ -1,7 +1,10 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.Analog
 
+
 class IBUFG extends BlackBox {
   val io = IO(new Bundle {
     val I = Input(Bool())
diff --git a/ChiselProject/src/generators/xilinx/bundle/Axi4BlackboxBundles.scala b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala
similarity index 97%
rename from ChiselProject/src/generators/xilinx/bundle/Axi4BlackboxBundles.scala
rename to package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala
index 8eeb810..c745974 100644
--- a/ChiselProject/src/generators/xilinx/bundle/Axi4BlackboxBundles.scala
+++ b/package-vivado-ips/src/xilinx/bundle/Axi4BlackboxBundles.scala
@@ -1,6 +1,8 @@
+package vivadoips
+
 import chisel3._
 import chisel3.util._
-
+import amba.{Axi4Params, Axi4Bundle, Axi4Constants, Axi4LiteBundle, Axi4StreamBundle, AxResponse, AxSize, AxBurst}
 
 
 class Axi4LiteBlackboxBundle(params: Axi4Params = Axi4Params()) extends Bundle {
diff --git a/ChiselProject/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv b/package-vivado-ips/test/resources/verilog/Axi4MemoryForTestTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/Axi4MemoryForTestTestbench.sv
rename to package-vivado-ips/test/resources/verilog/Axi4MemoryForTestTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv b/package-vivado-ips/test/resources/verilog/Axi4SpiFlashTestBench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/Axi4SpiFlashTestBench.sv
rename to package-vivado-ips/test/resources/verilog/Axi4SpiFlashTestBench.sv
diff --git a/ChiselProject/test/resources/verilog/examples/AxiInterface.vh b/package-vivado-ips/test/resources/verilog/AxiInterface.vh
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/AxiInterface.vh
rename to package-vivado-ips/test/resources/verilog/AxiInterface.vh
diff --git a/ChiselProject/test/resources/verilog/examples/UartTestbench.sv b/package-vivado-ips/test/resources/verilog/UartTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/examples/UartTestbench.sv
rename to package-vivado-ips/test/resources/verilog/UartTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/components/RamTestbench.sv b/package-vivado-ips/test/resources/verilog/components/RamTestbench.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/components/RamTestbench.sv
rename to package-vivado-ips/test/resources/verilog/components/RamTestbench.sv
diff --git a/ChiselProject/test/resources/verilog/components/plusarg_file_mem.sv b/package-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv
similarity index 100%
rename from ChiselProject/test/resources/verilog/components/plusarg_file_mem.sv
rename to package-vivado-ips/test/resources/verilog/components/plusarg_file_mem.sv
diff --git a/scripts/install-mill.sh b/scripts/install-mill.sh
deleted file mode 100755
index d025405..0000000
--- a/scripts/install-mill.sh
+++ /dev/null
@@ -1,10 +0,0 @@
-source ./env.sh
-
-# Install mill
-echo "Installing mill..."
-echo "Toolchain directory: $TOOLCHAIN_DIR"
-
-mkdir -p $TOOLCHAIN_DIR
-
-curl -L https://github.com/com-lihaoyi/mill/releases/download/0.12.3/0.12.3 > $TOOLCHAIN_DIR/mill && chmod +x $TOOLCHAIN_DIR/mill
-export PATH="$TOOLCHAIN_DIR:$PATH"
diff --git a/scripts/vivado-ecad.sh b/scripts/vivado-ecad.sh
deleted file mode 100755
index 2088b4e..0000000
--- a/scripts/vivado-ecad.sh
+++ /dev/null
@@ -1 +0,0 @@
-source /ecad/tools/xilinx/Vivado/2023.2/settings64.sh
diff --git a/toolchains/mill b/toolchains/mill
new file mode 100755
index 0000000..f868036
--- /dev/null
+++ b/toolchains/mill
@@ -0,0 +1,265 @@
+#!/usr/bin/env sh
+
+# This is a wrapper script, that automatically download mill from GitHub release pages
+# You can give the required mill version with --mill-version parameter
+# If no version is given, it falls back to the value of DEFAULT_MILL_VERSION
+#
+# Original Project page: https://github.com/lefou/millw
+# Script Version: 0.4.12
+#
+# If you want to improve this script, please also contribute your changes back!
+#
+# Licensed under the Apache License, Version 2.0
+
+set -e
+
+if [ -z "${DEFAULT_MILL_VERSION}" ] ; then
+  DEFAULT_MILL_VERSION=0.12.10
+fi
+
+
+if [ -z "${GITHUB_RELEASE_CDN}" ] ; then
+  GITHUB_RELEASE_CDN=""
+fi
+
+
+MILL_REPO_URL="https://github.com/com-lihaoyi/mill"
+
+if [ -z "${CURL_CMD}" ] ; then
+  CURL_CMD=curl
+fi
+
+# Explicit commandline argument takes precedence over all other methods
+if [ "$1" = "--mill-version" ] ; then
+  shift
+  if [ "x$1" != "x" ] ; then
+    MILL_VERSION="$1"
+    shift
+  else
+    echo "You specified --mill-version without a version." 1>&2
+    echo "Please provide a version that matches one provided on" 1>&2
+    echo "${MILL_REPO_URL}/releases" 1>&2
+    false
+  fi
+fi
+
+# Please note, that if a MILL_VERSION is already set in the environment,
+# We reuse it's value and skip searching for a value.
+
+# If not already set, read .mill-version file
+if [ -z "${MILL_VERSION}" ] ; then
+  if [ -f ".mill-version" ] ; then
+    MILL_VERSION="$(tr '\r' '\n' < .mill-version | head -n 1 2> /dev/null)"
+  elif [ -f ".config/mill-version" ] ; then
+    MILL_VERSION="$(tr '\r' '\n' < .config/mill-version | head -n 1 2> /dev/null)"
+  fi
+fi
+
+MILL_USER_CACHE_DIR="${XDG_CACHE_HOME:-${HOME}/.cache}/mill"
+
+if [ -z "${MILL_DOWNLOAD_PATH}" ] ; then
+  MILL_DOWNLOAD_PATH="${MILL_USER_CACHE_DIR}/download"
+fi
+
+# If not already set, try to fetch newest from Github
+if [ -z "${MILL_VERSION}" ] ; then
+  # TODO: try to load latest version from release page
+  echo "No mill version specified." 1>&2
+  echo "You should provide a version via '.mill-version' file or --mill-version option." 1>&2
+
+  mkdir -p "${MILL_DOWNLOAD_PATH}"
+  LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest" 2>/dev/null || (
+    # we might be on OSX or BSD which don't have -d option for touch
+    # but probably a -A [-][[hh]mm]SS
+    touch "${MILL_DOWNLOAD_PATH}/.expire_latest"; touch -A -010000 "${MILL_DOWNLOAD_PATH}/.expire_latest"
+  ) || (
+    # in case we still failed, we retry the first touch command with the intention
+    # to show the (previously suppressed) error message
+    LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest"
+  )
+
+  # POSIX shell variant of bash's -nt operator, see https://unix.stackexchange.com/a/449744/6993
+  # if [ "${MILL_DOWNLOAD_PATH}/.latest" -nt "${MILL_DOWNLOAD_PATH}/.expire_latest" ] ; then
+  if [ -n "$(find -L "${MILL_DOWNLOAD_PATH}/.latest" -prune -newer "${MILL_DOWNLOAD_PATH}/.expire_latest")" ]; then
+    # we know a current latest version
+    MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null)
+  fi
+
+  if [ -z "${MILL_VERSION}" ] ; then
+    # we don't know a current latest version
+    echo "Retrieving latest mill version ..." 1>&2
+    LANG=C ${CURL_CMD} -s -i -f -I ${MILL_REPO_URL}/releases/latest 2> /dev/null  | grep --ignore-case Location: | sed s'/^.*tag\///' | tr -d '\r\n' > "${MILL_DOWNLOAD_PATH}/.latest"
+    MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null)
+  fi
+
+  if [ -z "${MILL_VERSION}" ] ; then
+    # Last resort
+    MILL_VERSION="${DEFAULT_MILL_VERSION}"
+    echo "Falling back to hardcoded mill version ${MILL_VERSION}" 1>&2
+  else
+    echo "Using mill version ${MILL_VERSION}" 1>&2
+  fi
+fi
+
+MILL_NATIVE_SUFFIX="-native"
+FULL_MILL_VERSION=$MILL_VERSION
+ARTIFACT_SUFFIX=""
+case "$MILL_VERSION" in
+    *"$MILL_NATIVE_SUFFIX")
+  MILL_VERSION=${MILL_VERSION%"$MILL_NATIVE_SUFFIX"}
+  if [ "$(expr substr $(uname -s) 1 5 2>/dev/null)" = "Linux" ]; then
+    if [ "$(uname -m)" = "aarch64" ]; then
+      ARTIFACT_SUFFIX="-native-linux-aarch64"
+    else
+      ARTIFACT_SUFFIX="-native-linux-amd64"
+    fi
+  elif [ "$(uname)" = "Darwin" ]; then
+    if [ "$(uname -m)" = "arm64" ]; then
+      ARTIFACT_SUFFIX="-native-mac-aarch64"
+    else
+      ARTIFACT_SUFFIX="-native-mac-amd64"
+    fi
+  else
+     echo "This native mill launcher supports only Linux and macOS." 1>&2
+     exit 1
+  fi
+esac
+
+MILL="${MILL_DOWNLOAD_PATH}/${FULL_MILL_VERSION}"
+
+try_to_use_system_mill() {
+  if [ "$(uname)" != "Linux" ]; then
+    return 0
+  fi
+
+  MILL_IN_PATH="$(command -v mill || true)"
+
+  if [ -z "${MILL_IN_PATH}" ]; then
+    return 0
+  fi
+
+  SYSTEM_MILL_FIRST_TWO_BYTES=$(head --bytes=2 "${MILL_IN_PATH}")
+  if [ "${SYSTEM_MILL_FIRST_TWO_BYTES}" = "#!" ]; then
+	  # MILL_IN_PATH is (very likely) a shell script and not the mill
+	  # executable, ignore it.
+	  return 0
+  fi
+
+  SYSTEM_MILL_PATH=$(readlink -e "${MILL_IN_PATH}")
+  SYSTEM_MILL_SIZE=$(stat --format=%s "${SYSTEM_MILL_PATH}")
+  SYSTEM_MILL_MTIME=$(stat --format=%y "${SYSTEM_MILL_PATH}")
+
+  if [ ! -d "${MILL_USER_CACHE_DIR}" ]; then
+    mkdir -p "${MILL_USER_CACHE_DIR}"
+  fi
+
+  SYSTEM_MILL_INFO_FILE="${MILL_USER_CACHE_DIR}/system-mill-info"
+  if [ -f "${SYSTEM_MILL_INFO_FILE}" ]; then
+    parseSystemMillInfo() {
+        LINE_NUMBER="${1}"
+        # Select the line number of the SYSTEM_MILL_INFO_FILE, cut the
+        # variable definition in that line in two halves and return
+        # the value, and finally remove the quotes.
+        sed -n "${LINE_NUMBER}p" "${SYSTEM_MILL_INFO_FILE}" |\
+            cut -d= -f2 |\
+            sed 's/"\(.*\)"/\1/'
+    }
+
+    CACHED_SYSTEM_MILL_PATH=$(parseSystemMillInfo 1)
+    CACHED_SYSTEM_MILL_VERSION=$(parseSystemMillInfo 2)
+    CACHED_SYSTEM_MILL_SIZE=$(parseSystemMillInfo 3)
+    CACHED_SYSTEM_MILL_MTIME=$(parseSystemMillInfo 4)
+
+    if [ "${SYSTEM_MILL_PATH}" = "${CACHED_SYSTEM_MILL_PATH}" ] \
+           && [ "${SYSTEM_MILL_SIZE}" = "${CACHED_SYSTEM_MILL_SIZE}" ] \
+           && [ "${SYSTEM_MILL_MTIME}" = "${CACHED_SYSTEM_MILL_MTIME}" ]; then
+      if [ "${CACHED_SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then
+          MILL="${SYSTEM_MILL_PATH}"
+          return 0
+      else
+          return 0
+      fi
+    fi
+  fi
+
+  SYSTEM_MILL_VERSION=$(${SYSTEM_MILL_PATH} --version | head -n1 | sed -n 's/^Mill.*version \(.*\)/\1/p')
+
+  cat <<EOF > "${SYSTEM_MILL_INFO_FILE}"
+CACHED_SYSTEM_MILL_PATH="${SYSTEM_MILL_PATH}"
+CACHED_SYSTEM_MILL_VERSION="${SYSTEM_MILL_VERSION}"
+CACHED_SYSTEM_MILL_SIZE="${SYSTEM_MILL_SIZE}"
+CACHED_SYSTEM_MILL_MTIME="${SYSTEM_MILL_MTIME}"
+EOF
+
+  if [ "${SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then
+    MILL="${SYSTEM_MILL_PATH}"
+  fi
+}
+try_to_use_system_mill
+
+# If not already downloaded, download it
+if [ ! -s "${MILL}" ] ; then
+
+  # support old non-XDG download dir
+  MILL_OLD_DOWNLOAD_PATH="${HOME}/.mill/download"
+  OLD_MILL="${MILL_OLD_DOWNLOAD_PATH}/${MILL_VERSION}"
+  if [ -x "${OLD_MILL}" ] ; then
+    MILL="${OLD_MILL}"
+  else
+    case $MILL_VERSION in
+      0.0.* | 0.1.* | 0.2.* | 0.3.* | 0.4.* )
+        DOWNLOAD_SUFFIX=""
+        DOWNLOAD_FROM_MAVEN=0
+        ;;
+      0.5.* | 0.6.* | 0.7.* | 0.8.* | 0.9.* | 0.10.* | 0.11.0-M* )
+        DOWNLOAD_SUFFIX="-assembly"
+        DOWNLOAD_FROM_MAVEN=0
+        ;;
+      *)
+        DOWNLOAD_SUFFIX="-assembly"
+        DOWNLOAD_FROM_MAVEN=1
+        ;;
+    esac
+
+    DOWNLOAD_FILE=$(mktemp mill.XXXXXX)
+
+    if [ "$DOWNLOAD_FROM_MAVEN" = "1" ] ; then
+      DOWNLOAD_URL="https://repo1.maven.org/maven2/com/lihaoyi/mill-dist${ARTIFACT_SUFFIX}/${MILL_VERSION}/mill-dist${ARTIFACT_SUFFIX}-${MILL_VERSION}.jar"
+    else
+      MILL_VERSION_TAG=$(echo "$MILL_VERSION" | sed -E 's/([^-]+)(-M[0-9]+)?(-.*)?/\1\2/')
+      DOWNLOAD_URL="${GITHUB_RELEASE_CDN}${MILL_REPO_URL}/releases/download/${MILL_VERSION_TAG}/${MILL_VERSION}${DOWNLOAD_SUFFIX}"
+      unset MILL_VERSION_TAG
+    fi
+
+    # TODO: handle command not found
+    echo "Downloading mill ${MILL_VERSION} from ${DOWNLOAD_URL} ..." 1>&2
+    ${CURL_CMD} -f -L -o "${DOWNLOAD_FILE}" "${DOWNLOAD_URL}"
+    chmod +x "${DOWNLOAD_FILE}"
+    mkdir -p "${MILL_DOWNLOAD_PATH}"
+    mv "${DOWNLOAD_FILE}" "${MILL}"
+
+    unset DOWNLOAD_FILE
+    unset DOWNLOAD_SUFFIX
+  fi
+fi
+
+if [ -z "$MILL_MAIN_CLI" ] ; then
+  MILL_MAIN_CLI="${0}"
+fi
+
+MILL_FIRST_ARG=""
+if [ "$1" = "--bsp" ] || [ "$1" = "-i" ] || [ "$1" = "--interactive" ] || [ "$1" = "--no-server" ] || [ "$1" = "--repl" ] || [ "$1" = "--help" ] ; then
+  # Need to preserve the first position of those listed options
+  MILL_FIRST_ARG=$1
+  shift
+fi
+
+unset MILL_DOWNLOAD_PATH
+unset MILL_OLD_DOWNLOAD_PATH
+unset OLD_MILL
+unset MILL_VERSION
+unset MILL_REPO_URL
+
+# We don't quote MILL_FIRST_ARG on purpose, so we can expand the empty value without quotes
+# shellcheck disable=SC2086
+exec "${MILL}" $MILL_FIRST_ARG -D "mill.main.cli=${MILL_MAIN_CLI}" "$@"