Specialized Layout for Decoupling Capacitors

[seveibar]

We want to make this less messy

official layout

[seveibar]

acceptable solution:

[seveibar]

/bounty $300

[algora-pbc]

💎 $300 bounty • tscircuit

Steps to solve:

1. Start working: Comment /attempt #15 with your implementation plan
2. Submit work: Create a pull request including /claim #15 in the PR body to claim the bounty
3. Receive payment: 100% of the bounty is received 2-5 days post-reward. Make sure you are eligible for payouts

❗ Important guidelines:

• Join our discord to get support from other contributors
• Links: tscircuit docs · tscircuit playground
• To claim a bounty for UI, you need to provide a short demo video of your changes in your pull request
• Do not ask to be assigned unless you've contributed before

Thank you for contributing to tscircuit/matchpack!

Attempt	Started (UTC)	Solution	Actions
🟢 @GhadiSaab	Feb 06, 2026, 09:21:03 PM	#30	Reward
🟢 @AouIssa	Feb 07, 2026, 05:24:12 AM	#31	Reward
🟢 @natinew77-creator	Jan 09, 2026, 04:21:19 PM	#28	Reward
🟢 @anzal787	Jan 10, 2026, 09:03:28 AM	#29	Reward
🟢 @lamb356	Dec 12, 2025, 04:52:24 AM	#27	Reward
🟢 @adilkadivala	Sep 21, 2025, 05:10:08 PM	WIP

[nailoo]

@seveibar, I'd like to take on this issue, can you assign it to me?

[adilkadivala]

/attempt #15

[lamb356]

I'd like to work on this. Could you clarify the expected behavior? Should capacitors be placed in a linear arrangement near specific pins (VCC/GND), or is there a specific algorithm/heuristic you have in mind?

[natinew77-creator]

/attempt #15

Implementation Plan: I will implement a specialized packing strategy for decoupling capacitors in matchpack to ensure a clean, professional layout. My plan includes:

Detection: Identifying decoupling capacitors based on their connection to power (VCC) and ground (GND) nets.

Alignment Heuristic: Implementing a linear row or grid layout for these capacitors to match the "acceptable solution" provided in the issue.

Proximity Optimization: Ensuring these groups are placed in close proximity to the relevant power pins of the main component (e.g., U3) to minimize trace length.

Visual Verification: Providing a demo video/screenshot of the resulting layout in the playground to confirm it meets the "non-messy" standard.