Propose/implement a solution to bad layout

[seveibar]

Improve the layout in #11

May require new technique or phase.

/bounty $150

[nailoo]

@seveibar, could you guide me on how to generate the schematic snapshot for reviewing the final layout? I checked the repro you mentioned, but I didn't see any snapshot added.

[ManbirS07]

/attempt #12
@seveibar May I work on this? Here is my implementation plan:

To improve layout clarity and eliminate overlaps, I will add two new phases to the pipeline:

1. Voltage Bias Phase
   Identify all nets and pins related to positive voltage (VCC, VDD, V+, etc.).
   Adjust chip placements so those connections are biased upward in the layout.
   This will make the schematic more intuitive and follow common conventions.

2. Overlap Resolution Phase
   After packing, detect any chip overlaps using bounding boxes.
   Iteratively nudge overlapping chips apart, using a simple force-based or grid-based algorithm.
   Ensure minimum spacing between chips for clarity.

Steps for the same:
I will design and implement both phases as new solver classes.
I will then integrate them into the pipeline in the LayoutPipelineSolver file and test with example circuits to verify improved clarity and organization of all the circuit components.

[seveibar]

@ManbirS07 we dont do assignments except for frequent contributors, but youre welcome to attempt!!

[ManbirS07]

@seveibar Hi, are any changes required, or is there something that I missed?
I am open to any feedback !!

[eyeaadil]

can i work on this issue ?

[Harihara04sudhan]

is this issue still there?

[anzal787]

Hi @mustafa7, I'm interested in fixing this layout issue. The editor link isn't loading the code properly for me. Could you please paste the code snippet directly here? I have a solution ready to improve the component placement and clear the trace overlaps.