From ec8157d14f698a9254eb89f971aa80ad7c754a62 Mon Sep 17 00:00:00 2001 From: Stefano Rivera Date: Thu, 30 Jan 2020 11:30:48 +0100 Subject: [PATCH 1/3] shadow_base was replaced by base_address --- targets/netv2/hdmi2pcie.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/netv2/hdmi2pcie.py b/targets/netv2/hdmi2pcie.py index b77c05970..3e9412dd5 100644 --- a/targets/netv2/hdmi2pcie.py +++ b/targets/netv2/hdmi2pcie.py @@ -78,7 +78,7 @@ def __init__(self, platform, *args, **kwargs): self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000) + self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, base_address=0x40000000) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone) From c4d544ae9566fb346d9b444be98b730727ba7bd5 Mon Sep 17 00:00:00 2001 From: Stefano Rivera Date: Fri, 31 Jan 2020 11:22:35 +0100 Subject: [PATCH 2/3] Get the base address from the memory map --- targets/netv2/hdmi2pcie.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/netv2/hdmi2pcie.py b/targets/netv2/hdmi2pcie.py index 3e9412dd5..e1961c48c 100644 --- a/targets/netv2/hdmi2pcie.py +++ b/targets/netv2/hdmi2pcie.py @@ -78,7 +78,8 @@ def __init__(self, platform, *args, **kwargs): self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge - self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, base_address=0x40000000) + self.submodules.pcie_bridge = LitePCIeWishboneBridge( + self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone) From 6cae00ad2cd2f373cc40c2da340acc83be2647ee Mon Sep 17 00:00:00 2001 From: Stefano Rivera Date: Fri, 31 Jan 2020 11:36:40 +0100 Subject: [PATCH 3/3] That is the default address_decoder --- targets/netv2/hdmi2pcie.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/netv2/hdmi2pcie.py b/targets/netv2/hdmi2pcie.py index e1961c48c..32b112a6a 100644 --- a/targets/netv2/hdmi2pcie.py +++ b/targets/netv2/hdmi2pcie.py @@ -79,7 +79,7 @@ def __init__(self, platform, *args, **kwargs): # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( - self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) + self.pcie_endpoint, base_address=self.mem_map["csr"]) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone)