AnalogFlow.md

Analog Design Flow

This design is a mixed-signal design.
The digital design flow isn't really applicable.

It is rather counterproductive to do a top down design.
The proof is in the analog layout pudding, and accurate extraction and modeling of the key analog elements.

In progress

• Lay out switched cascode transistor
  • pmos transistor with
    • gate contact
    • drain contact
    • source connected to current source transistor by pdiffusion abutment
  • arrangeable in an array by abutment
    • the width of the cascode transistor, plus the gate contact and poly spacing, determine the width of a unit current source
  • define as DRC clean parametrizable cell
    • cascode length
    • cascode width
• Extend cascode transistor to switched cascoded current source
  • for good matching and low 1/f noise, long and narrow
  • arrangeable in an array by abutment
  • shared poly for common bias voltage
• Mockup layout of a row of 256 unit current sources.
  It doesn't make sense to lay out a 256 element thermometer code DAC as one row,
  but this layout (column width: 282μm, height: 4.4μm)
  shows that the analog part of the design will fit within a HeiChips tile comfortably.

Proof-of-concept unit cell

width: 1.1μm, height 3.9μm

Layout

• DRC and LvS clean row of 16 unit current sources
• Test schematic with 2 unit sources as reference current mirror, 16 output sources

• DRC clean 2x64 unit current sources analog-only layout

• DRC clean 2x64 unit current sources analog-only layout

• Design cascode bias generator
  • Create test schematics to characterize g_m/I_d and g_m/g_o of transistors
  • Create test schematics to characterize g_o of cascoded current sources as function of voltage
• Extend cascode transistor to switched cascoded current source
  • define as DRC clean parametrizable cell
    • current source length
    • current source width
    • cascode length
    • cascode width
• Extract post-layout netlist for LvS
  to compare against xschem schematic

Gotchas

• Hierarchical bottom up analog design leads to crashes unless a verified best practice how to reference to hierarchical klayout libraries is established and verified
  Problem: This requires coordination by different domain experts, namely
  • klayout
  • IHP analog PDK
  • IHP analog standard cell library organization
  • any containers or other virtualization schemes that might be used
    In discussion forums, you get #worksforme answers from experts in one of the domains that don't take into account side effects.
    Such answers are less than useless.
    One czar of pcells needs to be volunteered to establish, publish, and maintain
    RECOMMENDED BEST PRACTICES about directory structures, instantiation hierarchies, how to include sub-layout cells (parametric or not) into klayout GDS files.
    Solution for now: Import sub-.gds schematic files into the top level schematic.
  • Invariant under various and sundry (and subtly incompatible) library integration schemes:
    The top level .gds file is self-contained.
• When thinking how to connect digital outputs to the cascode switches,
  • the transistors that switch between VDDA and V_casc,P should be directly adjacent to the switched sources
  • the pinout and form factor of the digital logic driving a row of 64 current sources needs to have matching form factor and pinout.
• Connecting V_bias,p by poly abutment is not just a bad idea because at cryogenic temperatures, poly may become highly resistive. (Solved)
  It is also advantageous to shield the current sources by metal1
  • so the connections to the switch/cascode transistors can be routed on top of the current sources without adverse effects on matching.
  • metal1 density rules are met without random metal1 fill on the most mismatch sensitive analog transistors.

The current mirror design isn't as robust to size variations as expected

I need to get an overview which simulation environment and device dimensions work and which don't.

• test_pcsource_DC.sch
  • Original dimensions:
    • source 0.55μm/2μm
    • cascode 0.3μm/0.3μm
    • bias transistor 6μm/0.15μm
      look sane at tt corner, 27°C.
• test_pcascsrc_DC.sch
  with adjustable parameters
  • Dimensions as drawn in pcsource2u.gds:
    • source 1.45μm/5μm
    • cascode 1.2μm/0.6μm
    • bias transistor 3μm/0.15μm, 6μm/0.15μm 12μm/0.15μm
      look sane at tt, ss, ff corners at -55°C, 27°C, 150°C.
      Gate leakage becomes a factor, especially at ff corner for large output voltage drops and I_ref=10nA.
• test_pcascsrc_mult_DC.sch
  with adjustable parameters and number of input and output currents
  • Dimensions as drawn in pcsource2u.gds:
    • source 1.45μm/5μm
    • cascode 1.2μm/0.6μm
    • bias transistor 6μm/0.15μm
      works for
      • 32 out, 2 in
      • 64 out, 2 in
      • 128 out, 4 in
        DC OP convergence problems for
      • 256 out, 8 in
• test_switchedsources_tran.sch
  with adjustable parameters and number of input and output currents
  • Dimensions as drawn in pcsource2u.gds:
    • source 1.45μm/5μm
    • cascode 1.2μm/0.6μm
    • bias transistor 6μm/0.15μm
      works when not using leaky lvpmos as bypass capacitors for the bias lines
• test_unitsource2u_DC.sch
  with adjustable number of input and output currents
  • Dimensions as drawn in pcsource2u.gds:
    • source 1.45μm/5μm
    • cascode 1.2μm/0.6μm
    • bias transistor 6μm/0.15μm
      works when not using leaky lvpmos as bypass capacitors for the bias lines
      works for
      • 1 out, 1 in
      • 64 out, 2 in
        With 66 current sources, gate leakage becomes a factor.
• test_unitsource2u_DC.tran
  with adjustable number of input and output currents
  • Dimensions as drawn in pcsource2u.gds:
    • source 1.45μm/5μm
    • cascode 1.2μm/0.6μm
    • bias transistor 6μm/0.15μm
      works for
      • 1 out, 1 in
        HVPMOS bypass varactors really make a difference
      • 64 out, 2 in
        The simulation takes forever

To do

• Extract post-layout netlist with parasitics

• Use suitable device models

  • that can handle millikelvin temperatures
  • Make the models available in the open environment
  • If the models don't exist, write them

• Find out how to generate analog/mixed signal pad frames

  • Preferably without involving the librelane overhead
    • Look at Krzysztof Herman's repositories and examples
  • Suitable for stand-alone submission of designs
    • in the last free IHP BiCMOS run
    • in the last free IHP CMOS engineering run
    • Find valid reasons to submit designs on later IHP characterization runs

• Design input current sinks for unit current generation

  • External input pad
  • on-chip current reference (if sufficient time and support)

References

IHP Open PDK
IHP Open PDK docs