Skip to content

Explore defining verilog and HW modules or subsets of IP cores  #20

@strangemonad

Description

@strangemonad

Can this bridge beyond pure software into hw implementations

e.g what could it mean to define things usable by chisel, verilog etc.

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions