From fe6bdcba14bfc5c1225b21ad48605e0592c52108 Mon Sep 17 00:00:00 2001 From: Henny Sipma Date: Mon, 9 Jun 2025 21:49:12 -0700 Subject: [PATCH 01/16] CHB:ARM:add disassembly support for FLDMIAX (arm) --- .../CHB/bchlibarm32/bCHDisassembleARMInstruction.ml | 12 ++++++++++++ .../bCHDisassembleARMInstructionTest.ml | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml b/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml index 64e1fb57..51d4faa7 100644 --- a/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml +++ b/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml @@ -1703,6 +1703,18 @@ let parse_misc_6_type (instr: doubleword_int) (cond: int) = (* VMOV , , *) VectorMoveDDS (c, VfpNone, rt WR, rt2 WR, rtd WR, dm RD) + (* FLDMIAX{}{}>Rn>{!}, *) + (* <6>01001DW11011<-imm7>1 *) + | (1, 1, 11) when (bv 22) = 0 && (bv 0) = 1 -> + let d = prefix_bit (bv 22) (b 15 12) in + let rnreg = get_arm_reg (b 19 16) in + let rn = arm_register_op rnreg in + let regs = (b 7 1) in + let rl = arm_extension_register_list_op XDouble d regs in + let mem = mk_arm_mem_multiple_op ~size:8 rnreg regs in + (* FLXMIAX, *) + FLoadMultipleIncrementAfter (false, c, rn RD, rl WR, mem RD) + (* <6>01D11<13><10><-imm8-> *) (* VPOP - A2 *) | (1, 3, 10) when (b 19 16) = 13 -> let d = postfix_bit (bv 22) (b 15 12) in diff --git a/CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml b/CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml index 279207be..3bf5e0c1 100644 --- a/CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml +++ b/CodeHawk/CHT/CHB_tests/bchlibarm32_tests/txbchlibarm32/bCHDisassembleARMInstructionTest.ml @@ -197,6 +197,10 @@ let arm_pc_relative () = let arm_vector () = let tests = [ + ("FLDMIAX", "210b90ec", + "FLDMIAX R0, {D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15}"); + ("FSTMIAX", "210b80ec", + "FSTMIAX R0, {D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15}"); ("VDUP.32", "474cfcf3", "VDUP.32 Q10, D7[1]"); ("VDUP.32-scalar", "622cfcf3", "VDUP.32 Q9, D18[1]"); ("VEOR-Q", "746106f3", "VEOR Q3, Q3, Q10"); From a1ebec48d3f4857499dfcbb0a9c9778ac219845d Mon Sep 17 00:00:00 2001 From: Henny Sipma Date: Mon, 9 Jun 2025 22:53:09 -0700 Subject: [PATCH 02/16] CHB:ARM:disassembly for STCL/STC2/LDC2 --- .../bCHDisassembleARMInstruction.ml | 38 +++++++++++++++++++ .../bCHDisassembleThumbInstruction.ml | 4 +- .../bCHDisassembleARMInstructionTest.ml | 5 ++- 3 files changed, 44 insertions(+), 3 deletions(-) diff --git a/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml b/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml index 51d4faa7..7482df6f 100644 --- a/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml +++ b/CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml @@ -1836,6 +1836,23 @@ let parse_misc_6_type (instr: doubleword_int) (cond: int) = (* FSTMIAX , *) FStoreMultipleIncrementAfter (false, c, rn RD, rl RD, mem WR) + (* <6>01D10<-imm8-> *) (* STCL - A1 *) + | (1, 2, 1) -> + let isindex = (bv 24) = 1 in + let isadd = (bv 23) = 1 in + let iswback = (bv 21) = 1 in + let islong = (bv 22) = 1 in + let crd = b 15 12 in + let coproc = b 11 8 in + let imm32 = 4 * (b 7 0) in + let offset = ARMImmOffset imm32 in + let rnreg = get_arm_reg (b 19 16) in + let mem = + mk_arm_offset_address_op + ~align:4 rnreg offset ~isadd ~isindex ~iswback in + (* STC{L} , , [, #+/-]{!} *) + StoreCoprocessor (islong, false, c, coproc, crd, mem WR, None) + (* <6>01D00<11><-imm8-> *) (* VSTM - A1-wb *) | (1, 2, 11) when (bv 0) = 0 -> let d = prefix_bit (bv 22) (b 15 12) in @@ -4750,6 +4767,27 @@ let parse_cond15 (instr: doubleword_int) (iaddr: doubleword_int) = (* BLX