From d9fd3d17a721301b6505d2e763b3047b1fdd29fb Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Fri, 21 Mar 2025 17:56:00 +0000 Subject: [PATCH 1/9] Added vivado stuff --- .../passes/graph/transforms/verilog/config.py | 58 +++++++++++++++++++ .../graph/transforms/verilog/config.tcl | 36 ++++++++++++ .../graph/transforms/verilog/generate.tcl | 26 +++++++++ 3 files changed, 120 insertions(+) create mode 100644 test/passes/graph/transforms/verilog/config.py create mode 100644 test/passes/graph/transforms/verilog/config.tcl create mode 100644 test/passes/graph/transforms/verilog/generate.tcl diff --git a/test/passes/graph/transforms/verilog/config.py b/test/passes/graph/transforms/verilog/config.py new file mode 100644 index 000000000..6555684f6 --- /dev/null +++ b/test/passes/graph/transforms/verilog/config.py @@ -0,0 +1,58 @@ +import os + +config_file = "config.tcl" + +template = { + "fc1_DATA_IN_0_PRECISION_0": 10, + "fc1_DATA_IN_0_PRECISION_1": 10, + "fc1_DATA_IN_0_TENSOR_SIZE_DIM_0": 20, + "fc1_DATA_IN_0_PARALLELISM_DIM_0": 4, + "fc1_DATA_IN_0_TENSOR_SIZE_DIM_1": 6, + "fc1_DATA_IN_0_PARALLELISM_DIM_1": 6, + "fc1_WEIGHT_PRECISION_0": 10, + "fc1_WEIGHT_PRECISION_1": 10, + "fc1_WEIGHT_TENSOR_SIZE_DIM_0": 20, + "fc1_WEIGHT_PARALLELISM_DIM_0": 4, + "fc1_WEIGHT_TENSOR_SIZE_DIM_1": 40, + "fc1_WEIGHT_PARALLELISM_DIM_1": 4, + "fc1_BIAS_PRECISION_0": 10, + "fc1_BIAS_PRECISION_1": 10, + "fc1_BIAS_TENSOR_SIZE_DIM_0": 40, + "fc1_BIAS_PARALLELISM_DIM_0": 4, + "fc1_BIAS_TENSOR_SIZE_DIM_1": 1, + "fc1_BIAS_PARALLELISM_DIM_1": 1, + "fc1_DATA_OUT_0_PRECISION_0": 10, + "fc1_DATA_OUT_0_TENSOR_SIZE_DIM_0": 40, + "fc1_DATA_OUT_0_PARALLELISM_DIM_0": 4, + "fc1_DATA_OUT_0_TENSOR_SIZE_DIM_1": 6, + "fc1_DATA_OUT_0_PARALLELISM_DIM_1": 6, + "fc1_DATA_OUT_0_PRECISION_1": 10, + "DATA_IN_0_PRECISION_0": 10, + "DATA_IN_0_PRECISION_1": 10, + "DATA_IN_0_TENSOR_SIZE_DIM_0": 20, + "DATA_IN_0_PARALLELISM_DIM_0": 4, + "DATA_IN_0_TENSOR_SIZE_DIM_1": 6, + "DATA_IN_0_PARALLELISM_DIM_1": 6, + "DATA_OUT_0_PRECISION_0": 10, + "DATA_OUT_0_TENSOR_SIZE_DIM_0": 40, + "DATA_OUT_0_PARALLELISM_DIM_0": 4, + "DATA_OUT_0_TENSOR_SIZE_DIM_1": 6, + "DATA_OUT_0_PARALLELISM_DIM_1": 6, + "DATA_OUT_0_PRECISION_1": 10, +} + + +def writeConfig(parameters): + with open(config_file, "w") as f: + for key, value in parameters.items(): + f.write(f"set PARAMS({key}) {value}\n") + + +def main(): + writeConfig(template) + print(f"Configuration written to {config_file}") + os.system('vivado -mode batch -nolog -nojou -source generate.tcl') + + +if __name__ == '__main__': + main() diff --git a/test/passes/graph/transforms/verilog/config.tcl b/test/passes/graph/transforms/verilog/config.tcl new file mode 100644 index 000000000..8fbe93bc2 --- /dev/null +++ b/test/passes/graph/transforms/verilog/config.tcl @@ -0,0 +1,36 @@ +set PARAMS(fc1_DATA_IN_0_PRECISION_0) 10 +set PARAMS(fc1_DATA_IN_0_PRECISION_1) 10 +set PARAMS(fc1_DATA_IN_0_TENSOR_SIZE_DIM_0) 20 +set PARAMS(fc1_DATA_IN_0_PARALLELISM_DIM_0) 4 +set PARAMS(fc1_DATA_IN_0_TENSOR_SIZE_DIM_1) 6 +set PARAMS(fc1_DATA_IN_0_PARALLELISM_DIM_1) 6 +set PARAMS(fc1_WEIGHT_PRECISION_0) 10 +set PARAMS(fc1_WEIGHT_PRECISION_1) 10 +set PARAMS(fc1_WEIGHT_TENSOR_SIZE_DIM_0) 20 +set PARAMS(fc1_WEIGHT_PARALLELISM_DIM_0) 4 +set PARAMS(fc1_WEIGHT_TENSOR_SIZE_DIM_1) 40 +set PARAMS(fc1_WEIGHT_PARALLELISM_DIM_1) 4 +set PARAMS(fc1_BIAS_PRECISION_0) 10 +set PARAMS(fc1_BIAS_PRECISION_1) 10 +set PARAMS(fc1_BIAS_TENSOR_SIZE_DIM_0) 40 +set PARAMS(fc1_BIAS_PARALLELISM_DIM_0) 4 +set PARAMS(fc1_BIAS_TENSOR_SIZE_DIM_1) 1 +set PARAMS(fc1_BIAS_PARALLELISM_DIM_1) 1 +set PARAMS(fc1_DATA_OUT_0_PRECISION_0) 10 +set PARAMS(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_0) 40 +set PARAMS(fc1_DATA_OUT_0_PARALLELISM_DIM_0) 4 +set PARAMS(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_1) 6 +set PARAMS(fc1_DATA_OUT_0_PARALLELISM_DIM_1) 6 +set PARAMS(fc1_DATA_OUT_0_PRECISION_1) 10 +set PARAMS(DATA_IN_0_PRECISION_0) 10 +set PARAMS(DATA_IN_0_PRECISION_1) 10 +set PARAMS(DATA_IN_0_TENSOR_SIZE_DIM_0) 20 +set PARAMS(DATA_IN_0_PARALLELISM_DIM_0) 4 +set PARAMS(DATA_IN_0_TENSOR_SIZE_DIM_1) 6 +set PARAMS(DATA_IN_0_PARALLELISM_DIM_1) 6 +set PARAMS(DATA_OUT_0_PRECISION_0) 10 +set PARAMS(DATA_OUT_0_TENSOR_SIZE_DIM_0) 40 +set PARAMS(DATA_OUT_0_PARALLELISM_DIM_0) 4 +set PARAMS(DATA_OUT_0_TENSOR_SIZE_DIM_1) 6 +set PARAMS(DATA_OUT_0_PARALLELISM_DIM_1) 6 +set PARAMS(DATA_OUT_0_PRECISION_1) 10 diff --git a/test/passes/graph/transforms/verilog/generate.tcl b/test/passes/graph/transforms/verilog/generate.tcl new file mode 100644 index 000000000..d58c26a95 --- /dev/null +++ b/test/passes/graph/transforms/verilog/generate.tcl @@ -0,0 +1,26 @@ + +create_project -in_memory -part xcku5p-ffvb676-2-e + +set_property board_part xilinx.com:kcu116:part0:1.5 [current_project] + +add_files {/home/omar/.mase/top/hardware/rtl/input_buffer.sv /home/omar/.mase/top/hardware/rtl/split2.sv /home/omar/.mase/top/hardware/rtl/or_tree_layer.sv /home/omar/.mase/top/hardware/rtl/top.sv /home/omar/.mase/top/hardware/rtl/unpacked_register_slice.sv /home/omar/.mase/top/hardware/rtl/join2.sv /home/omar/.mase/top/hardware/rtl/log2_max_abs.sv /home/omar/.mase/top/hardware/rtl/fc1_weight_source.sv /home/omar/.mase/top/hardware/rtl/ultraram.v /home/omar/.mase/top/hardware/rtl/skid_buffer.sv /home/omar/.mase/top/hardware/rtl/unpacked_mx_fifo.sv /home/omar/.mase/top/hardware/rtl/ultraram_fifo.sv /home/omar/.mase/top/hardware/rtl/mxint_linear.sv /home/omar/.mase/top/hardware/rtl/fixed_adder_tree_layer.sv /home/omar/.mase/top/hardware/rtl/fixed_dot_product.sv /home/omar/.mase/top/hardware/rtl/mxint_accumulator.sv /home/omar/.mase/top/hardware/rtl/mxint_dot_product.sv /home/omar/.mase/top/hardware/rtl/fixed_mult.sv /home/omar/.mase/top/hardware/rtl/fixed_vector_mult.sv /home/omar/.mase/top/hardware/rtl/fc1_bias_source.sv /home/omar/.mase/top/hardware/rtl/or_tree.sv /home/omar/.mase/top/hardware/rtl/mxint_cast.sv /home/omar/.mase/top/hardware/rtl/fixed_adder_tree.sv /home/omar/.mase/top/hardware/rtl/mxint_circular.sv /home/omar/.mase/top/hardware/rtl/mxint_register_slice.sv /home/omar/.mase/top/hardware/rtl/unpacked_skid_buffer.sv /home/omar/.mase/top/hardware/rtl/fifo.sv /home/omar/.mase/top/hardware/rtl/simple_dual_port_ram.sv /home/omar/.mase/top/hardware/rtl/join_n.sv /home/omar/.mase/top/hardware/rtl/blk_mem_gen_0.sv /home/omar/.mase/top/hardware/rtl/register_slice.sv} + +set_property top top [current_fileset] + +# Load parameters from the file +source config.tcl + +# Apply parameters dynamically +set generic_params "" +foreach key [array names PARAMS] { + append generic_params " -generic $key=$PARAMS($key)" +} + +# Run synthesis with dynamic parameters +eval "synth_design -mode out_of_context -top top -part xcku5p-ffvb676-2-e $generic_params" + +#launch_runs synth_1 -jobs 8 +#wait_on_run synth_1 + +#open_run synth_1 -name synth_1 +#report_utilization -name utilization_1 From c9fbef1f5db432f2d5d6b1cf7878587d966c556b Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Fri, 21 Mar 2025 16:58:52 +0000 Subject: [PATCH 2/9] Verilog format --- .../mxint_operators/rtl/mxint_accumulator.sv | 18 ++++++------- .../mxint_operators/rtl/mxint_cast.sv | 26 ++++++++++++------- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv index b15d558be..3cf59b344 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv @@ -20,17 +20,17 @@ module mxint_accumulator #( input logic rst, // Input Data - input logic signed [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], - input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, - input logic data_in_0_valid, - output logic data_in_0_ready, + input logic [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], + input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, + input logic data_in_0_valid, + output logic data_in_0_ready, // Output Data - output logic signed [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], - output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, - output logic data_out_0_valid, - input logic data_out_0_ready, - output logic [ COUNTER_WIDTH:0] accum_count + output logic [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], + output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, + output logic data_out_0_valid, + input logic data_out_0_ready, + output logic [ COUNTER_WIDTH:0] accum_count ); localparam RIGHT_PADDING = 2 ** DATA_IN_0_PRECISION_1; diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv index 07c372a84..606a1bafa 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv @@ -17,16 +17,16 @@ module mxint_cast #( input logic rst, // Input Data - input logic signed [IN_MAN_WIDTH-1:0] mdata_in [BLOCK_SIZE-1:0], - input logic [IN_EXP_WIDTH-1:0] edata_in, - input logic data_in_valid, - output logic data_in_ready, + input logic [IN_MAN_WIDTH-1:0] mdata_in [BLOCK_SIZE-1:0], + input logic [IN_EXP_WIDTH-1:0] edata_in, + input logic data_in_valid, + output logic data_in_ready, // Output Data - output logic signed [OUT_MAN_WIDTH-1:0] mdata_out [BLOCK_SIZE-1:0], - output logic [OUT_EXP_WIDTH-1:0] edata_out, - output logic data_out_valid, - input logic data_out_ready + output logic [OUT_MAN_WIDTH-1:0] mdata_out [BLOCK_SIZE-1:0], + output logic [OUT_EXP_WIDTH-1:0] edata_out, + output logic data_out_valid, + input logic data_out_ready ); // ============================= @@ -103,7 +103,9 @@ module mxint_cast #( if (FIFO_DEPTH == 0) begin always_comb begin - mbuffer_data_for_out = mdata_in; + for (int i = 0; i < BLOCK_SIZE; i++) begin + mbuffer_data_for_out[i] = $signed(mdata_in[i]); + end ebuffer_data_for_out = edata_in; buffer_data_for_out_valid = data_for_out_valid; data_for_out_ready = buffer_data_for_out_ready; @@ -129,6 +131,12 @@ module mxint_cast #( .data_out_ready(buffer_data_for_out_ready) ); + always_comb begin + for (int i = 0; i < BLOCK_SIZE; i++) begin + mbuffer_data_for_out[i] = $signed(fifo_out[i]); + end + end + end // ============================= From 6f37a1b500430a35dd3154954c0a7dbe1dc56433 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Fri, 21 Mar 2025 16:58:28 +0000 Subject: [PATCH 3/9] Modified code to make it syntheisable --- .../add_metadata/hardware_metadata_layers.py | 5 ++++ .../mxint_operators/rtl/mxint_accumulator.sv | 20 ++++++------- .../mxint_operators/rtl/mxint_cast.sv | 28 +++++++++++-------- .../mxint_operators/rtl/mxint_linear.sv | 1 - 4 files changed, 31 insertions(+), 23 deletions(-) diff --git a/src/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py b/src/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py index 9753c2057..409f560d3 100644 --- a/src/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py +++ b/src/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py @@ -88,6 +88,11 @@ class IpDescType(TypedDict): "common/rtl/unpacked_register_slice.sv", "common/rtl/split2.sv", "common/rtl/join2.sv", + "common/rtl/join_n.sv", + "common/rtl/register_slice.sv", + "memory/rtl/fifo.sv", + "memory/rtl/blk_mem_gen_0.sv", + "memory/rtl/simple_dual_port_ram.sv", "memory/rtl/unpacked_skid_buffer.sv", "memory/rtl/skid_buffer.sv", "memory/rtl/ultraram_fifo.sv", diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv index 3cf59b344..1ee3569a8 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv @@ -20,17 +20,17 @@ module mxint_accumulator #( input logic rst, // Input Data - input logic [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], - input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, - input logic data_in_0_valid, - output logic data_in_0_ready, + input logic [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], + input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, + input logic data_in_0_valid, + output logic data_in_0_ready, // Output Data - output logic [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], - output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, - output logic data_out_0_valid, - input logic data_out_0_ready, - output logic [ COUNTER_WIDTH:0] accum_count + output logic [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], + output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, + output logic data_out_0_valid, + input logic data_out_0_ready, + output logic [ COUNTER_WIDTH:0] accum_count ); localparam RIGHT_PADDING = 2 ** DATA_IN_0_PRECISION_1; @@ -98,7 +98,7 @@ module mxint_accumulator #( shifted_mdata_out_0[i] = mdata_out_0[i]; end else begin shifted_mdata_in_0[i] = padded_mdata_in_0[i]; - shifted_mdata_out_0[i] = mdata_out_0[i] >>> -shift; + shifted_mdata_out_0[i] = $signed(mdata_out_0[i]) >>> -shift; end end diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv index 606a1bafa..4bdbc7523 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv @@ -18,15 +18,15 @@ module mxint_cast #( // Input Data input logic [IN_MAN_WIDTH-1:0] mdata_in [BLOCK_SIZE-1:0], - input logic [IN_EXP_WIDTH-1:0] edata_in, - input logic data_in_valid, - output logic data_in_ready, + input logic [IN_EXP_WIDTH-1:0] edata_in, + input logic data_in_valid, + output logic data_in_ready, // Output Data output logic [OUT_MAN_WIDTH-1:0] mdata_out [BLOCK_SIZE-1:0], - output logic [OUT_EXP_WIDTH-1:0] edata_out, - output logic data_out_valid, - input logic data_out_ready + output logic [OUT_EXP_WIDTH-1:0] edata_out, + output logic data_out_valid, + input logic data_out_ready ); // ============================= @@ -50,6 +50,7 @@ module mxint_cast #( logic data_for_max_valid, data_for_max_ready, data_for_out_valid, data_for_out_ready; logic signed [IN_MAN_WIDTH-1:0] mbuffer_data_for_out[BLOCK_SIZE-1:0]; + logic [IN_MAN_WIDTH-1:0] fifo_out[BLOCK_SIZE-1:0]; logic [IN_EXP_WIDTH-1:0] ebuffer_data_for_out; logic buffer_data_for_out_valid, buffer_data_for_out_ready; @@ -103,7 +104,8 @@ module mxint_cast #( if (FIFO_DEPTH == 0) begin always_comb begin - for (int i = 0; i < BLOCK_SIZE; i++) begin + for (int i = 0; i < BLOCK_SIZE; i++) + begin mbuffer_data_for_out[i] = $signed(mdata_in[i]); end ebuffer_data_for_out = edata_in; @@ -125,16 +127,18 @@ module mxint_cast #( .edata_in(edata_in), .data_in_valid(data_for_out_valid), .data_in_ready(data_for_out_ready), - .mdata_out(mbuffer_data_for_out), + .mdata_out(fifo_out), .edata_out(ebuffer_data_for_out), .data_out_valid(buffer_data_for_out_valid), .data_out_ready(buffer_data_for_out_ready) ); - always_comb begin - for (int i = 0; i < BLOCK_SIZE; i++) begin - mbuffer_data_for_out[i] = $signed(fifo_out[i]); - end + always_comb + begin + for (int i = 0; i < BLOCK_SIZE; i++) + begin + mbuffer_data_for_out[i] = $signed(fifo_out[i]); + end end end diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_linear.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_linear.sv index 312b8f4f0..5682a211e 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_linear.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_linear.sv @@ -288,7 +288,6 @@ module mxint_linear #( assign acc_data_out_ready = cast_data_out_0_ready; assign cast_data_out_0_valid = acc_data_out_valid; assign cast_edata_out_0 = acc_edata_out; - assign bias_ready = 1; mxint_cast #( .IN_MAN_WIDTH(LOSSLESS_OUT_WIDTH), From 1d5dca06ef23c3d4b67ff62f0577c067f9790b45 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Sat, 22 Mar 2025 22:20:30 +0000 Subject: [PATCH 4/9] Working Optuna Fully Deep Connected Analysis --- .../verilog/analyse_mxint_resources.py | 173 +++++++++++++++ .../passes/graph/transforms/verilog/config.py | 209 ++++++++++++++---- .../graph/transforms/verilog/config.tcl | 36 --- .../graph/transforms/verilog/generate.tcl | 32 +-- .../verilog/test_emit_verilog_mxint.py | 33 +-- 5 files changed, 373 insertions(+), 110 deletions(-) create mode 100644 test/passes/graph/transforms/verilog/analyse_mxint_resources.py delete mode 100644 test/passes/graph/transforms/verilog/config.tcl diff --git a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py new file mode 100644 index 000000000..7672586c5 --- /dev/null +++ b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py @@ -0,0 +1,173 @@ +import os, re, random +import optuna +from optuna import study +from optuna.samplers import TPESampler, GridSampler +import json +from chop.tools.logger import set_logging_verbosity +from chop.tools import get_logger +from test_emit_verilog_mxint import MLP, shared_emit_verilog_mxint +import os, sys, logging, traceback, pdb +import pytest +import toml +import torch +import torch.nn as nn +import chop as chop +import chop.passes as passes +from pathlib import Path +from chop.actions import simulate +from chop.passes.graph.analysis.report.report_node import report_node_type_analysis_pass +from chop.tools.logger import set_logging_verbosity +from chop.tools import get_logger + +config_file = "config.tcl" + +set_logging_verbosity("debug") + +logger = get_logger(__name__) + +batch_size = 6 +block_size = 4 + +search_space = { + "IN_FEATURES" : [block_size * i for i in range(1, 4)], + "OUT_FEATURES" : [block_size * i for i in range(1, 4)], + "m_width" : [i for i in range(3, 6)], + "e_width" : [i for i in range(3, 6)] +} + +def dump_param(trial_number, quan_args, filename="output.json"): + try: + with open(filename, "r") as file: + data = json.load(file) + except (FileNotFoundError, json.JSONDecodeError): + data = {} + + data[str(trial_number)] = quan_args + + with open(filename, "w") as file: + json.dump(data, file, indent=4) + + +def write_value(trial_number, name, value, filename="output.json"): + try: + with open(filename, "r") as file: + data = json.load(file) + except (FileNotFoundError, json.JSONDecodeError): + data = {} + + if str(trial_number) in data.keys(): + data[str(trial_number)][name] = value + else: + data[str(trial_number)] = {name : value} + + with open(filename, "w") as file: + json.dump(data, file, indent=4) + +def get_params(trial): + + block_size = trial.suggest_int('block_size', 2, 10) + batch_parallelism = random.randint(2, 10) + mlp_depth = random.randint(1, 10) + mlp_features = [block_size * random.randint(1, 10) for i in range(mlp_depth + 1)] + + params = { + "seed": trial.number, + "block_size": block_size, + "batch_parallelism": batch_parallelism, + "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), + "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), + "batches": batch_parallelism * random.randint(1, 10), + "num_batches": random.randint(1, 10), + } + + mlp = MLP(mlp_features) + input_shape = (mlp_features[0],) + + logger.info( + f"{block_size=}, {batch_parallelism=}, {params['e_width']=}, {params['m_width']=}, {params['batches']=}" + ) + + mg, mlp = shared_emit_verilog_mxint(mlp, input_shape, params, simulate=False) + + return params, mg, mlp + +def writeTrialNumber(trial_number): + with open(config_file, "w") as f: + f.write(f'set trial_number {trial_number}\n') + +def extract_site_type_used_util(filename): + site_data = {} + with open(filename, 'r') as file: + lines = file.readlines() + + pattern = re.compile(r'\|\s*([^|]+?)\s*\|\s*(\d+)\s*\|.*?\|\s*(\d+\.\d+)\s*\|') + + for line in lines: + match = pattern.match(line) + if match: + site_type = match.group(1).strip() + used = int(match.group(2).strip()) + util = float(match.group(3).strip()) + site_data[site_type] = {'Used': used, 'Util%': util} + + return site_data + +def get_bram_uram_util(filename): + site_data = extract_site_type_used_util(filename) + bram_util = site_data.get("Block RAM Tile", {}).get("Util%", 0.0) + uram_util = site_data.get("URAM", {}).get("Util%", 0.0) + return {"bram": bram_util, "uram": uram_util} + +def getResources(trial): + params, mg, mlp = get_params(trial) + dump_param(trial.number, params) + writeTrialNumber(trial.number) + # os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') + bram_utils = get_bram_uram_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') + clb_luts = extract_site_type_used_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') + out = clb_luts['CLB LUTs*']['Util%'] + clb_luts['CLB Registers']['Util%'] + clb_luts['CARRY8']['Util%'] + bram_utils['bram'] + bram_utils['uram'] + write_value(trial.number, 'resource_score', out) + return out + +def getAccuracy(trial): + params, mg, mlp = get_params(trial) + quantized = mg.model + + criterion = nn.MSELoss() + total_mse = 0.0 + + for _ in range(100): + x = torch.randn(params['batches'], mg.model[0].in_features) # Generate random input + y1 = quantized(x) + y2 = mlp(x) + mse = criterion(y1, y2) + total_mse += mse.item() + + avg_mse = total_mse / 100 + + write_value(trial.number, 'avg_mse', avg_mse) + return avg_mse + + +def main(): + sampler = TPESampler() + + study = optuna.create_study( + directions=["minimize", "minimize"], + study_name="resource_accuracy_optimiser", + sampler=sampler + ) + + study.optimize( + lambda trial: (getResources(trial), getAccuracy(trial)), + n_trials=1, + timeout=60*60*24, + n_jobs=1 + ) + + print("Best trials:") + for trial in study.best_trials: + print(f"Trial {trial.number}: {trial.values}") + +if __name__ == '__main__': + main() \ No newline at end of file diff --git a/test/passes/graph/transforms/verilog/config.py b/test/passes/graph/transforms/verilog/config.py index 6555684f6..b53855dbc 100644 --- a/test/passes/graph/transforms/verilog/config.py +++ b/test/passes/graph/transforms/verilog/config.py @@ -1,58 +1,177 @@ -import os +import os, re, random +import optuna +from optuna import study +from optuna.samplers import TPESampler, GridSampler +import json +from chop.tools.logger import set_logging_verbosity +from chop.tools import get_logger +from test_emit_verilog_mxint import MLP, shared_emit_verilog_mxint +import os, sys, logging, traceback, pdb +import pytest +import toml +import torch +import torch.nn as nn +import chop as chop +import chop.passes as passes +from pathlib import Path +from chop.actions import simulate +from chop.passes.graph.analysis.report.report_node import report_node_type_analysis_pass +from chop.tools.logger import set_logging_verbosity +from chop.tools import get_logger config_file = "config.tcl" -template = { - "fc1_DATA_IN_0_PRECISION_0": 10, - "fc1_DATA_IN_0_PRECISION_1": 10, - "fc1_DATA_IN_0_TENSOR_SIZE_DIM_0": 20, - "fc1_DATA_IN_0_PARALLELISM_DIM_0": 4, - "fc1_DATA_IN_0_TENSOR_SIZE_DIM_1": 6, - "fc1_DATA_IN_0_PARALLELISM_DIM_1": 6, - "fc1_WEIGHT_PRECISION_0": 10, - "fc1_WEIGHT_PRECISION_1": 10, - "fc1_WEIGHT_TENSOR_SIZE_DIM_0": 20, - "fc1_WEIGHT_PARALLELISM_DIM_0": 4, - "fc1_WEIGHT_TENSOR_SIZE_DIM_1": 40, - "fc1_WEIGHT_PARALLELISM_DIM_1": 4, - "fc1_BIAS_PRECISION_0": 10, - "fc1_BIAS_PRECISION_1": 10, - "fc1_BIAS_TENSOR_SIZE_DIM_0": 40, - "fc1_BIAS_PARALLELISM_DIM_0": 4, - "fc1_BIAS_TENSOR_SIZE_DIM_1": 1, - "fc1_BIAS_PARALLELISM_DIM_1": 1, - "fc1_DATA_OUT_0_PRECISION_0": 10, - "fc1_DATA_OUT_0_TENSOR_SIZE_DIM_0": 40, - "fc1_DATA_OUT_0_PARALLELISM_DIM_0": 4, - "fc1_DATA_OUT_0_TENSOR_SIZE_DIM_1": 6, - "fc1_DATA_OUT_0_PARALLELISM_DIM_1": 6, - "fc1_DATA_OUT_0_PRECISION_1": 10, - "DATA_IN_0_PRECISION_0": 10, - "DATA_IN_0_PRECISION_1": 10, - "DATA_IN_0_TENSOR_SIZE_DIM_0": 20, - "DATA_IN_0_PARALLELISM_DIM_0": 4, - "DATA_IN_0_TENSOR_SIZE_DIM_1": 6, - "DATA_IN_0_PARALLELISM_DIM_1": 6, - "DATA_OUT_0_PRECISION_0": 10, - "DATA_OUT_0_TENSOR_SIZE_DIM_0": 40, - "DATA_OUT_0_PARALLELISM_DIM_0": 4, - "DATA_OUT_0_TENSOR_SIZE_DIM_1": 6, - "DATA_OUT_0_PARALLELISM_DIM_1": 6, - "DATA_OUT_0_PRECISION_1": 10, +set_logging_verbosity("debug") + +logger = get_logger(__name__) + +batch_size = 6 +block_size = 4 + +search_space = { + "IN_FEATURES" : [block_size * i for i in range(1, 4)], + "OUT_FEATURES" : [block_size * i for i in range(1, 4)], + "m_width" : [i for i in range(3, 6)], + "e_width" : [i for i in range(3, 6)] } +def dump_param(trial_number, quan_args, filename="output.json"): + try: + with open(filename, "r") as file: + data = json.load(file) + except (FileNotFoundError, json.JSONDecodeError): + data = {} + + data[str(trial_number)] = quan_args + + with open(filename, "w") as file: + json.dump(data, file, indent=4) + + +def write_value(trial_number, name, value, filename="output.json"): + try: + with open(filename, "r") as file: + data = json.load(file) + except (FileNotFoundError, json.JSONDecodeError): + data = {} + + if str(trial_number) in data.keys(): + data[str(trial_number)][name] = value + else: + data[str(trial_number)] = {name : value} + + with open(filename, "w") as file: + json.dump(data, file, indent=4) + +def get_params(trial): + + block_size = trial.suggest_int('block_size', 2, 10) + batch_parallelism = random.randint(2, 10) + mlp_depth = random.randint(1, 10) + mlp_features = [block_size * random.randint(1, 10) for i in range(mlp_depth + 1)] + + params = { + "seed": trial.number, + "block_size": block_size, + "batch_parallelism": batch_parallelism, + "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), + "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), + "batches": batch_parallelism * random.randint(1, 10), + "num_batches": random.randint(1, 10), + } + + mlp = MLP(mlp_features) + input_shape = (mlp_features[0],) + + dump_param(trial.number, trial.params) + + logger.info( + f"{block_size=}, {batch_parallelism=}, {params['e_width']=}, {params['m_width']=}, {params['batches']=}" + ) -def writeConfig(parameters): + mg, mlp = shared_emit_verilog_mxint(mlp, input_shape, params, simulate=False) + + return params, mg, mlp + +def writeTrialNumber(trial_number): with open(config_file, "w") as f: - for key, value in parameters.items(): - f.write(f"set PARAMS({key}) {value}\n") + f.write(f'set trial_number {trial_number}\n') + +def extract_site_type_used_util(filename): + site_data = {} + with open(filename, 'r') as file: + lines = file.readlines() + + pattern = re.compile(r'\|\s*([^|]+?)\s*\|\s*(\d+)\s*\|.*?\|\s*(\d+\.\d+)\s*\|') + + for line in lines: + match = pattern.match(line) + if match: + site_type = match.group(1).strip() + used = int(match.group(2).strip()) + util = float(match.group(3).strip()) + site_data[site_type] = {'Used': used, 'Util%': util} + + return site_data + +def get_bram_uram_util(filename): + site_data = extract_site_type_used_util(filename) + bram_util = site_data.get("Block RAM Tile", {}).get("Util%", 0.0) + uram_util = site_data.get("URAM", {}).get("Util%", 0.0) + return {"bram": bram_util, "uram": uram_util} + +def getResources(trial): + _, mg, mlp = get_params(trial) + writeTrialNumber(trial.number) + # os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') + bram_utils = get_bram_uram_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') + clb_luts = extract_site_type_used_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') + out = clb_luts['CLB LUTs*']['Util%'] + clb_luts['CLB Registers']['Util%'] + clb_luts['CARRY8']['Util%'] + bram_utils['bram'] + bram_utils['uram'] + write_value(trial.number, 'resource_score', out) + return out + +def getAccuracy(trial): + params, mg, mlp = get_params(trial) + quantized = mg.model + + criterion = nn.MSELoss() + total_mse = 0.0 + + for _ in range(100): + x = torch.randn(params['batches'], mg.model[0].in_features) # Generate random input + y1 = quantized(x) + y2 = mlp(x) + mse = criterion(y1, y2) + total_mse += mse.item() + + avg_mse = total_mse / 100 + + write_value(trial.number, 'avg_mse', avg_mse) + return avg_mse def main(): - writeConfig(template) - print(f"Configuration written to {config_file}") - os.system('vivado -mode batch -nolog -nojou -source generate.tcl') + sampler = TPESampler() + + study = optuna.create_study( + directions=["minimize", "minimize"], + study_name="resource_accuracy_optimiser", + sampler=sampler + ) + + study.optimize( + lambda trial: (getResources(trial), getAccuracy(trial)), + n_trials=1, + timeout=60*60*24, + n_jobs=1 + ) + print("Best trials:") + for trial in study.best_trials: + print(f"Trial {trial.number}: {trial.values}") if __name__ == '__main__': - main() + write_value(0, "avg_msg", 0.1234) + write_value(0, "new_metric", 0.5678) + write_value(1, "avg_msg", 0.4321) + # main() diff --git a/test/passes/graph/transforms/verilog/config.tcl b/test/passes/graph/transforms/verilog/config.tcl deleted file mode 100644 index 8fbe93bc2..000000000 --- a/test/passes/graph/transforms/verilog/config.tcl +++ /dev/null @@ -1,36 +0,0 @@ -set PARAMS(fc1_DATA_IN_0_PRECISION_0) 10 -set PARAMS(fc1_DATA_IN_0_PRECISION_1) 10 -set PARAMS(fc1_DATA_IN_0_TENSOR_SIZE_DIM_0) 20 -set PARAMS(fc1_DATA_IN_0_PARALLELISM_DIM_0) 4 -set PARAMS(fc1_DATA_IN_0_TENSOR_SIZE_DIM_1) 6 -set PARAMS(fc1_DATA_IN_0_PARALLELISM_DIM_1) 6 -set PARAMS(fc1_WEIGHT_PRECISION_0) 10 -set PARAMS(fc1_WEIGHT_PRECISION_1) 10 -set PARAMS(fc1_WEIGHT_TENSOR_SIZE_DIM_0) 20 -set PARAMS(fc1_WEIGHT_PARALLELISM_DIM_0) 4 -set PARAMS(fc1_WEIGHT_TENSOR_SIZE_DIM_1) 40 -set PARAMS(fc1_WEIGHT_PARALLELISM_DIM_1) 4 -set PARAMS(fc1_BIAS_PRECISION_0) 10 -set PARAMS(fc1_BIAS_PRECISION_1) 10 -set PARAMS(fc1_BIAS_TENSOR_SIZE_DIM_0) 40 -set PARAMS(fc1_BIAS_PARALLELISM_DIM_0) 4 -set PARAMS(fc1_BIAS_TENSOR_SIZE_DIM_1) 1 -set PARAMS(fc1_BIAS_PARALLELISM_DIM_1) 1 -set PARAMS(fc1_DATA_OUT_0_PRECISION_0) 10 -set PARAMS(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_0) 40 -set PARAMS(fc1_DATA_OUT_0_PARALLELISM_DIM_0) 4 -set PARAMS(fc1_DATA_OUT_0_TENSOR_SIZE_DIM_1) 6 -set PARAMS(fc1_DATA_OUT_0_PARALLELISM_DIM_1) 6 -set PARAMS(fc1_DATA_OUT_0_PRECISION_1) 10 -set PARAMS(DATA_IN_0_PRECISION_0) 10 -set PARAMS(DATA_IN_0_PRECISION_1) 10 -set PARAMS(DATA_IN_0_TENSOR_SIZE_DIM_0) 20 -set PARAMS(DATA_IN_0_PARALLELISM_DIM_0) 4 -set PARAMS(DATA_IN_0_TENSOR_SIZE_DIM_1) 6 -set PARAMS(DATA_IN_0_PARALLELISM_DIM_1) 6 -set PARAMS(DATA_OUT_0_PRECISION_0) 10 -set PARAMS(DATA_OUT_0_TENSOR_SIZE_DIM_0) 40 -set PARAMS(DATA_OUT_0_PARALLELISM_DIM_0) 4 -set PARAMS(DATA_OUT_0_TENSOR_SIZE_DIM_1) 6 -set PARAMS(DATA_OUT_0_PARALLELISM_DIM_1) 6 -set PARAMS(DATA_OUT_0_PRECISION_1) 10 diff --git a/test/passes/graph/transforms/verilog/generate.tcl b/test/passes/graph/transforms/verilog/generate.tcl index d58c26a95..6f80fa788 100644 --- a/test/passes/graph/transforms/verilog/generate.tcl +++ b/test/passes/graph/transforms/verilog/generate.tcl @@ -1,26 +1,30 @@ create_project -in_memory -part xcku5p-ffvb676-2-e - set_property board_part xilinx.com:kcu116:part0:1.5 [current_project] -add_files {/home/omar/.mase/top/hardware/rtl/input_buffer.sv /home/omar/.mase/top/hardware/rtl/split2.sv /home/omar/.mase/top/hardware/rtl/or_tree_layer.sv /home/omar/.mase/top/hardware/rtl/top.sv /home/omar/.mase/top/hardware/rtl/unpacked_register_slice.sv /home/omar/.mase/top/hardware/rtl/join2.sv /home/omar/.mase/top/hardware/rtl/log2_max_abs.sv /home/omar/.mase/top/hardware/rtl/fc1_weight_source.sv /home/omar/.mase/top/hardware/rtl/ultraram.v /home/omar/.mase/top/hardware/rtl/skid_buffer.sv /home/omar/.mase/top/hardware/rtl/unpacked_mx_fifo.sv /home/omar/.mase/top/hardware/rtl/ultraram_fifo.sv /home/omar/.mase/top/hardware/rtl/mxint_linear.sv /home/omar/.mase/top/hardware/rtl/fixed_adder_tree_layer.sv /home/omar/.mase/top/hardware/rtl/fixed_dot_product.sv /home/omar/.mase/top/hardware/rtl/mxint_accumulator.sv /home/omar/.mase/top/hardware/rtl/mxint_dot_product.sv /home/omar/.mase/top/hardware/rtl/fixed_mult.sv /home/omar/.mase/top/hardware/rtl/fixed_vector_mult.sv /home/omar/.mase/top/hardware/rtl/fc1_bias_source.sv /home/omar/.mase/top/hardware/rtl/or_tree.sv /home/omar/.mase/top/hardware/rtl/mxint_cast.sv /home/omar/.mase/top/hardware/rtl/fixed_adder_tree.sv /home/omar/.mase/top/hardware/rtl/mxint_circular.sv /home/omar/.mase/top/hardware/rtl/mxint_register_slice.sv /home/omar/.mase/top/hardware/rtl/unpacked_skid_buffer.sv /home/omar/.mase/top/hardware/rtl/fifo.sv /home/omar/.mase/top/hardware/rtl/simple_dual_port_ram.sv /home/omar/.mase/top/hardware/rtl/join_n.sv /home/omar/.mase/top/hardware/rtl/blk_mem_gen_0.sv /home/omar/.mase/top/hardware/rtl/register_slice.sv} +# /home/omar/.mase/top/hardware/rtl/ +add_files -fileset sources_1 /home/omar/.mase/top/hardware/rtl/ set_property top top [current_fileset] -# Load parameters from the file source config.tcl -# Apply parameters dynamically -set generic_params "" -foreach key [array names PARAMS] { - append generic_params " -generic $key=$PARAMS($key)" -} +puts "Trial: ${trial_number}" + +eval "synth_design -mode out_of_context -top top -part xcku5p-ffvb676-2-e" + +save_project_as -force my_project + +launch_runs synth_1 -jobs 12 +wait_on_run synth_1 + +open_run synth_1 +report_utilization -file "/home/omar/Documents/year-4/adls/mase/resources/util_${trial_number}.txt" -# Run synthesis with dynamic parameters -eval "synth_design -mode out_of_context -top top -part xcku5p-ffvb676-2-e $generic_params" +# launch_runs synth_1 -jobs 12 +# wait_on_run synth_1 -#launch_runs synth_1 -jobs 8 -#wait_on_run synth_1 +# open_run synth_1 -name synth_1 +# report_utilization -name utilization_1 -#open_run synth_1 -name synth_1 -#report_utilization -name utilization_1 +# write_report -format csv -file "utilization_${trial_number}.xml" utilization_1 \ No newline at end of file diff --git a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py index e031c956f..74e3ef59c 100644 --- a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py +++ b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py @@ -107,7 +107,7 @@ def forward(self, x): shared_emit_verilog_mxint(linear, input_shape, params) -def shared_emit_verilog_mxint(model, input_shape, params: dict): +def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = True): # Set seeds torch.manual_seed(params["seed"]) random.seed(params["seed"]) @@ -176,26 +176,29 @@ def shared_emit_verilog_mxint(model, input_shape, params: dict): mg, _ = passes.emit_verilog_top_transform_pass(mg) mg, _ = passes.emit_bram_transform_pass(mg) mg, _ = passes.emit_internal_rtl_transform_pass(mg) - mg, _ = passes.emit_cocotb_transform_pass( - mg, - pass_args={ - "wait_time": 10 * block_size * batch_parallelism * num_batches, - "wait_unit": "us", - "num_batches": num_batches, - }, - ) - simulate( - skip_build=False, - skip_test=False, - simulator="verilator", - waves=True, - ) + if (simulate): + mg, _ = passes.emit_cocotb_transform_pass( + mg, + pass_args={ + "wait_time": 10 * block_size * batch_parallelism * num_batches, + "wait_unit": "us", + "num_batches": num_batches, + }, + ) + + simulate( + skip_build=False, + skip_test=False, + simulator="verilator", + waves=True, + ) logger.info( f"{block_size=}, {batch_parallelism=}, {m_width=}, {e_width=}, {batches=}" ) + return model, mg.model if __name__ == "__main__": seed = os.getenv("COCOTB_SEED") From ce3fd2aabce07d3422eea4bd1c9972b6e91f7515 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Sun, 23 Mar 2025 12:57:39 +0000 Subject: [PATCH 5/9] migrating to run host --- .../verilog/analyse_mxint_resources.py | 26 ++++++------------- .../graph/transforms/verilog/generate.tcl | 7 ++--- 2 files changed, 12 insertions(+), 21 deletions(-) diff --git a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py index 7672586c5..efa8a77cb 100644 --- a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py +++ b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py @@ -25,16 +25,6 @@ logger = get_logger(__name__) -batch_size = 6 -block_size = 4 - -search_space = { - "IN_FEATURES" : [block_size * i for i in range(1, 4)], - "OUT_FEATURES" : [block_size * i for i in range(1, 4)], - "m_width" : [i for i in range(3, 6)], - "e_width" : [i for i in range(3, 6)] -} - def dump_param(trial_number, quan_args, filename="output.json"): try: with open(filename, "r") as file: @@ -66,9 +56,9 @@ def write_value(trial_number, name, value, filename="output.json"): def get_params(trial): block_size = trial.suggest_int('block_size', 2, 10) - batch_parallelism = random.randint(2, 10) - mlp_depth = random.randint(1, 10) - mlp_features = [block_size * random.randint(1, 10) for i in range(mlp_depth + 1)] + batch_parallelism = trial.suggest_int('batch_parallelism', 2, 10) + mlp_depth = 4 + mlp_features = [block_size * 4 for i in range(mlp_depth + 1)] params = { "seed": trial.number, @@ -76,8 +66,8 @@ def get_params(trial): "batch_parallelism": batch_parallelism, "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), - "batches": batch_parallelism * random.randint(1, 10), - "num_batches": random.randint(1, 10), + "batches": batch_parallelism * 4, + "num_batches": 10, } mlp = MLP(mlp_features) @@ -122,7 +112,7 @@ def getResources(trial): params, mg, mlp = get_params(trial) dump_param(trial.number, params) writeTrialNumber(trial.number) - # os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') + os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') bram_utils = get_bram_uram_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') clb_luts = extract_site_type_used_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') out = clb_luts['CLB LUTs*']['Util%'] + clb_luts['CLB Registers']['Util%'] + clb_luts['CARRY8']['Util%'] + bram_utils['bram'] + bram_utils['uram'] @@ -160,7 +150,7 @@ def main(): study.optimize( lambda trial: (getResources(trial), getAccuracy(trial)), - n_trials=1, + n_trials=100, timeout=60*60*24, n_jobs=1 ) @@ -170,4 +160,4 @@ def main(): print(f"Trial {trial.number}: {trial.values}") if __name__ == '__main__': - main() \ No newline at end of file + main() diff --git a/test/passes/graph/transforms/verilog/generate.tcl b/test/passes/graph/transforms/verilog/generate.tcl index 6f80fa788..c4b5181b5 100644 --- a/test/passes/graph/transforms/verilog/generate.tcl +++ b/test/passes/graph/transforms/verilog/generate.tcl @@ -3,7 +3,8 @@ create_project -in_memory -part xcku5p-ffvb676-2-e set_property board_part xilinx.com:kcu116:part0:1.5 [current_project] # /home/omar/.mase/top/hardware/rtl/ -add_files -fileset sources_1 /home/omar/.mase/top/hardware/rtl/ + +add_files -fileset sources_1 /home/oa321/.mase/top/hardware/rtl/ set_property top top [current_fileset] @@ -19,7 +20,7 @@ launch_runs synth_1 -jobs 12 wait_on_run synth_1 open_run synth_1 -report_utilization -file "/home/omar/Documents/year-4/adls/mase/resources/util_${trial_number}.txt" +report_utilization -file "/home/oa321/adls/mase/resources/util_${trial_number}.txt" # launch_runs synth_1 -jobs 12 # wait_on_run synth_1 @@ -27,4 +28,4 @@ report_utilization -file "/home/omar/Documents/year-4/adls/mase/resources/util_$ # open_run synth_1 -name synth_1 # report_utilization -name utilization_1 -# write_report -format csv -file "utilization_${trial_number}.xml" utilization_1 \ No newline at end of file +# write_report -format csv -file "utilization_${trial_number}.xml" utilization_1 From 21fed49bddba0f6a2152753006a1414ff691a65b Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Sun, 23 Mar 2025 16:33:52 +0000 Subject: [PATCH 6/9] Fixing mlp features --- .../graph/transforms/verilog/analyse_mxint_resources.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py index efa8a77cb..184ddf0c8 100644 --- a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py +++ b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py @@ -55,10 +55,10 @@ def write_value(trial_number, name, value, filename="output.json"): def get_params(trial): - block_size = trial.suggest_int('block_size', 2, 10) + block_size = 2**trial.suggest_int('block_size', 1, 8) batch_parallelism = trial.suggest_int('batch_parallelism', 2, 10) mlp_depth = 4 - mlp_features = [block_size * 4 for i in range(mlp_depth + 1)] + mlp_features = [256 for i in range(mlp_depth + 1)] params = { "seed": trial.number, From b00daff935bfbf1bd4f2095d9d93aa3aa9278b60 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Mon, 24 Mar 2025 14:13:36 +0000 Subject: [PATCH 7/9] Re-definint parameters --- .../transforms/verilog/analyse_mxint_resources.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py index 184ddf0c8..ef0157c25 100644 --- a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py +++ b/test/passes/graph/transforms/verilog/analyse_mxint_resources.py @@ -55,10 +55,10 @@ def write_value(trial_number, name, value, filename="output.json"): def get_params(trial): - block_size = 2**trial.suggest_int('block_size', 1, 8) - batch_parallelism = trial.suggest_int('batch_parallelism', 2, 10) - mlp_depth = 4 - mlp_features = [256 for i in range(mlp_depth + 1)] + block_size = 2**trial.suggest_int('block_size', 1, 5) + batch_parallelism = 2**trial.suggest_int('batch_parallelism', 1, 5) + mlp_depth = 3 + mlp_features = [128 for i in range(mlp_depth + 1)] params = { "seed": trial.number, @@ -66,7 +66,7 @@ def get_params(trial): "batch_parallelism": batch_parallelism, "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), - "batches": batch_parallelism * 4, + "batches": 128, "num_batches": 10, } From a492512ce95ff47be49edd4260917e72536691e1 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Tue, 25 Mar 2025 09:04:40 +0000 Subject: [PATCH 8/9] Clean up --- .../mxint_operators/rtl/mxint_accumulator.sv | 18 +- .../mxint_operators/rtl/mxint_cast.sv | 25 ++- .../passes/graph/transforms/verilog/config.py | 177 ------------------ .../graph/transforms/verilog/generate.tcl | 17 +- .../verilog/test_emit_verilog_mxint.py | 3 +- ...ces.py => test_synthesize_mxint_vivado.py} | 68 ++++--- 6 files changed, 72 insertions(+), 236 deletions(-) delete mode 100644 test/passes/graph/transforms/verilog/config.py rename test/passes/graph/transforms/verilog/{analyse_mxint_resources.py => test_synthesize_mxint_vivado.py} (70%) diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv index 1ee3569a8..c51f17a76 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_accumulator.sv @@ -20,17 +20,17 @@ module mxint_accumulator #( input logic rst, // Input Data - input logic [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], - input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, - input logic data_in_0_valid, - output logic data_in_0_ready, + input logic [DATA_IN_0_PRECISION_0-1:0] mdata_in_0 [BLOCK_SIZE - 1:0], + input logic [DATA_IN_0_PRECISION_1-1:0] edata_in_0, + input logic data_in_0_valid, + output logic data_in_0_ready, // Output Data - output logic [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], - output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, - output logic data_out_0_valid, - input logic data_out_0_ready, - output logic [ COUNTER_WIDTH:0] accum_count + output logic [DATA_OUT_0_PRECISION_0-1:0] mdata_out_0 [BLOCK_SIZE - 1:0], + output logic [DATA_OUT_0_PRECISION_1-1:0] edata_out_0, + output logic data_out_0_valid, + input logic data_out_0_ready, + output logic [ COUNTER_WIDTH:0] accum_count ); localparam RIGHT_PADDING = 2 ** DATA_IN_0_PRECISION_1; diff --git a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv index 4bdbc7523..647479928 100644 --- a/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv +++ b/src/mase_components/linear_layers/mxint_operators/rtl/mxint_cast.sv @@ -18,15 +18,15 @@ module mxint_cast #( // Input Data input logic [IN_MAN_WIDTH-1:0] mdata_in [BLOCK_SIZE-1:0], - input logic [IN_EXP_WIDTH-1:0] edata_in, - input logic data_in_valid, - output logic data_in_ready, + input logic [IN_EXP_WIDTH-1:0] edata_in, + input logic data_in_valid, + output logic data_in_ready, // Output Data output logic [OUT_MAN_WIDTH-1:0] mdata_out [BLOCK_SIZE-1:0], - output logic [OUT_EXP_WIDTH-1:0] edata_out, - output logic data_out_valid, - input logic data_out_ready + output logic [OUT_EXP_WIDTH-1:0] edata_out, + output logic data_out_valid, + input logic data_out_ready ); // ============================= @@ -104,8 +104,7 @@ module mxint_cast #( if (FIFO_DEPTH == 0) begin always_comb begin - for (int i = 0; i < BLOCK_SIZE; i++) - begin + for (int i = 0; i < BLOCK_SIZE; i++) begin mbuffer_data_for_out[i] = $signed(mdata_in[i]); end ebuffer_data_for_out = edata_in; @@ -133,12 +132,10 @@ module mxint_cast #( .data_out_ready(buffer_data_for_out_ready) ); - always_comb - begin - for (int i = 0; i < BLOCK_SIZE; i++) - begin - mbuffer_data_for_out[i] = $signed(fifo_out[i]); - end + always_comb begin + for (int i = 0; i < BLOCK_SIZE; i++) begin + mbuffer_data_for_out[i] = $signed(fifo_out[i]); + end end end diff --git a/test/passes/graph/transforms/verilog/config.py b/test/passes/graph/transforms/verilog/config.py deleted file mode 100644 index b53855dbc..000000000 --- a/test/passes/graph/transforms/verilog/config.py +++ /dev/null @@ -1,177 +0,0 @@ -import os, re, random -import optuna -from optuna import study -from optuna.samplers import TPESampler, GridSampler -import json -from chop.tools.logger import set_logging_verbosity -from chop.tools import get_logger -from test_emit_verilog_mxint import MLP, shared_emit_verilog_mxint -import os, sys, logging, traceback, pdb -import pytest -import toml -import torch -import torch.nn as nn -import chop as chop -import chop.passes as passes -from pathlib import Path -from chop.actions import simulate -from chop.passes.graph.analysis.report.report_node import report_node_type_analysis_pass -from chop.tools.logger import set_logging_verbosity -from chop.tools import get_logger - -config_file = "config.tcl" - -set_logging_verbosity("debug") - -logger = get_logger(__name__) - -batch_size = 6 -block_size = 4 - -search_space = { - "IN_FEATURES" : [block_size * i for i in range(1, 4)], - "OUT_FEATURES" : [block_size * i for i in range(1, 4)], - "m_width" : [i for i in range(3, 6)], - "e_width" : [i for i in range(3, 6)] -} - -def dump_param(trial_number, quan_args, filename="output.json"): - try: - with open(filename, "r") as file: - data = json.load(file) - except (FileNotFoundError, json.JSONDecodeError): - data = {} - - data[str(trial_number)] = quan_args - - with open(filename, "w") as file: - json.dump(data, file, indent=4) - - -def write_value(trial_number, name, value, filename="output.json"): - try: - with open(filename, "r") as file: - data = json.load(file) - except (FileNotFoundError, json.JSONDecodeError): - data = {} - - if str(trial_number) in data.keys(): - data[str(trial_number)][name] = value - else: - data[str(trial_number)] = {name : value} - - with open(filename, "w") as file: - json.dump(data, file, indent=4) - -def get_params(trial): - - block_size = trial.suggest_int('block_size', 2, 10) - batch_parallelism = random.randint(2, 10) - mlp_depth = random.randint(1, 10) - mlp_features = [block_size * random.randint(1, 10) for i in range(mlp_depth + 1)] - - params = { - "seed": trial.number, - "block_size": block_size, - "batch_parallelism": batch_parallelism, - "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), - "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), - "batches": batch_parallelism * random.randint(1, 10), - "num_batches": random.randint(1, 10), - } - - mlp = MLP(mlp_features) - input_shape = (mlp_features[0],) - - dump_param(trial.number, trial.params) - - logger.info( - f"{block_size=}, {batch_parallelism=}, {params['e_width']=}, {params['m_width']=}, {params['batches']=}" - ) - - mg, mlp = shared_emit_verilog_mxint(mlp, input_shape, params, simulate=False) - - return params, mg, mlp - -def writeTrialNumber(trial_number): - with open(config_file, "w") as f: - f.write(f'set trial_number {trial_number}\n') - -def extract_site_type_used_util(filename): - site_data = {} - with open(filename, 'r') as file: - lines = file.readlines() - - pattern = re.compile(r'\|\s*([^|]+?)\s*\|\s*(\d+)\s*\|.*?\|\s*(\d+\.\d+)\s*\|') - - for line in lines: - match = pattern.match(line) - if match: - site_type = match.group(1).strip() - used = int(match.group(2).strip()) - util = float(match.group(3).strip()) - site_data[site_type] = {'Used': used, 'Util%': util} - - return site_data - -def get_bram_uram_util(filename): - site_data = extract_site_type_used_util(filename) - bram_util = site_data.get("Block RAM Tile", {}).get("Util%", 0.0) - uram_util = site_data.get("URAM", {}).get("Util%", 0.0) - return {"bram": bram_util, "uram": uram_util} - -def getResources(trial): - _, mg, mlp = get_params(trial) - writeTrialNumber(trial.number) - # os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') - bram_utils = get_bram_uram_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') - clb_luts = extract_site_type_used_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') - out = clb_luts['CLB LUTs*']['Util%'] + clb_luts['CLB Registers']['Util%'] + clb_luts['CARRY8']['Util%'] + bram_utils['bram'] + bram_utils['uram'] - write_value(trial.number, 'resource_score', out) - return out - -def getAccuracy(trial): - params, mg, mlp = get_params(trial) - quantized = mg.model - - criterion = nn.MSELoss() - total_mse = 0.0 - - for _ in range(100): - x = torch.randn(params['batches'], mg.model[0].in_features) # Generate random input - y1 = quantized(x) - y2 = mlp(x) - mse = criterion(y1, y2) - total_mse += mse.item() - - avg_mse = total_mse / 100 - - write_value(trial.number, 'avg_mse', avg_mse) - return avg_mse - - -def main(): - sampler = TPESampler() - - study = optuna.create_study( - directions=["minimize", "minimize"], - study_name="resource_accuracy_optimiser", - sampler=sampler - ) - - study.optimize( - lambda trial: (getResources(trial), getAccuracy(trial)), - n_trials=1, - timeout=60*60*24, - n_jobs=1 - ) - - print("Best trials:") - for trial in study.best_trials: - print(f"Trial {trial.number}: {trial.values}") - -if __name__ == '__main__': - write_value(0, "avg_msg", 0.1234) - write_value(0, "new_metric", 0.5678) - write_value(1, "avg_msg", 0.4321) - # main() diff --git a/test/passes/graph/transforms/verilog/generate.tcl b/test/passes/graph/transforms/verilog/generate.tcl index c4b5181b5..6315fe3e7 100644 --- a/test/passes/graph/transforms/verilog/generate.tcl +++ b/test/passes/graph/transforms/verilog/generate.tcl @@ -1,15 +1,12 @@ +source config.tcl create_project -in_memory -part xcku5p-ffvb676-2-e set_property board_part xilinx.com:kcu116:part0:1.5 [current_project] -# /home/omar/.mase/top/hardware/rtl/ - -add_files -fileset sources_1 /home/oa321/.mase/top/hardware/rtl/ +add_files -fileset sources_1 "$top_dir/hardware/rtl/" set_property top top [current_fileset] -source config.tcl - puts "Trial: ${trial_number}" eval "synth_design -mode out_of_context -top top -part xcku5p-ffvb676-2-e" @@ -20,12 +17,4 @@ launch_runs synth_1 -jobs 12 wait_on_run synth_1 open_run synth_1 -report_utilization -file "/home/oa321/adls/mase/resources/util_${trial_number}.txt" - -# launch_runs synth_1 -jobs 12 -# wait_on_run synth_1 - -# open_run synth_1 -name synth_1 -# report_utilization -name utilization_1 - -# write_report -format csv -file "utilization_${trial_number}.xml" utilization_1 +report_utilization -file "$mase_dir/resources/util_${trial_number}.txt" diff --git a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py index 74e3ef59c..0a5b691fd 100644 --- a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py +++ b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py @@ -177,7 +177,7 @@ def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = mg, _ = passes.emit_bram_transform_pass(mg) mg, _ = passes.emit_internal_rtl_transform_pass(mg) - if (simulate): + if simulate: mg, _ = passes.emit_cocotb_transform_pass( mg, pass_args={ @@ -200,6 +200,7 @@ def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = return model, mg.model + if __name__ == "__main__": seed = os.getenv("COCOTB_SEED") if seed is None: diff --git a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py b/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py similarity index 70% rename from test/passes/graph/transforms/verilog/analyse_mxint_resources.py rename to test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py index ef0157c25..c6e200b55 100644 --- a/test/passes/graph/transforms/verilog/analyse_mxint_resources.py +++ b/test/passes/graph/transforms/verilog/test_synthesize_mxint_vivado.py @@ -25,6 +25,7 @@ logger = get_logger(__name__) + def dump_param(trial_number, quan_args, filename="output.json"): try: with open(filename, "r") as file: @@ -48,15 +49,16 @@ def write_value(trial_number, name, value, filename="output.json"): if str(trial_number) in data.keys(): data[str(trial_number)][name] = value else: - data[str(trial_number)] = {name : value} + data[str(trial_number)] = {name: value} with open(filename, "w") as file: json.dump(data, file, indent=4) + def get_params(trial): - block_size = 2**trial.suggest_int('block_size', 1, 5) - batch_parallelism = 2**trial.suggest_int('batch_parallelism', 1, 5) + block_size = 2 ** trial.suggest_int("block_size", 1, 4) + batch_parallelism = 2 ** trial.suggest_int("batch_parallelism", 1, 4) mlp_depth = 3 mlp_features = [128 for i in range(mlp_depth + 1)] @@ -64,8 +66,8 @@ def get_params(trial): "seed": trial.number, "block_size": block_size, "batch_parallelism": batch_parallelism, - "m_width": (m_width := trial.suggest_int('m_width', 4, 10)), - "e_width": trial.suggest_int('e_width', 3, min(m_width - 1, 10)), + "m_width": (m_width := trial.suggest_int("m_width", 4, 10)), + "e_width": trial.suggest_int("e_width", 3, min(m_width - 1, 10)), "batches": 128, "num_batches": 10, } @@ -81,16 +83,20 @@ def get_params(trial): return params, mg, mlp + def writeTrialNumber(trial_number): with open(config_file, "w") as f: - f.write(f'set trial_number {trial_number}\n') + f.write(f"set trial_number {trial_number}\n") + f.write(f"set top_dir {Path.home()}/.mase/top/\n") + f.write(f"set mase_dir {Path.cwd()}/") + def extract_site_type_used_util(filename): site_data = {} - with open(filename, 'r') as file: + with open(filename, "r") as file: lines = file.readlines() - pattern = re.compile(r'\|\s*([^|]+?)\s*\|\s*(\d+)\s*\|.*?\|\s*(\d+\.\d+)\s*\|') + pattern = re.compile(r"\|\s*([^|]+?)\s*\|\s*(\d+)\s*\|.*?\|\s*(\d+\.\d+)\s*\|") for line in lines: match = pattern.match(line) @@ -98,27 +104,40 @@ def extract_site_type_used_util(filename): site_type = match.group(1).strip() used = int(match.group(2).strip()) util = float(match.group(3).strip()) - site_data[site_type] = {'Used': used, 'Util%': util} + site_data[site_type] = {"Used": used, "Util%": util} return site_data + def get_bram_uram_util(filename): site_data = extract_site_type_used_util(filename) bram_util = site_data.get("Block RAM Tile", {}).get("Util%", 0.0) uram_util = site_data.get("URAM", {}).get("Util%", 0.0) return {"bram": bram_util, "uram": uram_util} + def getResources(trial): params, mg, mlp = get_params(trial) dump_param(trial.number, params) writeTrialNumber(trial.number) - os.system(f'vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl') - bram_utils = get_bram_uram_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') - clb_luts = extract_site_type_used_util(f'{Path.cwd()}/resources/util_{trial.number}.txt') - out = clb_luts['CLB LUTs*']['Util%'] + clb_luts['CLB Registers']['Util%'] + clb_luts['CARRY8']['Util%'] + bram_utils['bram'] + bram_utils['uram'] - write_value(trial.number, 'resource_score', out) + os.system( + f"vivado -mode batch -nolog -nojou -source {Path.cwd()}/test/passes/graph/transforms/verilog/generate.tcl" + ) + bram_utils = get_bram_uram_util(f"{Path.cwd()}/resources/util_{trial.number}.txt") + clb_luts = extract_site_type_used_util( + f"{Path.cwd()}/resources/util_{trial.number}.txt" + ) + out = ( + clb_luts["CLB LUTs*"]["Util%"] + + clb_luts["CLB Registers"]["Util%"] + + clb_luts["CARRY8"]["Util%"] + + bram_utils["bram"] + + bram_utils["uram"] + ) + write_value(trial.number, "resource_score", out) return out + def getAccuracy(trial): params, mg, mlp = get_params(trial) quantized = mg.model @@ -127,7 +146,7 @@ def getAccuracy(trial): total_mse = 0.0 for _ in range(100): - x = torch.randn(params['batches'], mg.model[0].in_features) # Generate random input + x = torch.randn(params["batches"], mg.model[0].in_features) y1 = quantized(x) y2 = mlp(x) mse = criterion(y1, y2) @@ -135,7 +154,7 @@ def getAccuracy(trial): avg_mse = total_mse / 100 - write_value(trial.number, 'avg_mse', avg_mse) + write_value(trial.number, "avg_mse", avg_mse) return avg_mse @@ -145,19 +164,26 @@ def main(): study = optuna.create_study( directions=["minimize", "minimize"], study_name="resource_accuracy_optimiser", - sampler=sampler + sampler=sampler, ) study.optimize( lambda trial: (getResources(trial), getAccuracy(trial)), - n_trials=100, - timeout=60*60*24, - n_jobs=1 + n_trials=10, + timeout=60 * 60 * 24, + n_jobs=1, ) print("Best trials:") for trial in study.best_trials: print(f"Trial {trial.number}: {trial.values}") -if __name__ == '__main__': + +if __name__ == "__main__": + + try: + os.mkdir(f"{Path.cwd()}/resources/") + except: + pass + main() From 325b901131622e163b0940cc86f19bd36b36da57 Mon Sep 17 00:00:00 2001 From: Omar Alkhatib Date: Tue, 25 Mar 2025 09:28:33 +0000 Subject: [PATCH 9/9] Fixed test_emit_verilog_mxint.py --- .../graph/transforms/verilog/test_emit_verilog_mxint.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py index 0a5b691fd..3e6815e40 100644 --- a/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py +++ b/test/passes/graph/transforms/verilog/test_emit_verilog_mxint.py @@ -107,7 +107,7 @@ def forward(self, x): shared_emit_verilog_mxint(linear, input_shape, params) -def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = True): +def shared_emit_verilog_mxint(model, input_shape, params: dict, sim: bool = True): # Set seeds torch.manual_seed(params["seed"]) random.seed(params["seed"]) @@ -177,7 +177,7 @@ def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = mg, _ = passes.emit_bram_transform_pass(mg) mg, _ = passes.emit_internal_rtl_transform_pass(mg) - if simulate: + if sim: mg, _ = passes.emit_cocotb_transform_pass( mg, pass_args={ @@ -209,6 +209,6 @@ def shared_emit_verilog_mxint(model, input_shape, params: dict, simulate: bool = else: seed = int(seed) logger.info(f"Using provided {seed=}") - test_emit_verilog_mxint_linear(seed) - # test_emit_verilog_mxint_mlp(seed) + # test_emit_verilog_mxint_linear(seed) + test_emit_verilog_mxint_mlp(seed) logger.info(f"{seed=}")