From 280f93265528fb4f589a4eb7114d96693a72c6ee Mon Sep 17 00:00:00 2001
From: shengxiansong <353841956@qq.com>
Date: Tue, 29 Jul 2025 07:34:07 +0000
Subject: [PATCH] simulate axilite slave is ok when commit this lines; and rst
 is low active, use rstn may be better

---
 sv/axi4lite_drv.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sv/axi4lite_drv.sv b/sv/axi4lite_drv.sv
index a55b50f..d574ab7 100644
--- a/sv/axi4lite_drv.sv
+++ b/sv/axi4lite_drv.sv
@@ -125,7 +125,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
       if (to_ctr == 31) begin
         `uvm_error("uvm_axi4lite_master_driver","AWVALID timeout");
       end       
-      @(posedge vif.clk);
+      //@(posedge vif.clk);
       vif.AWADDR  <= 32'h0;
       vif.AWPROT  <= 3'h0;
       vif.AWVALID <= 1'b0;     
@@ -144,7 +144,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
       if (to_ctr == 31) begin
         `uvm_error("uvm_axi4lite_master_driver","ARVALID timeout");
       end       
-      @(posedge vif.clk);
+      //@(posedge vif.clk);
       vif.ARADDR  <= 32'h0;
       vif.ARPROT  <= 3'h0;
       vif.ARVALID <= 1'b0;      
@@ -158,7 +158,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
       vif.WDATA  <= data;
       vif.WSTRB  <= 4'hf;
       vif.WVALID <= 1'b1;
-      @(posedge vif.clk);
+      //@(posedge vif.clk);
       for(to_ctr = 0; to_ctr <= 31; to_ctr ++) begin
          @(posedge vif.clk);
          if (vif.WREADY) break;
@@ -166,7 +166,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
       if (to_ctr == 31) begin
         `uvm_error("uvm_axi4lite_master_driver","AWVALID timeout");
       end
-      @(posedge vif.clk);
+      //@(posedge vif.clk);
       vif.WDATA  <= 32'h0;
       vif.WSTRB  <= 4'h0;
       vif.WVALID <= 1'b0;