About Using HLS Cache

[taoistmiao]

Hi,

I'm trying to bring up the simulation with HLS cache while the make sim command failed at the end reporting the bit width mismatches between Verilog and VHDL sources. Am I missing any steps here?

Looking further into files for inval_data_addr for example, I notices that the inval address bit width is declared as addr_t which is ADDR_BITS-1 in SystemVerilog caches as shown in esp/rtl/caches/esp-caches/common/defs/cache_types.svh, while the bit width in SystemC caches is declared as linr_addr_t which is ADDR_BITS-OFFSET_BITS as shown in esp/rtl/caches/esp-caches/systemc/common/caches/cache_consts.hpp

Thanks!

The errors reported:

# ** Error (suppressible): (vsim-3058) The width (28) of Verilog port 'l2_inval_data_addr' does not match the array length (32) of its VHDL connection.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(0)/cpu_tile/tile_cpu_i/tile_cpu_1/with_cache_coherence/l2_wrapper_1/l2_gen/l2_cache_i/hls_gen/basic_512sets_4ways_2x64line_32addr_llsc_le_gen/l2_basic_512sets_4ways_2x64line_32addr_llsc_le_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/l2/l2_basic_512sets_4ways_2x64line_32addr_llsc_le/l2_basic_512sets_4ways_2x64line_32addr_llsc_le.v
# ** Error (suppressible): (vsim-3058) The width (28) of Verilog port 'l2_inval_data_addr' does not match the array length (32) of its VHDL connection.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(1)/cpu_tile/tile_cpu_i/tile_cpu_1/with_cache_coherence/l2_wrapper_1/l2_gen/l2_cache_i/hls_gen/basic_512sets_4ways_2x64line_32addr_llsc_le_gen/l2_basic_512sets_4ways_2x64line_32addr_llsc_le_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/l2/l2_basic_512sets_4ways_2x64line_32addr_llsc_le/l2_basic_512sets_4ways_2x64line_32addr_llsc_le.v
# ** Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'llc_dma_req_in_data_word_offset'.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(2)/mem_tile/tile_mem_i/tile_mem_1/with_cache_coherence/llc_wrapper_1/llc_gen/llc_cache_i/hls_gen/basic_1024sets_16ways_2x64line_32addr_gen/llc_basic_1024sets_16ways_2x64line_32addr_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/llc/llc_basic_1024sets_16ways_2x64line_32addr/llc_basic_1024sets_16ways_2x64line_32addr.v
# ** Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'llc_dma_req_in_data_valid_words'.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(2)/mem_tile/tile_mem_i/tile_mem_1/with_cache_coherence/llc_wrapper_1/llc_gen/llc_cache_i/hls_gen/basic_1024sets_16ways_2x64line_32addr_gen/llc_basic_1024sets_16ways_2x64line_32addr_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/llc/llc_basic_1024sets_16ways_2x64line_32addr/llc_basic_1024sets_16ways_2x64line_32addr.v
# ** Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'llc_dma_rsp_out_data_word_offset'.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(2)/mem_tile/tile_mem_i/tile_mem_1/with_cache_coherence/llc_wrapper_1/llc_gen/llc_cache_i/hls_gen/basic_1024sets_16ways_2x64line_32addr_gen/llc_basic_1024sets_16ways_2x64line_32addr_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/llc/llc_basic_1024sets_16ways_2x64line_32addr/llc_basic_1024sets_16ways_2x64line_32addr.v
# ** Error (suppressible): (vsim-3058) The width (28) of Verilog port 'l2_inval_data_addr' does not match the array length (32) of its VHDL connection.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(4)/cpu_tile/tile_cpu_i/tile_cpu_1/with_cache_coherence/l2_wrapper_1/l2_gen/l2_cache_i/hls_gen/basic_512sets_4ways_2x64line_32addr_llsc_le_gen/l2_basic_512sets_4ways_2x64line_32addr_llsc_le_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/l2/l2_basic_512sets_4ways_2x64line_32addr_llsc_le/l2_basic_512sets_4ways_2x64line_32addr_llsc_le.v
# ** Error (suppressible): (vsim-3058) The width (28) of Verilog port 'l2_inval_data_addr' does not match the array length (32) of its VHDL connection.
#    Time: 0 fs  Iteration: 0  Instance: /testbench/top_1/esp_1/tiles_gen(5)/cpu_tile/tile_cpu_i/tile_cpu_1/with_cache_coherence/l2_wrapper_1/l2_gen/l2_cache_i/hls_gen/basic_512sets_4ways_2x64line_32addr_llsc_le_gen/l2_basic_512sets_4ways_2x64line_32addr_llsc_le_i File: /home/v69610/mydata/esp/tech/virtex7/sccs/l2/l2_basic_512sets_4ways_2x64line_32addr_llsc_le/l2_basic_512sets_4ways_2x64line_32addr_llsc_le.v
# Error loading design
Error loading design
# End time: 14:19:14 on Jun 27,2025, Elapsed time: 0:00:04
# Errors: 7, Warnings: 0, Suppressed Warnings: 1
make: *** [/home/v69610/mydata/esp/utils/make/modelsim.mk:125: sim] Error 12