FPGA Design Filesystem Read Speed

[dib5230]

I have several questions related to the filesystem read speed of an ESP FPGA design. I am targetting a VCU118. Based on my testing, the filesystem read speed of an ESP design is roughly an order of magnitude slower than the read speed of a conventional computer:

System	Read Speed
Ubuntu 22.04 VM:	~140 MB/s
ESP design with 1 Ariane RISC-V CPU	~10 MB/s

1. Is the read speed of my ESP design consistent with the expected read speed of an ESP design?

The filesystem read speed of an ESP design with a single Ariane RISC-V core and caches disabled appears to be roughly 1.5x to 2x faster than the read speed of a multi-core design, with two Ariane RISC-V cores. However, the read speed of a single-core design with caches enabled (required for a multi-core design) appears to be similar to the read speed of the multi-core design, though the read speed of the single-core design appears to still be slightly faster.

2. Is the read speed expected to change depending on whether caches are enabled or disabled?

3. Do you have any suggestions for improving the read speed of a multi-core design, such that its read speed more closely matches the read speed of a single-core design with caches disabled? Would using a custom cache configuration help?

I believe I am using the default cache configuration when caches are enabled. For my ESP design read tests, I am reading in a 50 MB file of random data (created with /dev/urandom). As an additional note, memory mapping a file, and then copying data from the memory mapped file to an input buffer, appears to be faster than reading from a file.