Failure when linking testbench

[medbzkst]

The tool consistently fails when it arrives at the "Linking testbench" step. It always takes the same time, whatever is happening in the background (~ 4.59s), which suggests that it is not waiting for something to happen when Vitis HLS is compiling.

I am running on Vitis HLS 2022.1.

[AdrianLiu00]

Same problem. Is there any insight provided about how it works about linking the testbench?

[ArkaneMoose]

Apologies for the delayed response. Hovering over the error text in the message error in X.XXs should give the full error message.

You can also try running this Python script from the same conda environment where you installed LightningSim; it should hopefully provide more output when it crashes. (Run it as ./cli.py path/to/solution1.)

For reference, the actual code that handles this step can be found here:

LightningSim/backend/lightningsim/runner.py

Lines 479 to 536 in d3fb26b

	with self.steps[RunnerStep.LINKING_TESTBENCH]:
	output_path = output_dir / f"testbench_{kernel}"
	compile_mapper = await compile_mapper
	self.add_completed_process(compile_mapper)
	compile_mapper.check_returncode()
	compile_project_files = [
	compilation_process
	for compilation_processes in await compile_project_files
	for compilation_process in compilation_processes
	]
	self.add_completed_processes(compile_project_files)
	for compilation in compile_project_files:
	compilation.check_returncode()
	link_objects = " ".join(
	str(path).replace(" ", "\\ ")
	for path in (*project_object_paths, object_path, mapper_path)
	)
	extra_ld_flags = shlex.join(
	str(flag)
	for flag in (
	*ldflags,
	"-L",
	TEMPLATE_DIR,
	"-llightningsimrt",
	"-g",
	"-O3",
	"-flto",
	)
	)
	link_testbench = await run(
	[
	"make",
	"-B",
	"-f",
	xilinx_hls / "include/Makefile.sysc.rules",
	f"AUTOPILOT_ROOT={xilinx_hls}",
	f'AUTOPILOT_TOOL={xilinx_hls / "lnx64/tools"}',
	f"AUTOPILOT_MACH=lnx64",
	f"CXX={CXX}",
	f"TARGET={output_path}",
	f"ObjDir={tempdir_str}",
	f"OBJECTS={link_objects}",
	f"ExtraLDFlags={extra_ld_flags}",
	"__SIM_MATHHLS__=1",
	"__SIM_FPO__=1",
	"__SIM_FFT__=1",
	"__SIM_FIR__=1",
	"__SIM_DDS__=1",
	output_path,
	],
	cwd=self.solution.path.parent.parent,
	)
	self.add_completed_process(link_testbench)
	link_testbench.check_returncode()
	for file in project_binary_files:
	shutil.copy2(file.path, output_dir)
	for directory in project_directories:
	os.symlink(directory.path.absolute(), output_dir / directory.path.name)

[AdrianLiu00]

Thanks for your response. I tried the cli python script and the key traceback of the link error went as below.

> .../x86_64-conda-linux-gnu/bin/ld: /opt/xilinx/2022.1/Vitis_HLS/2022.1/lnx64/tools/systemc/lib/libsystemc.a(sc_main_main.o): in function `sc_elab_and_sim':
> sc_main_main.cpp:(.text+0xd8): undefined reference to `sc_main'
> collect2: error: ld returned 1 exit status
> make: *** [/opt/xilinx/2022.1/Vitis_HLS/2022.1/include/Makefile.sysc.rules:393: /tmp/lightningsim.dc3um42t/testbench_top] Error 1

I guess this issue may come form the mismatch of xilinx vitis version?

[ArkaneMoose]

Yes, this looks like it's due to a change in 2022.1. I had updated this step to use the Xilinx-provided Makefile in the hopes that the linking process would now be version-agnostic, but apparently no such luck.

I'll have to look at what changed in the linking process between 2021.1 and 2022.1.