Support Avoid Re-synthesizing Already-Completed Configurations #73
Description
When running runtime intensive Vitis HLS flows (e.g., csynth, impl) or any flow across multiple configurations or datasets, there is currently no officially supported way to avoid redundant flow execution, e.g. synthesis and implementation of designs, that have already been processed in previous runs.
Users must currently rely on ad-hoc scripts or manual checking for output files, which is error-prone and inefficient, especially when dealing with partially completed or failed runs.
This issue proposes to add support for a structured “design flow log” for each configuration, recording when flows start, complete, fail, or time out. On each run, check this log to skip completed flows, rerun failed or incomplete ones, and only process new configurations. If the design/config doesn’t exist on disk or in the log, run it as normal. Merging multiple executions for the same dataset should be seamless.
Unifying the current runtime logging and sentinel-file approach into this “design flow log” idea makes the most sense.