diff --git a/README.md b/README.md index 79d4d84..378b4af 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ This repository contains the example files for the overlay tutorial documentation and notebook for the PYNQ-Z1 board. To rebuild the bitstreams: - * Open Vivado 2018.3 + * Open Vivado 2020.2 * In the TCL consolde run `cd <>` * and `source build_all.tcl` diff --git a/build_all.tcl b/build_all.tcl index a016c08..c7d9763 100644 --- a/build_all.tcl +++ b/build_all.tcl @@ -1,23 +1,23 @@ cd ip -foreach script [glob */script.tcl] { exec vivado_hls -f $script } +foreach script [glob */script.tcl] { exec vitis_hls -f $script } cd ../overlays source tutorial_1.tcl add_files -norecurse [make_wrapper -files [get_files "[current_bd_design].bd"] -top] update_compile_order -fileset sources_1 set_property top tutorial_1_wrapper [current_fileset] -launch_runs impl_1 -to_step write_bitstream +launch_runs impl_1 -to_step write_bitstream -jobs 4 wait_on_run impl_1 file copy -force tutorial_1/tutorial_1.runs/impl_1/tutorial_1_wrapper.bit tutorial_1.bit -file copy -force tutorial_1/tutorial_1.srcs/sources_1/bd/tutorial_1/hw_handoff/tutorial_1.hwh tutorial_1.hwh +file copy -force tutorial_1/tutorial_1.gen/sources_1/bd/tutorial_1/hw_handoff/tutorial_1.hwh tutorial_1.hwh close_project source tutorial_2.tcl add_files -norecurse [make_wrapper -files [get_files "[current_bd_design].bd"] -top] update_compile_order -fileset sources_1 set_property top tutorial_2_wrapper [current_fileset] -launch_runs impl_1 -to_step write_bitstream +launch_runs impl_1 -to_step write_bitstream -jobs 4 wait_on_run impl_1 file copy -force tutorial_2/tutorial_2.runs/impl_1/tutorial_2_wrapper.bit tutorial_2.bit -file copy -force tutorial_2/tutorial_2.srcs/sources_1/bd/tutorial_2/hw_handoff/tutorial_2.hwh tutorial_2.hwh +file copy -force tutorial_2/tutorial_2.gen/sources_1/bd/tutorial_2/hw_handoff/tutorial_2.hwh tutorial_2.hwh close_project diff --git a/ip/mult_constant/mult_constant.cpp b/ip/mult_constant/mult_constant.cpp index 523cf12..620a68a 100644 --- a/ip/mult_constant/mult_constant.cpp +++ b/ip/mult_constant/mult_constant.cpp @@ -1,19 +1,25 @@ #include "ap_axi_sdata.h" -#include "ap_int.h" +#include "hls_stream.h" -typedef ap_axiu<32,1,1,1> stream_type; +typedef ap_axis<32,1,1,1> stream_type; -void mult_constant(stream_type* in_data, stream_type* out_data, ap_int<32> constant) { -#pragma HLS INTERFACE s_axilite register port=constant +void mult_constant(hls::stream< stream_type > &in_data, hls::stream< stream_type > &out_data, ap_int<32> constant_r ){ +#pragma HLS INTERFACE s_axilite register port=constant_r #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE axis port=in_data #pragma HLS INTERFACE axis port=out_data - out_data->data = in_data->data * constant; - out_data->dest = in_data->dest; - out_data->id = in_data->id; - out_data->keep = in_data->keep; - out_data->last = in_data->last; - out_data->strb = in_data->strb; - out_data->user = in_data->user; + + stream_type temp; + + while(1) + { + in_data.read(temp); + temp.data = temp.data.to_int() * constant_r; + out_data.write(temp); + if(temp.last) + { + break; + } + } } diff --git a/ip/mult_constant/script.tcl b/ip/mult_constant/script.tcl index cb7ae99..7d3ed9e 100644 --- a/ip/mult_constant/script.tcl +++ b/ip/mult_constant/script.tcl @@ -1,8 +1,8 @@ open_project mult_constant set_top mult_constant add_files mult_constant/mult_constant.cpp -open_solution "solution1" -set_part {xc7z020clg484-1} -tool vivado +open_solution "solution1" -flow_target vivado +set_part {xc7z020clg400-1} create_clock -period 10 -name default #source "./mult_constant/solution1/directives.tcl" #csim_design diff --git a/ip/scalar_add/script.tcl b/ip/scalar_add/script.tcl index b6e9c26..2ce7203 100644 --- a/ip/scalar_add/script.tcl +++ b/ip/scalar_add/script.tcl @@ -1,8 +1,8 @@ open_project scalar_add set_top add add_files scalar_add/add.cpp -open_solution "solution1" -set_part {xc7z020clg484-1} -tool vivado +open_solution "solution1" -flow_target vivado +set_part {xc7z020clg400-1} create_clock -period 10 -name default #source "./scalar_add/solution1/directives.tcl" #csim_design diff --git a/overlays/tutorial_1.bit b/overlays/tutorial_1.bit index 15dd9bb..d3f9a7a 100644 Binary files a/overlays/tutorial_1.bit and b/overlays/tutorial_1.bit differ diff --git a/overlays/tutorial_1.hwh b/overlays/tutorial_1.hwh index 96d48e0..735a849 100644 --- a/overlays/tutorial_1.hwh +++ b/overlays/tutorial_1.hwh @@ -1,5 +1,5 @@  - + @@ -29,7 +29,7 @@ - + @@ -1309,7 +1309,7 @@ - + @@ -1547,13 +1547,13 @@ - + - + @@ -2073,7 +2073,7 @@ - + @@ -2086,53 +2086,53 @@ - + - + - + - + - + - + - + - + - + - + @@ -2145,33 +2145,33 @@ - + - + - + - + - + - + @@ -2309,23 +2309,23 @@ - + - - + + - - - - + + + + - + @@ -2335,10 +2335,10 @@ - + - + @@ -2349,7 +2349,7 @@ - + @@ -2369,7 +2369,7 @@ - + @@ -2389,7 +2389,7 @@ - + @@ -2434,8 +2434,8 @@ - - + + @@ -2443,91 +2443,91 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2537,19 +2537,18 @@ - + - + - @@ -2578,23 +2577,23 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + diff --git a/overlays/tutorial_1.tcl b/overlays/tutorial_1.tcl index 2d99b44..0ce484f 100644 --- a/overlays/tutorial_1.tcl +++ b/overlays/tutorial_1.tcl @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2018.3 +set scripts_vivado_version 2020.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -72,10 +72,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -96,19 +96,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -125,7 +125,7 @@ xilinx.com:hls:add:1.0\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -135,14 +135,14 @@ xilinx.com:hls:add:1.0\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -166,14 +166,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -186,8 +186,10 @@ proc create_root_design { parentCell } { # Create interface ports set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + # Create ports # Create instance: processing_system7_0, and set properties @@ -226,11 +228,13 @@ proc create_root_design { parentCell } { CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ @@ -401,11 +405,15 @@ proc create_root_design { parentCell } { CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ + CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ CONFIG.PCW_I2C_RESET_ENABLE {1} \ CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ @@ -633,7 +641,34 @@ proc create_root_design { parentCell } { CONFIG.PCW_MIO_9_PULLUP {enabled} \ CONFIG.PCW_MIO_9_SLEW {slow} \ CONFIG.PCW_MIO_PRIMITIVE {54} \ - CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS { \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#SD 0#USB \ + 0#SD 0#USB \ + 0#SD 0#USB \ + 0#UART 0#Enet \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART \ + Flash#GPIO#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + GPIO#Quad SPI \ + Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet \ + } \ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ @@ -784,6 +819,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ @@ -808,6 +844,11 @@ proc create_root_design { parentCell } { CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ + CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \ CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ @@ -936,6 +977,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ CONFIG.PCW_USB_RESET_ENABLE {1} \ CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ @@ -992,7 +1034,7 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalar_add/s_axi_AXILiteS] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalar_add/s_axi_control] # Create port connections connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins scalar_add/ap_clk] @@ -1001,7 +1043,7 @@ proc create_root_design { parentCell } { connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins scalar_add/ap_rst_n] # Create address segments - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalar_add/s_axi_AXILiteS/Reg] SEG_add_0_Reg + assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalar_add/s_axi_control/Reg] -force # Restore current instance diff --git a/overlays/tutorial_2.bit b/overlays/tutorial_2.bit index 605503a..e8a324b 100644 Binary files a/overlays/tutorial_2.bit and b/overlays/tutorial_2.bit differ diff --git a/overlays/tutorial_2.hwh b/overlays/tutorial_2.hwh index 0c29e7e..df10861 100644 --- a/overlays/tutorial_2.hwh +++ b/overlays/tutorial_2.hwh @@ -1,5 +1,5 @@  - + @@ -29,7 +29,7 @@ - + @@ -159,7 +159,7 @@ - + @@ -1026,21 +1026,21 @@ - + - + - - + + - - + + @@ -1055,100 +1055,100 @@ - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1158,7 +1158,7 @@ - + @@ -1173,25 +1173,11 @@ - + - - - - - - - - - - - - - - @@ -1202,33 +1188,18 @@ - + - - - - - - - - - - - - - - - + - @@ -1257,35 +1228,35 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - + + + + - - - + + + @@ -1294,24 +1265,18 @@ - - - - - - - - - - - + + + + + - - - + + + @@ -1320,17 +1285,11 @@ - - - - - - - + @@ -2179,7 +2138,7 @@ - + @@ -2202,7 +2161,7 @@ - + @@ -2229,7 +2188,7 @@ - + @@ -2379,17 +2338,13 @@ - + - - - - - + @@ -2400,11 +2355,7 @@ - - - - - + @@ -2485,17 +2436,13 @@ - - + + - - - - - + @@ -2506,11 +2453,7 @@ - - - - - + @@ -2582,8 +2525,8 @@ - - + + @@ -2630,8 +2573,8 @@ - - + + @@ -2689,7 +2632,7 @@ - + @@ -2700,7 +2643,7 @@ - + @@ -2714,10 +2657,6 @@ - - - - @@ -2726,10 +2665,10 @@ - + - + @@ -2740,7 +2679,7 @@ - + @@ -2760,7 +2699,7 @@ - + @@ -2780,7 +2719,7 @@ - + @@ -2825,8 +2764,8 @@ - - + + @@ -2834,91 +2773,91 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2928,19 +2867,18 @@ - + - + - @@ -2969,23 +2907,23 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + @@ -4350,7 +4288,7 @@ - + @@ -4664,8 +4602,8 @@ - - + + @@ -4673,7 +4611,7 @@ - + @@ -5201,9 +5139,9 @@ - + - + @@ -5214,55 +5152,55 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -5273,40 +5211,40 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -5317,55 +5255,55 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -5376,35 +5314,35 @@ - + - + - + - + - + - + - + - + - + - + - + - + @@ -5729,24 +5667,24 @@ - + - - + + - - - - + + + + - + diff --git a/overlays/tutorial_2.tcl b/overlays/tutorial_2.tcl index bb58d94..9977883 100644 --- a/overlays/tutorial_2.tcl +++ b/overlays/tutorial_2.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2018.3 +set scripts_vivado_version 2020.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -34,6 +34,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ +# To test this script, run the following commands from Vivado Tcl console: +# source tutorial_2_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + set list_projs [get_projects -quiet] if { $list_projs eq "" } { create_project tutorial_2 tutorial_2 -part xc7z020clg400-1 @@ -72,10 +79,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -96,19 +103,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -127,7 +134,7 @@ xilinx.com:ip:axi_dma:7.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -137,14 +144,14 @@ xilinx.com:ip:axi_dma:7.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -159,21 +166,21 @@ proc create_hier_cell_const_multiply { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_const_multiply() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_const_multiply() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -189,9 +196,13 @@ proc create_hier_cell_const_multiply { parentCell nameHier } { # Create interface pins create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_control + # Create pins create_bd_pin -dir I -type clk ap_clk @@ -213,7 +224,7 @@ proc create_hier_cell_const_multiply { parentCell nameHier } { connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins multiply_dma/M_AXI_MM2S] connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins multiply_dma/M_AXI_S2MM] connect_bd_intf_net -intf_net mult_constant_0_out_data [get_bd_intf_pins multiply/out_data] [get_bd_intf_pins multiply_dma/S_AXIS_S2MM] - connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins s_axi_AXILiteS] [get_bd_intf_pins multiply/s_axi_AXILiteS] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins s_axi_control] [get_bd_intf_pins multiply/s_axi_control] connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins multiply_dma/S_AXI_LITE] # Create port connections @@ -239,14 +250,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -259,8 +270,10 @@ proc create_root_design { parentCell } { # Create interface ports set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + # Create ports # Create instance: axi_mem_intercon, and set properties @@ -313,11 +326,13 @@ proc create_root_design { parentCell } { CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ @@ -488,11 +503,15 @@ proc create_root_design { parentCell } { CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ + CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ CONFIG.PCW_I2C_RESET_ENABLE {1} \ CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ @@ -720,7 +739,34 @@ proc create_root_design { parentCell } { CONFIG.PCW_MIO_9_PULLUP {enabled} \ CONFIG.PCW_MIO_9_SLEW {slow} \ CONFIG.PCW_MIO_PRIMITIVE {54} \ - CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS { \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#Enet 0 \ + 0#SD 0#USB \ + 0#SD 0#USB \ + 0#SD 0#USB \ + 0#UART 0#Enet \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + 0#USB 0#SD \ + Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART \ + Flash#GPIO#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + Flash#Quad SPI \ + GPIO#Quad SPI \ + Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet \ + } \ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ @@ -871,6 +917,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ @@ -895,6 +942,11 @@ proc create_root_design { parentCell } { CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ + CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \ CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ @@ -1023,6 +1075,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ CONFIG.PCW_USB_RESET_ENABLE {1} \ CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ @@ -1079,8 +1132,8 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins old_add/s_axi_AXILiteS] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins const_multiply/s_axi_AXILiteS] [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins old_add/s_axi_control] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins const_multiply/s_axi_control] [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI] connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins const_multiply/S_AXI_LITE] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI] # Create port connections @@ -1090,27 +1143,13 @@ proc create_root_design { parentCell } { connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins const_multiply/ap_rst_n] [get_bd_pins old_add/ap_rst_n] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] # Create address segments - create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs const_multiply/multiply_dma/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs const_multiply/multiply/s_axi_AXILiteS/Reg] SEG_mult_constant_0_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs old_add/s_axi_AXILiteS/Reg] SEG_old_add_Reg - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_0_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_0_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x01000000 -offset 0xFC000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_QSPI_LINEAR] SEG_processing_system7_0_ACP_QSPI_LINEAR - create_bd_addr_seg -range 0x01000000 -offset 0xFC000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_QSPI_LINEAR] SEG_processing_system7_0_ACP_QSPI_LINEAR - - # Exclude Address Segments - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_IOP] SEG_processing_system7_0_ACP_IOP - exclude_bd_addr_seg [get_bd_addr_segs const_multiply/multiply_dma/Data_MM2S/SEG_processing_system7_0_ACP_IOP] - - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_0_ACP_M_AXI_GP0 - exclude_bd_addr_seg [get_bd_addr_segs const_multiply/multiply_dma/Data_MM2S/SEG_processing_system7_0_ACP_M_AXI_GP0] - - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_IOP] SEG_processing_system7_0_ACP_IOP - exclude_bd_addr_seg [get_bd_addr_segs const_multiply/multiply_dma/Data_S2MM/SEG_processing_system7_0_ACP_IOP] - - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_0_ACP_M_AXI_GP0 - exclude_bd_addr_seg [get_bd_addr_segs const_multiply/multiply_dma/Data_S2MM/SEG_processing_system7_0_ACP_M_AXI_GP0] - + assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs const_multiply/multiply_dma/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs const_multiply/multiply/s_axi_control/Reg] -force + assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs old_add/s_axi_control/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] -force + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_DDR_LOWOCM] -force + assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces const_multiply/multiply_dma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_QSPI_LINEAR] -force + assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces const_multiply/multiply_dma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_ACP/ACP_QSPI_LINEAR] -force # Restore current instance