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  <header style="margin-bottom:2rem;">
    <p><a href="#projects">Projects</a> · <a href="#edu">Education</a> · <a href="#experience">Experience</a> · <a href="#skills-static">Skills</a></p>
  </header>
  <section id="contact-static"><h2>Contact</h2><p>Email: <b>dgazizul [at] uwaterloo [dot] ca</b></p><p>Links: <a href="https://github.com/sathworld" rel="noopener noreferrer">GitHub</a> · <a href="https://www.linkedin.com/in/dgazizullin/" rel="noopener noreferrer">LinkedIn</a></p></section>
  <section id="resumes"><h2>Resumes</h2><ul><li><a href="resumes/Damir%20Gazizullin%20-%20Electrical.pdf" download>Damir Gazizullin - Electrical</a></li><li><a href="resumes/Damir%20Gazizullin%20-%20Embedded.pdf" download>Damir Gazizullin - Embedded</a></li><li><a href="resumes/Damir%20Gazizullin%20-%20FPGA%20ASIC.pdf" download>Damir Gazizullin - FPGA ASIC</a></li></ul></section>
  
  <section id="projects">
    <h2>Projects</h2>
    <article class="project-item">
  <h3>Mixed Signal ASIC for Matrix-Vector Multiplication</h3>
  <p class="meta">June 2025 – November 2025</p>
  <p class="tags"><strong>Tags:</strong> ASIC, Signal Processing, Simulation, ASIC Layout</p>
  <p class="links"><a href="https://github.com/UW-ASIC/Matrix-Vector-Multiplier" rel="noopener noreferrer">Repository</a> · <a href="https://github.com/UW-ASIC/UWASIC-ALG" rel="noopener noreferrer">Custom-made Schematic Optimizer</a></p>
  
  <div class="images"><img src="/portfolio/mvm/MVM-ASIC-DIAGRAM.webp" alt="Matrix-Vector Multiplier Architecture Diagram" title="Matrix-Vector Multiplier Architecture Diagram" loading="lazy"><img src="/portfolio/mvm/VMM-Principle.png" alt="Principle of Operation Diagram" title="Principle of Operation Diagram" loading="lazy"></div>
  <ul class="bullets"><li>Computes matrix–vector products with programmable resistors (weights), DAC-driven inputs, TIAs, and SAR ADCs.</li><li>Defined SAR ADC architecture and conversion sequencing to digitize outputs Y1…Yn.</li><li>Designed trans-impedance amplifiers (TIAs) to sense and condition MVM currents for accurate readout.</li><li>Built voltage-source DACs to drive input vector voltages representing column entries −X1…−Xm.</li><li>Implemented programmable-resistor DACs to encode row entries per the system architecture.</li><li>Developed digital control and interface logic supporting AXI interface to drive biases, orchestrate conversions, and read back results.</li><li>Surveyed IEEE literature and alternative analog MVM implementations to guide design trade-offs.</li><li>Developed a custom tool that optimizes xschem schematics by running automated ngspice simulations and parameter sweeps.</li><li>Designed SAR ADC blocks and low-noise, high-bandwidth op-amps for TIA front-ends and buffering stages.</li></ul>
</article>
<article class="project-item">
  <h3>Custom 50V ESC PCBA for Micromobility Vehicles with BLDC Motors</h3>
  <p class="meta">May 2025 – September 2025</p>
  <p class="tags"><strong>Tags:</strong> PCBA, PCB</p>
  <p class="links"><a href="https://github.com/Electrium-Mobility/sresc" rel="noopener noreferrer">Repository</a></p>
  
  
  <ul class="bullets"><li>Designed a custom 4-layer PCB for a 50V brushless motor electronic speed controller (ESC) targeting micromobility vehicles.</li><li>Created the schematic and PCB layout in KiCad, ensuring signal integrity and thermal management for high-current paths.</li><li>Selected components and created a bill of materials (BOM) that reduced costs by over 30% while meeting performance requirements.</li><li>Increased availability of user-accessible GPIO by 10% compared to existing ESCs on the market.</li></ul>
</article>
<article class="project-item">
  <h3>FPGA Implementation of a configurable digital 512x512 Matrix-Vector Multiplier targeting Xilinx Series 7 FPGAs</h3>
  <p class="meta">July 2025 – August 2025</p>
  <p class="tags"><strong>Tags:</strong> RTL, FPGA, RTL Verification, Python, Signal Processing</p>
  <p class="links"><a href="https://github.com/sathworld/mvm" rel="noopener noreferrer">Repository</a></p>
  
  <div class="images"><img src="/portfolio/mvm327/MVM-FPGA-Block-Diagram.png" alt="Matrix-Vector Multiplier FPGA Block Diagram" title="Matrix-Vector Multiplier FPGA Block Diagram" loading="lazy"><img src="/portfolio/mvm327/MVM-FPGA-Resource-Usage.png" alt="Resource Usage on Xilinx Pynq-Z1" title="Resource Usage on Xilinx Pynq-Z1" loading="lazy"></div>
  <ul class="bullets"><li>Designed a highly configurable digital matrix-vector multiplier (MVM) in Verilog, capable of handling 512x512 matrices with 8-bit integers.</li><li>Implemented the design to utilize Xilinx Series 7 FPGA DSP slices for efficient multiplication and addition operations, utilizing bit-packing techniques and ternary adders to maximize resource efficiency.</li><li>Developed a Python-based testbench using cocotb to perform exhaustive verification of separate modules and the overall MVM system, achieving 100% functional coverage across all configurations.</li><li>Achieved a clock frequency of up to 300 MHz on a Xilinx Pynq-Z1 board, with throughput of 38.4 GOPS.</li><li>Obtained resource usage of approximately 95% of DSP slices and 70% of LUTs on the FPGA for the full 512x512 configuration.</li><li>Utilized various implementation strategies, including disabling synthesis optimizations and floorplanning, to meet timing constraints and optimize performance.</li></ul>
</article>
<article class="project-item">
  <h3>ASIC &amp; FPGA Implementation on a Torus NoC based on HopliteRT</h3>
  <p class="meta">May 2025 – August 2025</p>
  <p class="tags"><strong>Tags:</strong> Networks-on-Chip, RTL, ASIC, FPGA, RTL Verification, Python</p>
  <p class="links"><a href="https://github.com/sathworld/hoplitert-noc-verilog" rel="noopener noreferrer">Repository</a> · <a href="https://nachiket.github.io/publications/hoplitert_fpt-2017.pdf" rel="noopener noreferrer">HopliteRT</a></p>
  
  <div class="images"><img src="/portfolio/torus_noc/torus.png" alt="Network-on-Chip Architecture" title="Network-on-Chip Architecture" loading="lazy"></div>
  <ul class="bullets"><li>Implemented a 4x4 2D Torus Network-on-Chip using the HopliteRT router architecture, supporting virtual channels and deadlock-free routing.</li><li>Designed and verified the NoC (including router, switch, and a client interface components) in SystemVerilog, simulating with Verilator and to ensure correct functionality and performance.</li><li>Achieved timing closure on the ASIC design targeting the TSMC 65nm node using Synopsys Design Compiler and Innovus, meeting the performance and area requirements.</li><li>Successfully synthesized and implemented the NoC on a Xilinx Artix-7 FPGA, achieving a maximum clock frequency of 200 MHz.</li><li>Developed a script for custom placement of the NoC routers on the FPGA and floorplanning to optimize routing and minimize latency.</li></ul>
</article>
<article class="project-item">
  <h3>3D Torus NoC Simulator in Booksim</h3>
  <p class="meta">June 2025 – August 2025</p>
  <p class="tags"><strong>Tags:</strong> Networks-on-Chip, Booksim, Simulation, Python</p>
  <p class="links"><a href="https://github.com/VoarL/booksim2-3dtorus" rel="noopener noreferrer">Repository</a></p>
  <p class="files"><a href="/portfolio/booksim_3d_torus/3D_Torus_NoC_Report.pdf" target="_blank" rel="noopener noreferrer">Project Report</a></p>
  <div class="images"><img src="/portfolio/booksim_3d_torus/drawing-torus-elev-stack.png" alt="3D Torus Topology" title="3D Torus Topology" loading="lazy"><img src="/portfolio/booksim_3d_torus/ThroughputVSTopology.png" alt="Throughput vs Vertical Link Topology" title="Throughput vs Vertical Link Topology" loading="lazy"></div>
  <ul class="bullets"><li>Extended Booksim2 to support a 3D Torus with bidirectional Z-dimension meshing for reducing bottlenecks from through-silicon vias (TSVs).</li><li>Implemented elevator-first deterministic routing, ensuring livelock and deadlock freedom while prioritizing Z &gt; Y &gt; X traversal.</li><li>Developed Python tooling for flexible elevator mapping: users can specify elevator coordinates via CSV, visualize mappings, and customize nearest-elevator selection functions.</li><li>Modeled TSVs with realistic multi-cycle latency penalties and integrated them into Booksim’s credit-based flow control system.</li><li>Explored elevator placement patterns (diagonal, checkerboard, sub-tiling) and quantified performance tradeoffs across throughput, latency, and injection rate.</li><li>Demonstrated that bidirectional Z-meshing can nearly double sustainable throughput with only ~33% area overhead, with non-linear gains depending on elevator density.</li></ul>
</article>
<article class="project-item">
  <h3>SPI-connected PWM Generator</h3>
  <p class="meta">April 2025 – May 2025</p>
  <p class="tags"><strong>Tags:</strong> RTL, ASIC, Tapeout, RTL Verification, Python</p>
  <p class="links"><a href="https://github.com/sathworld/spi-pwm-peripheral" rel="noopener noreferrer">Repository</a> · <a href="https://gds-viewer.tinytapeout.com/?process=SG13G2&amp;model=https%3A%2F%2Fdamirg.com%2Fspi-pwm-peripheral%2F%2Ftinytapeout.gds" rel="noopener noreferrer">GDSII View</a></p>
  
  <div class="images"><img src="/portfolio/spi-pwm/SPI_PERIPH.drawio.png" alt="SPI PWM Generator Block Diagram" title="SPI PWM Generator Block Diagram" loading="lazy"><img src="/portfolio/spi-pwm/ASIC-GDS.png" alt="GDSII View" title="GDSII View" loading="lazy"></div>
  <ul class="bullets"><li>Designed an SPI‑controlled PWM with adjustable frequency and duty cycles for 8 outputs, 2 frequency generators, and 4 channels.</li><li>Implemented the design in RTL using Verilog, targeting a 130nm open source process node based on the IHP130 PDK.</li><li>Verified functionality through extensive simulation and formal verification methods.</li><li>Prepared design for tapeout, including GDSII generation and DRC/LVS checks.</li></ul>
</article>
<article class="project-item">
  <h3>Strivonix Main PCBA and Firmware</h3>
  <p class="meta">January 2025 – March 2025</p>
  <p class="tags"><strong>Tags:</strong> Firmware, C, IoT, PCB, PCBA, ESPIDF</p>
  <p class="links"><a href="https://www.strivonix.com" rel="noopener noreferrer">Strivonix Website</a></p>
  
  <div class="images"><img src="/portfolio/Strivonix/IMG_20250519_214240.jpg" alt="Strivonix Main PCBA" title="Strivonix Main PCBA" loading="lazy"><img src="/portfolio/Strivonix/IMG_20250519_214211.jpg" alt="Strivonix PCBA in the housing" title="Strivonix PCBA in the housing" loading="lazy"></div>
  <ul class="bullets"><li>Led the design and testing of a portable massage device's 4-layer PCB, exceeding the required targets and reducing BOM cost by over 30%.</li><li>Built ESP32-S3 firmware using ESP-IDF with FreeRTOS, utilizing software FSMs for peripheral interactions, achieving 95% accuracy for sensor readings using adaptively tuned Kalman filtering.</li><li>Implemented BLE drivers for the device to enable user-defined protocols that are saved in non-volatile memory (NVS).</li><li>Integrated OTA update functionality to enable remote firmware updates, improving maintainability and user experience.</li><li>Wrote comprehensive documentation for the PCB design and firmware architecture to facilitate future development and maintenance.</li><li>Conducted extensive testing and validation of the PCB and firmware to ensure reliability and performance under various operating conditions.</li></ul>
</article>
<article class="project-item">
  <h3>Custom 8-bit Computer Tapeout</h3>
  <p class="meta">September 2024 – December 2024</p>
  <p class="tags"><strong>Tags:</strong> RTL, RTL Verification, Python, Tapeout, ASIC</p>
  <p class="links"><a href="https://github.com/gjrchen/8-Bit-CPU-top" rel="noopener noreferrer">Repository</a> · <a href="https://legacy-gltf.gds-viewer.tinytapeout.com/?model=https://gjrchen.github.io/8-Bit-CPU-top/tinytapeout.gds.gltf" rel="noopener noreferrer">GDSII View</a></p>
  <p class="files"><a href="/portfolio/cpu8bit/8BitCPU_datasheet.pdf" target="_blank" rel="noopener noreferrer">CPU Datasheet</a></p>
  <div class="images"><img src="/portfolio/cpu8bit/CPU-GDS.png" alt="Post-Layout GDS" title="Post-Layout GDS" loading="lazy"><img src="/portfolio/cpu8bit/8bitSAP-1CPUArch.drawio.png" alt="8-bit SAP-1 CPU Architecture" title="8-bit SAP-1 CPU Architecture" loading="lazy"><img src="/portfolio/cpu8bit/CPU-mermaid.png" alt="CPU Execution State Diagram" title="CPU Execution State Diagram" loading="lazy"></div>
  <ul class="bullets"><li>Architected custom 8-bit ISA CPU with 16 instructions to balance datapath simplicity and opcode density.</li><li>Designed and verified pipelined ALU and register file blocks in Verilog, simulated with Verilator and cocotb.</li><li>Integrated modules from multiple teams to produce tapeout-ready GDS with &gt;20% area savings.</li><li>Validated timing with post-layout netlists and RC extraction to ensure functional accuracy.</li><li>Developed an on-chip programmer to flash programs and data into the RAM by communicating with an external MCU.</li><li>Broke instructions down into microinstructions to be carried out every CPU cycle, enabling the utilization of a single common bus and more complex instructions such as adding from the RAM.</li><li>Developed cocotb test suites for individual modules as well as complete integration tests.</li></ul>
</article>
<article class="project-item">
  <h3>Dino Game ASIC</h3>
  <p class="meta">January 2025 – March 2025</p>
  <p class="tags"><strong>Tags:</strong> RTL, RTL Verification, Verilator, Tapeout, FPGA, ASIC</p>
  <p class="links"><a href="https://github.com/UW-ASIC/Dino" rel="noopener noreferrer">Repository</a> · <a href="https://gds-viewer.tinytapeout.com/?model=https%3A%2F%2Fshuttle-assets.tinytapeout.com%2Fttihp25a%2Ftt_um_uwasic_dinogame%2Ftt_um_uwasic_dinogame.gds&amp;process=SG13G2" rel="noopener noreferrer">GDSII View</a></p>
  
  <div class="images"><img src="/portfolio/dinogame/ASIC.png" alt="Post-Layout GDS with visualized activity levels" title="Post-Layout GDS with visualized activity levels" loading="lazy"><img src="/portfolio/dinogame/DinoArchUWASIC.drawio.png" alt="Dino Architecture Diagram" title="Dino Architecture Diagram" loading="lazy"><img src="/portfolio/dinogame/Render.png" alt="Render Captured from an FPGA" title="Render Captured from an FPGA" loading="lazy"></div>
  <ul class="bullets"><li>Designed and FPGA-tested a 160×200 μm Dino Game ASIC with VGA output, submitted for tapeout via TinyTapeout.</li><li>Generated VGA output in real-time (“raced the beam”) to avoid frame buffer memory overhead due to ASIC size limits.</li><li>Architechted a custom graphics module with sprite rendering, collision detection, and game state management.</li><li>Created an elegant way for implementing different colour palettes that are switched based on the game state using only combinational logic.</li><li>Implemented a linear feedback shift register to generate random numbers and a basic physics engine for player physics.</li><li>Developed an autonomous controller in Verilog to play the game when no controller is detected on startup.</li><li>Developed VGA emulator in C++ using SDL2 and Verilat or to simulate chip input/output and test design in real time.</li></ul>
</article>
<article class="project-item">
  <h3>Wearable Telehealth Device</h3>
  <p class="meta">August 2022 – January 2023</p>
  <p class="tags"><strong>Tags:</strong> C++, MATLAB, Signal Processing, IoT</p>
  
  
  
  <ul class="bullets"><li>Built a WiFi-enabled wearable using an ESP8266 SoC and multiple I2C sensors for biometric monitoring.</li><li>Implemented ECG signal processing in MATLAB, achieving &gt;95% arrhythmia classification accuracy.</li><li>Created mobile dashboard with Blynk API and ThingSpeak for cloud monitoring and alerts.</li></ul>
</article>
  </section>
  
  <section id="edu">
    <h2>Education</h2>
    <p><strong>University of Waterloo</strong> – Waterloo, ON</p>
    <p>Candidate for Bachelor of Applied Science (B.A.Sc.), Electrical Engineering (GPA: 3.99)</p>
    <p>September 2022 – Present</p>
    <ul class="awards"><li>First in Class (Fall 2022, 1A)</li><li>First in Class (Spring 2023, 1B)</li><li>First in Class (Winter 2024, 2A)</li><li>First in Class (Fall 2024, 2B)</li></ul>
    <div class="courses"><h3>Selected Courses</h3><ul><li><strong>ECE 231</strong> Semiconductor Physics and Devices (Device Physics, EM)</li><li><strong>ECE 222</strong> Digital Computers (Comp Arch, Embedded)</li><li><strong>ECE 340</strong> Electronic Circuits 2 (Analog Design, Device Physics)</li><li><strong>ECE 331</strong> Electronic Devices (Device Physics, EM)</li><li><strong>ECE 493</strong> On-Chip Interconnect (Network-on-Chip) (Comp Arch, Digital Design)</li><li><strong>ECE 493</strong> Computer Arithmetic Hardware (Comp Arch, Digital Design)</li><li><strong>ECE 327</strong> Digital Hardware Systems (Digital Design, Embedded)</li><li><strong>ECE 320</strong> Computer Architecture (Comp Arch, Digital Design)</li><li><strong>ECE 318</strong> Communication Systems (Signal Processing, Analog Design)</li><li><strong>ECE 373</strong> Radio Frequency and Microwave Circuits (RF, EM, Analog Design)</li></ul></div>
  </section>
  
  <section id="experience">
    <h2>Experience</h2>
    <article class="exp-item">
  <h3>Product Development Coop – <a href="https://www.strivonix.com" rel="noopener noreferrer">Strivonix</a></h3>
  <ul class="bullets"><li>Led the design and testing of a portable pneumatic massage device's main 4-layer PCB, exceeding the required targets, achieving 97% functionality on the first design iteration and reducing BOM cost by over 30%.</li><li>Built ESP32-S3 firmware using ESP-IDF with FreeRTOS, utilizing software FSMs for peripheral interactions, achieving 95% accuracy for sensor readings using adaptively tuned Kalman filtering.</li><li>Implemented BLE drivers for the device to enable user-defined protocols that are saved in non-volatile memory (NVS).</li></ul>
</article>
<article class="exp-item">
  <h3>Founder &amp; Technical Lead – <a href="https://uwasic.com" rel="noopener noreferrer">UWASIC – IEEE SSCS Student Chapter</a></h3>
  <ul class="bullets"><li>Founded and led UWASIC, which became the IEEE Solid-State Circuits Society Student Chapter for the KW Section.</li><li>Directed Dino Game ASIC project that targets open-source PDKs (IHP Open130-G2, SkyWater SKY130), reduced used area by over 10%, led RTL design and integration, meeting the tapeout deadline ahead of schedule by 1 week.</li><li>Achieved timing closure on the design, yielding 15% of extra slack time in both PDKs using OpenSTA.</li><li>Built custom simulator/visualizer using Verilator and C++ to debug pipeline and FSM behavior issues pre-layout.</li><li>Developed the onboarding project for an SPI-connected PWM Output Expander in Verilog, recruiting 50+ members.</li><li>Implemented a 5-bit-operand mixed-signal matrix-vector multiplier that outperforms digital-only designs in area by 25%.</li></ul>
</article>
<article class="exp-item">
  <h3>Electrical Team Lead – <a href="https://electriummobility.com" rel="noopener noreferrer">Electrium Mobility</a></h3>
  <ul class="bullets"><li>Taught 20+ workshops on schematic capture, PCB layout and routing, board bring-up, as well as IPC-compliant design and soldering, improving the reliability of the submitted designs by 30%.</li><li>Designed and validated the design of a custom brushless motor electronic speed controller (ESC), reducing cost by 20% and extending the number of available IO by 10% compared to existing micromobility ESCs on the market.</li></ul>
</article>
  </section>
  
  <section id="skills-static">
    <h2>Skills</h2>
    <dl>
      <dt>ECAD/Tools</dt><dd>Vivado, cocotb, PSpice, Verilator, Altium Designer, KiCad, ESPIDF, Git, STM32CubeMX, Docker</dd><dt>Languages</dt><dd>Verilog, SystemVerilog, C++, C, Python, Tcl, MATLAB</dd><dt>Lab Equipment</dt><dd>Oscilloscope, Logic Analyzer, Spectral Analyzer, DMM, Hot Air Station, Soldering Iron</dd><dt>Certifications</dt><dd>IPC Certified Interconnect Designer (CID)</dd>
    </dl>
  </section>
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