Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL

[parker-research]

It would be awesome if this tool was similar to Verilator, in that it allowed running existing Verilog/VHDL code.

Ideally, it would support both:

• using existing testbenches (which would be valuable for porting code into RustHDL)
• using existing RTL code, with testbenches written in RustHDL (very similar to the Verilator model, but without gross C++ hassle)

Huge fan of this project, and wish there was more of it!

[samitbasu]

This is sort of possible in RHDL. You can integrate a rhdl-written test bench and verilog code into a single verilog artifact that you can run through a simulation tool. It's not particularly easy or ergonomic, but it is possible. I think the ideal case would be to redo what @zebreus did for RustHDL for RHDL, and provide some kind of macro to allow you to easily encapsulate Verilog into a RHDL design. I also saw someone had done some Rust-C++ magic to get a Rust app running inside a Verilog simulator. I'll look into it.