Support for ESP32 C3?

[muhammadqasimc]

Is there any support for ESP32 C3, I have a bunch of them and would like to utilise them as nodes, if supported is there a specific firmware available for it

[jeevadotnet]

I'm using 2 x old ESP32's just "fine" it seems.

Using "ESP32-S3 CSI Node Firmware" under:
/esp/esp-csi/examples/get-started/csi_recv_router

and then rewrote:

`main/app_main.c` to send a packed header matching the current Rust parser shape:

- magic `0xC5110001`
- fixed `node_id`
- `n_antennas = 1`
- `n_subcarriers = info->len / 2`
- `freq_mhz = 2437` for channel 6
- incrementing sequence number
- `rssi` and `noise_floor` from `wifi_pkt_rx_ctrl_t`
- raw `info->buf` copied after a 20-byte header

Board 1:
- chip: `ESP32-D0WD`
- flash: `4 MB`
- class: original ESP32

Board 2:
- chip: `ESP32-D0WDQ6-V3`
- flash: `4 MB`
- class: original ESP32

[ruvnet]

ESP32-C3 Status: Not Currently Supported

The firmware currently targets ESP32-S3 only. ESP32-C3 uses a RISC-V architecture (vs Xtensa on the S3), so the pre-built binaries won't work and a separate build target is needed.

The good news

ESP32-C3 does support CSI (starting with ESP-IDF v5.1+). The CSI API (esp_wifi_set_csi(), esp_wifi_set_csi_rx_cb()) is the same across variants. So a C3 port is technically feasible.

What would be needed

1. A separate sdkconfig.defaults.esp32c3 with CONFIG_IDF_TARGET="esp32c3"
2. The WASM3 component would need RISC-V compilation flags (currently Xtensa-only)
3. Reduced subcarrier count assumptions (C3 has 1 antenna, fewer spatial streams)
4. Partition table adjustment (C3 boards often have 4MB flash vs 8MB)

Workaround

You can build a minimal CSI sender on ESP32-C3 yourself using ESP-IDF's CSI example, and format the UDP frames to match our ADR-018 binary protocol (magic 0xC5110001, 20-byte header + I/Q data). The Rust aggregator will accept frames from any source as long as the format matches.

See also: #70 (earlier discussion on C3 compatibility)

We've added ESP32-C3 to the hardware support matrix in ADR-057. If there's community interest, we may add an official C3 build target in a future release.

[muhammadqasimc]

Thanks for the response, building it by myself seems a bit beyond my capabilities. So I look forward to an official build for ESP32 C3. Would love to be updated over here once that's implemented.

Thank you for this amazing project!

[ruvnet]

ESP32-C3 is not currently supported. The C3 is a single-core RISC-V chip without the dual-core Xtensa architecture that the firmware relies on (Core 0 for WiFi, Core 1 for DSP).

Key differences:

• C3: Single-core RISC-V, 400 KB SRAM, no PSRAM — too constrained for the full DSP pipeline
• S3: Dual-core Xtensa, 512 KB SRAM + up to 8 MB PSRAM — runs the full pipeline on Core 1

The CSI API is similar but the firmware's edge processing (biquad filters, Welford stats, multi-person vitals) needs the dedicated second core.

See also #70 which tracks the same question. For now, the ESP32-S3 is the only supported chip. The v0.4.3.1 release now supports both 4MB and 8MB S3 boards.