[32bit] branch on single bit

[jnk0le]

very common construct in peripheral/IO bound uC code

if (USART1->ISR & (1 << USART_ISR_RXNE_Pos)) { }

Normally the status bit needs to be extracted by andi or bexti followed by beqz/bnez

we could fuse the bexti + branch at quite low decoding cost

• addres offset stays the same
• shamt in place of rs2/imm5 as in beqi/bnei as well as bexti

only downsides are that the BRANCH major op can't fit another 2 branch instructions, and encoding is problematic on RV64.

On RV32E with peripherals mapped to upper GPRs we gain something like AVR8 SBIS/SBIC instruction

[jnk0le]

made a custom extension around that avr like IO concept: https://github.com/jnk0le/XTightlyCoupledIO

[jnk0le]

single bit can be tested by slli + bgez so bexti provides no advantage in this scenario