From f1f7c75c60671a051eb5c1967597b78e46081ba6 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Thu, 6 Feb 2025 18:36:00 +0100 Subject: [PATCH 1/3] treewide: Add version with delay line --- Bender.yml | 10 + Makefile | 2 + models/configurable_delay.behav.sv | 39 + models/configurable_delay.fpga.sv | 38 + src/regs/serial_link_delay_line.hjson | 376 ++ src/regs/serial_link_delay_line_reg_pkg.sv | 278 + src/regs/serial_link_delay_line_reg_top.sv | 5494 +++++++++++++++++ ...erial_link_single_channel_delay_line.hjson | 231 + ..._link_single_channel_delay_line_reg_pkg.sv | 187 + ..._link_single_channel_delay_line_reg_top.sv | 718 +++ src/serial_link.sv | 150 +- src/serial_link_occamy_wrapper.sv | 8 +- src/serial_link_physical_delay_line.sv | 216 + test/tb_axi_serial_link.sv | 9 +- test/tb_ch_calib_serial_link.sv | 9 +- 15 files changed, 7710 insertions(+), 55 deletions(-) create mode 100644 models/configurable_delay.behav.sv create mode 100644 models/configurable_delay.fpga.sv create mode 100644 src/regs/serial_link_delay_line.hjson create mode 100644 src/regs/serial_link_delay_line_reg_pkg.sv create mode 100644 src/regs/serial_link_delay_line_reg_top.sv create mode 100644 src/regs/serial_link_single_channel_delay_line.hjson create mode 100644 src/regs/serial_link_single_channel_delay_line_reg_pkg.sv create mode 100644 src/regs/serial_link_single_channel_delay_line_reg_top.sv create mode 100644 src/serial_link_physical_delay_line.sv diff --git a/Bender.yml b/Bender.yml index 4d7c30d..e3e69d6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -26,6 +26,10 @@ sources: - src/regs/serial_link_reg_top.sv - src/regs/serial_link_single_channel_reg_pkg.sv - src/regs/serial_link_single_channel_reg_top.sv + - src/regs/serial_link_delay_line_reg_pkg.sv + - src/regs/serial_link_delay_line_reg_top.sv + - src/regs/serial_link_single_channel_delay_line_reg_pkg.sv + - src/regs/serial_link_single_channel_delay_line_reg_top.sv # Parametrization - src/serial_link_pkg.sv @@ -39,6 +43,7 @@ sources: - src/serial_link_network.sv - src/serial_link_data_link.sv - src/serial_link_physical.sv + - src/serial_link_physical_delay_line.sv # Serial Link Wrapper - src/serial_link.sv @@ -56,8 +61,13 @@ sources: - target: test files: + - models/configurable_delay.behav.sv - test/tb_axi_serial_link.sv - test/tb_ch_calib_serial_link.sv - test/tb_stream_chopper.sv - test/tb_stream_chopper_dechopper.sv - test/tb_channel_allocator.sv + + - target: fpga + files: + - models/configurable_delay.fpga.sv diff --git a/Makefile b/Makefile index 5d4ffc4..ebed482 100644 --- a/Makefile +++ b/Makefile @@ -42,6 +42,8 @@ update-regs: src/regs/*.hjson echo $(REGGEN) $(REGGEN) src/regs/serial_link.hjson -r -t src/regs $(REGGEN) src/regs/serial_link_single_channel.hjson -r -t src/regs + $(REGGEN) src/regs/serial_link_delay_line.hjson -r -t src/regs + $(REGGEN) src/regs/serial_link_single_channel_delay_line.hjson -r -t src/regs # -------------- # QuestaSim diff --git a/models/configurable_delay.behav.sv b/models/configurable_delay.behav.sv new file mode 100644 index 0000000..f000ede --- /dev/null +++ b/models/configurable_delay.behav.sv @@ -0,0 +1,39 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Thomas Benz +// Paul Scheffler +// +// Based on work of: +// Fabian Schuiki +// Florian Zaruba + + +// Automatically generated by the Generic Delay generator. +`timescale 1ps/1ps + +(* no_ungroup *) +(* no_boundary_optimization *) +module configurable_delay #( + parameter int unsigned NUM_STEPS, // The desired number of delay taps. Must be + // a power of 2. Don't use very large values + // here, otherwise strategy to just let STA + // (with the right SDC) do the job for us + // will not work. + localparam DELAY_SEL_WIDTH = $clog2(NUM_STEPS) +) ( + input logic clk_i, + input logic enable_i, + input logic [DELAY_SEL_WIDTH-1:0] delay_i, + output logic clk_o +); + + logic enable_latched; + logic clk; + + assign clk = clk_i; + + always @(clk) clk_o <= #(real'(delay_i)*3.750ns/15) clk; + +endmodule diff --git a/models/configurable_delay.fpga.sv b/models/configurable_delay.fpga.sv new file mode 100644 index 0000000..4a727f4 --- /dev/null +++ b/models/configurable_delay.fpga.sv @@ -0,0 +1,38 @@ +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Thomas Benz +// Paul Scheffler +// +// Based on work of: +// Fabian Schuiki +// Florian Zaruba + +`timescale 1ps/1ps + +(* no_ungroup *) +(* no_boundary_optimization *) +module configurable_delay #( + parameter int unsigned NUM_STEPS, // The desired number of delay taps. Must be + // a power of 2. Don't use very large values + // here, otherwise strategy to just let STA + // (with the right SDC) do the job for us + // will not work. + localparam DELAY_SEL_WIDTH = $clog2(NUM_STEPS) +) ( + input logic clk_i, + input logic enable_i, + input logic [DELAY_SEL_WIDTH-1:0] delay_i, + output logic clk_o +); + + IBUF # + ( + .IBUF_LOW_PWR ("FALSE") + ) u_ibufg_sys_clk_o + ( + .I (clk_i), + .O (clk_o) + ); + +endmodule diff --git a/src/regs/serial_link_delay_line.hjson b/src/regs/serial_link_delay_line.hjson new file mode 100644 index 0000000..b98f409 --- /dev/null +++ b/src/regs/serial_link_delay_line.hjson @@ -0,0 +1,376 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Author: Alessandro Ottaviano + +{ + name: "serial_link_delay_line", + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: "32", + param_list: [ + { name: "NumChannels", + desc: "Number of channels", + type: "int", + default: "38", + local: "true" + }, + { name: "Log2NumChannels", + desc: "Number of channels", + type: "int", + default: "6", + local: "true" + }, + { name: "NumBits", + desc: "Number of bits transfered in one clock cycle (2*NumLanes for DDR, NumLanes for SDR)", + type: "int", + default: "16", + local: "true" + }, + { name: "Log2MaxClkDiv", + desc: "Number of bits for clock divider counter", + type: "int", + default: "10", + local: "true" + }, + { name: "FlushCounterWidth", + desc: "The number of bits used for the auto-flush counters in the channel allocator" + type: "int", + default: "8", + local: "true" + }, + { name: "Log2RawModeTXFifoDepth", + desc: "The depth of the TX FIFO for raw mode operation." + type: "int", + default: "3", + local: "true" + } + ], + + registers: [ + { + name: "CTRL", + desc: "Global clock, isolation and reset control configuration" + swaccess: "rw", + hwaccess: "hro", + // Clock disabled (i.e. gated) by default + fields: [ + { + bits: "0", + name: "clk_ena", + desc: "Clock gate enable for network, link, physical layer. (active-high)", + resval: 0, + }, + { + bits: "1", + name: "reset_n", + resval: 1, + // *Not* held in reset (i.e. signal high) by default. + // Since clock is gated on reset, inner serial link state should *not* change until ungate. + desc: "SW controlled synchronous reset. (active-low)" + }, + // All channels isolated by default + { + bits: "8", + name: "axi_in_isolate", + resval: 1, + desc: "Isolate AXI slave in port. (active-high)" + }, + { + bits: "9", + name: "axi_out_isolate", + resval: 1, + desc: "Isolate AXI master out port. (active-high)" + } + ] + }, + { + name: "ISOLATED", + desc: "Isolation status of AXI ports", + swaccess: "ro", + hwaccess: "hwo", + hwqe: "true", + hwext: "true", + // All channels isolated by default + fields: [ + {bits: "0:0", name: "axi_in", resval: 1, desc: "slave in isolation status"}, + {bits: "1:1", name: "axi_out", resval: 1, desc: "master out isolation status"}, + ] + }, + { + name: "RAW_MODE_EN", + desc: "Enables Raw mode", + swaccess: "wo", + hwaccess: "hro", + fields: [ + {bits: "0", resval: 0} + ] + }, + { + name: "RAW_MODE_IN_CH_SEL", + desc: "Receive channel select in RAW mode", + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "Log2NumChannels-1:0", + resval: 0 + } + ] + }, + {multireg: + { + name: "RAW_MODE_IN_DATA_VALID" + cname: "RAW_MODE_IN_DATA_VALID" + count: "NumChannels", + compact: "true", + desc: "Mask for valid data in RX FIFOs during RAW mode." + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { + bits: "0" + }, + ] + } + }, + { + name: "RAW_MODE_IN_DATA", + desc: "Data received by the selected channel in RAW mode", + swaccess: "ro", + hwaccess: "hrw", + hwext: "true", + hwre: "true", + fields: [ + { bits: "NumBits-1:0", + } + ] + }, + {multireg: + { + name: "RAW_MODE_OUT_CH_MASK" + cname: "RAW_MODE_OUT_CH_MASK" + count: "NumChannels", + compact: "true", + desc: "Selects channels to send out data in RAW mode, '1 corresponds to broadcasting" + swaccess: "wo", + hwaccess: "hro", + fields: [ + { + bits: "0", + resval: 0 + }, + ] + } + }, + { + name: "RAW_MODE_OUT_DATA_FIFO", + desc: "Data that will be pushed to the RAW mode output FIFO", + swaccess: "wo", + hwaccess: "hro", + hwqe: "true", + fields: [ + { bits: "NumBits-1:0", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_OUT_DATA_FIFO_CTRL", + desc: "Status and control register for the RAW mode data out FIFO", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + fields: [ + { + bits: "0", + name: "clear", + swaccess: "wo", + hwaccess: "hro", + desc: "Clears the raw mode TX FIFO.", + }, + { + bits: "8+Log2RawModeTXFifoDepth-1:8", + name: "fill_state", + swaccess: "ro", + hwaccess: "hwo", + desc: "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.", + resval: 0 + }, + { + bits: "31", + name: "is_full", + swaccess: "ro", + hwaccess: "hwo", + desc: "If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again.", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_OUT_EN", + desc: "Enable transmission of data currently hold in the output FIFO", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + resval: 0 + } + ] + }, + { + name: "FLOW_CONTROL_FIFO_CLEAR", + desc: "Clears the flow control Fifo", + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "0", + resval: 0 + } + ] + }, + { + name: "CHANNEL_ALLOC_TX_CFG" + desc: "Configuration settings for the TX side in the channel allocator" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "bypass_en", + desc: "Enable bypassing the TX channel allocator" + resval: 1 + }, + { + bits: "1", + name: "auto_flush_en", + desc: "Enable the auto-flush feature of the TX side in the channel allocator" + resval: 1 + }, + { + bits: "15:8", + name: "auto_flush_count", + desc: "The number of cycles to wait before auto flushing (sending) packets in the channel allocator", + resval: 2 + } + ] + }, + {multireg: + { + name: "CHANNEL_ALLOC_TX_CH_EN" + cname: "CHANNEL_ALLOC_TX_CH_EN" + count: "NumChannels", + compact: "true", + desc: "Channel enable mask for the TX side." + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + resval: 1 + }, + ] + } + }, + { + name: "CHANNEL_ALLOC_TX_CTRL", + desc: "Soft clear or force flush the TX side of the channel allocator", + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { + bits: "0", + name: "clear", + desc: "Software clear the TX side of the channel allocator", + }, + { + bits: "1", + name: "flush", + desc: "Flush (transmit remaining data) in the TX side of the channel allocator.", + } + ] + }, + { + name: "CHANNEL_ALLOC_RX_CFG" + desc: "Configuration settings for the RX side in the channel allocator" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "bypass_en", + desc: "Enable bypassing the RX channel allocator" + resval: 1 + }, + { + bits: "1", + name: "auto_flush_en", + desc: "Enable the auto-flush feature of the RX side in the channel allocator" + resval: 1 + }, + { + bits: "15:8", + name: "auto_flush_count", + desc: "The number of cycles to wait before synchronizing on partial packets on the RX side", + resval: 2 + }, + { + bits: "16", + name: "sync_en", + desc: "Enable (1) or disable (0) the synchronization barrier between the channels (needs to be disabled in raw mode).", + resval: 1 + } + ] + }, + { + name: "CHANNEL_ALLOC_RX_CTRL", + desc: "Soft clear the RX side of the channel allocator", + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { + bits: "0", + name: "clear", + desc: "Software clear the TX side of the channel allocator", + } + ] + }, + {multireg: + { + name: "CHANNEL_ALLOC_RX_CH_EN" + cname: "CHANNEL_ALLOC_RX_CH_EN" + count: "NumChannels", + compact: "true", + desc: "Channel enable mask for the RX side." + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + resval: 1 + }, + ] + } + }, + { + name: "QUADRATURE_CLOCK_DELAY", + desc: "Delay to get quadrature clock", + swaccess: "wo", + hwaccess: "hro", + fields: [ + {bits: "3:0", resval: 8} + ] + }, + ] +} diff --git a/src/regs/serial_link_delay_line_reg_pkg.sv b/src/regs/serial_link_delay_line_reg_pkg.sv new file mode 100644 index 0000000..c3c1f88 --- /dev/null +++ b/src/regs/serial_link_delay_line_reg_pkg.sv @@ -0,0 +1,278 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package serial_link_delay_line_reg_pkg; + + // Param list + parameter int NumChannels = 38; + parameter int Log2NumChannels = 6; + parameter int NumBits = 16; + parameter int Log2MaxClkDiv = 10; + parameter int FlushCounterWidth = 8; + parameter int Log2RawModeTXFifoDepth = 3; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } clk_ena; + struct packed { + logic q; + } reset_n; + struct packed { + logic q; + } axi_in_isolate; + struct packed { + logic q; + } axi_out_isolate; + } serial_link_delay_line_reg2hw_ctrl_reg_t; + + typedef struct packed { + logic q; + } serial_link_delay_line_reg2hw_raw_mode_en_reg_t; + + typedef struct packed { + logic [5:0] q; + } serial_link_delay_line_reg2hw_raw_mode_in_ch_sel_reg_t; + + typedef struct packed { + logic [15:0] q; + logic re; + } serial_link_delay_line_reg2hw_raw_mode_in_data_reg_t; + + typedef struct packed { + logic q; + } serial_link_delay_line_reg2hw_raw_mode_out_ch_mask_mreg_t; + + typedef struct packed { + logic [15:0] q; + logic qe; + } serial_link_delay_line_reg2hw_raw_mode_out_data_fifo_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } clear; + } serial_link_delay_line_reg2hw_raw_mode_out_data_fifo_ctrl_reg_t; + + typedef struct packed { + logic q; + } serial_link_delay_line_reg2hw_raw_mode_out_en_reg_t; + + typedef struct packed { + logic q; + logic qe; + } serial_link_delay_line_reg2hw_flow_control_fifo_clear_reg_t; + + typedef struct packed { + struct packed { + logic q; + } bypass_en; + struct packed { + logic q; + } auto_flush_en; + struct packed { + logic [7:0] q; + } auto_flush_count; + } serial_link_delay_line_reg2hw_channel_alloc_tx_cfg_reg_t; + + typedef struct packed { + logic q; + } serial_link_delay_line_reg2hw_channel_alloc_tx_ch_en_mreg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } clear; + struct packed { + logic q; + logic qe; + } flush; + } serial_link_delay_line_reg2hw_channel_alloc_tx_ctrl_reg_t; + + typedef struct packed { + struct packed { + logic q; + } bypass_en; + struct packed { + logic q; + } auto_flush_en; + struct packed { + logic [7:0] q; + } auto_flush_count; + struct packed { + logic q; + } sync_en; + } serial_link_delay_line_reg2hw_channel_alloc_rx_cfg_reg_t; + + typedef struct packed { + logic q; + logic qe; + } serial_link_delay_line_reg2hw_channel_alloc_rx_ctrl_reg_t; + + typedef struct packed { + logic q; + } serial_link_delay_line_reg2hw_channel_alloc_rx_ch_en_mreg_t; + + typedef struct packed { + logic [3:0] q; + } serial_link_delay_line_reg2hw_quadrature_clock_delay_reg_t; + + typedef struct packed { + struct packed { + logic d; + } axi_in; + struct packed { + logic d; + } axi_out; + } serial_link_delay_line_hw2reg_isolated_reg_t; + + typedef struct packed { + logic d; + } serial_link_delay_line_hw2reg_raw_mode_in_data_valid_mreg_t; + + typedef struct packed { + logic [15:0] d; + } serial_link_delay_line_hw2reg_raw_mode_in_data_reg_t; + + typedef struct packed { + struct packed { + logic [2:0] d; + } fill_state; + struct packed { + logic d; + } is_full; + } serial_link_delay_line_hw2reg_raw_mode_out_data_fifo_ctrl_reg_t; + + // Register -> HW type + typedef struct packed { + serial_link_delay_line_reg2hw_ctrl_reg_t ctrl; // [194:191] + serial_link_delay_line_reg2hw_raw_mode_en_reg_t raw_mode_en; // [190:190] + serial_link_delay_line_reg2hw_raw_mode_in_ch_sel_reg_t raw_mode_in_ch_sel; // [189:184] + serial_link_delay_line_reg2hw_raw_mode_in_data_reg_t raw_mode_in_data; // [183:167] + serial_link_delay_line_reg2hw_raw_mode_out_ch_mask_mreg_t [37:0] raw_mode_out_ch_mask; // [166:129] + serial_link_delay_line_reg2hw_raw_mode_out_data_fifo_reg_t raw_mode_out_data_fifo; // [128:112] + serial_link_delay_line_reg2hw_raw_mode_out_data_fifo_ctrl_reg_t raw_mode_out_data_fifo_ctrl; // [111:110] + serial_link_delay_line_reg2hw_raw_mode_out_en_reg_t raw_mode_out_en; // [109:109] + serial_link_delay_line_reg2hw_flow_control_fifo_clear_reg_t flow_control_fifo_clear; // [108:107] + serial_link_delay_line_reg2hw_channel_alloc_tx_cfg_reg_t channel_alloc_tx_cfg; // [106:97] + serial_link_delay_line_reg2hw_channel_alloc_tx_ch_en_mreg_t [37:0] channel_alloc_tx_ch_en; // [96:59] + serial_link_delay_line_reg2hw_channel_alloc_tx_ctrl_reg_t channel_alloc_tx_ctrl; // [58:55] + serial_link_delay_line_reg2hw_channel_alloc_rx_cfg_reg_t channel_alloc_rx_cfg; // [54:44] + serial_link_delay_line_reg2hw_channel_alloc_rx_ctrl_reg_t channel_alloc_rx_ctrl; // [43:42] + serial_link_delay_line_reg2hw_channel_alloc_rx_ch_en_mreg_t [37:0] channel_alloc_rx_ch_en; // [41:4] + serial_link_delay_line_reg2hw_quadrature_clock_delay_reg_t quadrature_clock_delay; // [3:0] + } serial_link_delay_line_reg2hw_t; + + // HW -> register type + typedef struct packed { + serial_link_delay_line_hw2reg_isolated_reg_t isolated; // [59:58] + serial_link_delay_line_hw2reg_raw_mode_in_data_valid_mreg_t [37:0] raw_mode_in_data_valid; // [57:20] + serial_link_delay_line_hw2reg_raw_mode_in_data_reg_t raw_mode_in_data; // [19:4] + serial_link_delay_line_hw2reg_raw_mode_out_data_fifo_ctrl_reg_t raw_mode_out_data_fifo_ctrl; // [3:0] + } serial_link_delay_line_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CTRL_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_ISOLATED_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_EN_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_CH_SEL_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_0_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_1_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_0_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_1_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_EN_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CFG_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_0_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_1_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CTRL_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CFG_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CTRL_OFFSET = 7'h 48; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_0_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_1_OFFSET = 7'h 50; + parameter logic [BlockAw-1:0] SERIAL_LINK_DELAY_LINE_QUADRATURE_CLOCK_DELAY_OFFSET = 7'h 54; + + // Reset values for hwext registers and their fields + parameter logic [1:0] SERIAL_LINK_DELAY_LINE_ISOLATED_RESVAL = 2'h 3; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_ISOLATED_AXI_IN_RESVAL = 1'h 1; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_ISOLATED_AXI_OUT_RESVAL = 1'h 1; + parameter logic [31:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_0_RESVAL = 32'h 0; + parameter logic [5:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_1_RESVAL = 6'h 0; + parameter logic [15:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_RESVAL = 16'h 0; + parameter logic [31:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_RESVAL = 32'h 0; + parameter logic [2:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_FILL_STATE_RESVAL = 3'h 0; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_IS_FULL_RESVAL = 1'h 0; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_RESVAL = 1'h 0; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_FLOW_CONTROL_FIFO_CLEAR_RESVAL = 1'h 0; + parameter logic [1:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CTRL_RESVAL = 2'h 0; + parameter logic [0:0] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CTRL_RESVAL = 1'h 0; + + // Register index + typedef enum int { + SERIAL_LINK_DELAY_LINE_CTRL, + SERIAL_LINK_DELAY_LINE_ISOLATED, + SERIAL_LINK_DELAY_LINE_RAW_MODE_EN, + SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_CH_SEL, + SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_0, + SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_1, + SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA, + SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_0, + SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_1, + SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO, + SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL, + SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_EN, + SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CFG, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_0, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_1, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CTRL, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CFG, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CTRL, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_0, + SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_1, + SERIAL_LINK_DELAY_LINE_QUADRATURE_CLOCK_DELAY + } serial_link_delay_line_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] SERIAL_LINK_DELAY_LINE_PERMIT [22] = '{ + 4'b 0011, // index[ 0] SERIAL_LINK_DELAY_LINE_CTRL + 4'b 0001, // index[ 1] SERIAL_LINK_DELAY_LINE_ISOLATED + 4'b 0001, // index[ 2] SERIAL_LINK_DELAY_LINE_RAW_MODE_EN + 4'b 0001, // index[ 3] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_CH_SEL + 4'b 1111, // index[ 4] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_0 + 4'b 0001, // index[ 5] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_1 + 4'b 0011, // index[ 6] SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA + 4'b 1111, // index[ 7] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_0 + 4'b 0001, // index[ 8] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_1 + 4'b 0011, // index[ 9] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO + 4'b 1111, // index[10] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL + 4'b 0001, // index[11] SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_EN + 4'b 0001, // index[12] SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR + 4'b 0011, // index[13] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CFG + 4'b 1111, // index[14] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_0 + 4'b 0001, // index[15] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_1 + 4'b 0001, // index[16] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CTRL + 4'b 0111, // index[17] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CFG + 4'b 0001, // index[18] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CTRL + 4'b 1111, // index[19] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_0 + 4'b 0001, // index[20] SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_1 + 4'b 0001 // index[21] SERIAL_LINK_DELAY_LINE_QUADRATURE_CLOCK_DELAY + }; + +endpackage + diff --git a/src/regs/serial_link_delay_line_reg_top.sv b/src/regs/serial_link_delay_line_reg_top.sv new file mode 100644 index 0000000..821ad46 --- /dev/null +++ b/src/regs/serial_link_delay_line_reg_top.sv @@ -0,0 +1,5494 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module serial_link_delay_line_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output serial_link_delay_line_reg_pkg::serial_link_delay_line_reg2hw_t reg2hw, // Write + input serial_link_delay_line_reg_pkg::serial_link_delay_line_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import serial_link_delay_line_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [BlockAw-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic ctrl_clk_ena_qs; + logic ctrl_clk_ena_wd; + logic ctrl_clk_ena_we; + logic ctrl_reset_n_qs; + logic ctrl_reset_n_wd; + logic ctrl_reset_n_we; + logic ctrl_axi_in_isolate_qs; + logic ctrl_axi_in_isolate_wd; + logic ctrl_axi_in_isolate_we; + logic ctrl_axi_out_isolate_qs; + logic ctrl_axi_out_isolate_wd; + logic ctrl_axi_out_isolate_we; + logic isolated_axi_in_qs; + logic isolated_axi_in_re; + logic isolated_axi_out_qs; + logic isolated_axi_out_re; + logic raw_mode_en_wd; + logic raw_mode_en_we; + logic [5:0] raw_mode_in_ch_sel_wd; + logic raw_mode_in_ch_sel_we; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_re; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_qs; + logic raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_re; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_qs; + logic raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_re; + logic [15:0] raw_mode_in_data_qs; + logic raw_mode_in_data_re; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_we; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_wd; + logic raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_we; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_wd; + logic raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_we; + logic [15:0] raw_mode_out_data_fifo_wd; + logic raw_mode_out_data_fifo_we; + logic raw_mode_out_data_fifo_ctrl_clear_wd; + logic raw_mode_out_data_fifo_ctrl_clear_we; + logic [2:0] raw_mode_out_data_fifo_ctrl_fill_state_qs; + logic raw_mode_out_data_fifo_ctrl_fill_state_re; + logic raw_mode_out_data_fifo_ctrl_is_full_qs; + logic raw_mode_out_data_fifo_ctrl_is_full_re; + logic raw_mode_out_en_qs; + logic raw_mode_out_en_wd; + logic raw_mode_out_en_we; + logic flow_control_fifo_clear_wd; + logic flow_control_fifo_clear_we; + logic channel_alloc_tx_cfg_bypass_en_qs; + logic channel_alloc_tx_cfg_bypass_en_wd; + logic channel_alloc_tx_cfg_bypass_en_we; + logic channel_alloc_tx_cfg_auto_flush_en_qs; + logic channel_alloc_tx_cfg_auto_flush_en_wd; + logic channel_alloc_tx_cfg_auto_flush_en_we; + logic [7:0] channel_alloc_tx_cfg_auto_flush_count_qs; + logic [7:0] channel_alloc_tx_cfg_auto_flush_count_wd; + logic channel_alloc_tx_cfg_auto_flush_count_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_we; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_qs; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_wd; + logic channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_we; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_qs; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_wd; + logic channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_we; + logic channel_alloc_tx_ctrl_clear_wd; + logic channel_alloc_tx_ctrl_clear_we; + logic channel_alloc_tx_ctrl_flush_wd; + logic channel_alloc_tx_ctrl_flush_we; + logic channel_alloc_rx_cfg_bypass_en_qs; + logic channel_alloc_rx_cfg_bypass_en_wd; + logic channel_alloc_rx_cfg_bypass_en_we; + logic channel_alloc_rx_cfg_auto_flush_en_qs; + logic channel_alloc_rx_cfg_auto_flush_en_wd; + logic channel_alloc_rx_cfg_auto_flush_en_we; + logic [7:0] channel_alloc_rx_cfg_auto_flush_count_qs; + logic [7:0] channel_alloc_rx_cfg_auto_flush_count_wd; + logic channel_alloc_rx_cfg_auto_flush_count_we; + logic channel_alloc_rx_cfg_sync_en_qs; + logic channel_alloc_rx_cfg_sync_en_wd; + logic channel_alloc_rx_cfg_sync_en_we; + logic channel_alloc_rx_ctrl_wd; + logic channel_alloc_rx_ctrl_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_we; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_qs; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_wd; + logic channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_we; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_qs; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_wd; + logic channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_we; + logic [3:0] quadrature_clock_delay_wd; + logic quadrature_clock_delay_we; + + // Register instances + // R[ctrl]: V(False) + + // F[clk_ena]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ctrl_clk_ena ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_clk_ena_we), + .wd (ctrl_clk_ena_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.clk_ena.q ), + + // to register interface (read) + .qs (ctrl_clk_ena_qs) + ); + + + // F[reset_n]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_reset_n ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_reset_n_we), + .wd (ctrl_reset_n_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.reset_n.q ), + + // to register interface (read) + .qs (ctrl_reset_n_qs) + ); + + + // F[axi_in_isolate]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_axi_in_isolate ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_axi_in_isolate_we), + .wd (ctrl_axi_in_isolate_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.axi_in_isolate.q ), + + // to register interface (read) + .qs (ctrl_axi_in_isolate_qs) + ); + + + // F[axi_out_isolate]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_axi_out_isolate ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_axi_out_isolate_we), + .wd (ctrl_axi_out_isolate_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.axi_out_isolate.q ), + + // to register interface (read) + .qs (ctrl_axi_out_isolate_qs) + ); + + + // R[isolated]: V(True) + + // F[axi_in]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_isolated_axi_in ( + .re (isolated_axi_in_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.isolated.axi_in.d), + .qre (), + .qe (), + .q (), + .qs (isolated_axi_in_qs) + ); + + + // F[axi_out]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_isolated_axi_out ( + .re (isolated_axi_out_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.isolated.axi_out.d), + .qre (), + .qe (), + .q (), + .qs (isolated_axi_out_qs) + ); + + + // R[raw_mode_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_en_we), + .wd (raw_mode_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_en.q ), + + .qs () + ); + + + // R[raw_mode_in_ch_sel]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("WO"), + .RESVAL (6'h0) + ) u_raw_mode_in_ch_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_in_ch_sel_we), + .wd (raw_mode_in_ch_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_in_ch_sel.q ), + + .qs () + ); + + + + // Subregister 0 of Multireg raw_mode_in_data_valid + // R[raw_mode_in_data_valid_0]: V(True) + + // F[raw_mode_in_data_valid_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_0 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[0].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_qs) + ); + + + // F[raw_mode_in_data_valid_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_1 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[1].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_qs) + ); + + + // F[raw_mode_in_data_valid_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_2 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[2].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_qs) + ); + + + // F[raw_mode_in_data_valid_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_3 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[3].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_qs) + ); + + + // F[raw_mode_in_data_valid_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_4 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[4].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_qs) + ); + + + // F[raw_mode_in_data_valid_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_5 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[5].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_qs) + ); + + + // F[raw_mode_in_data_valid_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_6 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[6].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_qs) + ); + + + // F[raw_mode_in_data_valid_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_7 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[7].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_qs) + ); + + + // F[raw_mode_in_data_valid_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_8 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[8].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_qs) + ); + + + // F[raw_mode_in_data_valid_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_9 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[9].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_qs) + ); + + + // F[raw_mode_in_data_valid_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_10 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[10].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_qs) + ); + + + // F[raw_mode_in_data_valid_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_11 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[11].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_qs) + ); + + + // F[raw_mode_in_data_valid_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_12 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[12].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_qs) + ); + + + // F[raw_mode_in_data_valid_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_13 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[13].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_qs) + ); + + + // F[raw_mode_in_data_valid_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_14 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[14].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_qs) + ); + + + // F[raw_mode_in_data_valid_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_15 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[15].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_qs) + ); + + + // F[raw_mode_in_data_valid_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_16 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[16].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_qs) + ); + + + // F[raw_mode_in_data_valid_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_17 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[17].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_qs) + ); + + + // F[raw_mode_in_data_valid_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_18 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[18].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_qs) + ); + + + // F[raw_mode_in_data_valid_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_19 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[19].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_qs) + ); + + + // F[raw_mode_in_data_valid_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_20 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[20].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_qs) + ); + + + // F[raw_mode_in_data_valid_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_21 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[21].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_qs) + ); + + + // F[raw_mode_in_data_valid_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_22 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[22].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_qs) + ); + + + // F[raw_mode_in_data_valid_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_23 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[23].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_qs) + ); + + + // F[raw_mode_in_data_valid_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_24 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[24].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_qs) + ); + + + // F[raw_mode_in_data_valid_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_25 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[25].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_qs) + ); + + + // F[raw_mode_in_data_valid_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_26 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[26].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_qs) + ); + + + // F[raw_mode_in_data_valid_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_27 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[27].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_qs) + ); + + + // F[raw_mode_in_data_valid_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_28 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[28].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_qs) + ); + + + // F[raw_mode_in_data_valid_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_29 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[29].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_qs) + ); + + + // F[raw_mode_in_data_valid_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_30 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[30].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_qs) + ); + + + // F[raw_mode_in_data_valid_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_0_raw_mode_in_data_valid_31 ( + .re (raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[31].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_qs) + ); + + + // Subregister 32 of Multireg raw_mode_in_data_valid + // R[raw_mode_in_data_valid_1]: V(True) + + // F[raw_mode_in_data_valid_32]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_32 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[32].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_qs) + ); + + + // F[raw_mode_in_data_valid_33]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_33 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[33].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_qs) + ); + + + // F[raw_mode_in_data_valid_34]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_34 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[34].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_qs) + ); + + + // F[raw_mode_in_data_valid_35]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_35 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[35].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_qs) + ); + + + // F[raw_mode_in_data_valid_36]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_36 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[36].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_qs) + ); + + + // F[raw_mode_in_data_valid_37]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid_1_raw_mode_in_data_valid_37 ( + .re (raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid[37].d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_qs) + ); + + + + // R[raw_mode_in_data]: V(True) + + prim_subreg_ext #( + .DW (16) + ) u_raw_mode_in_data ( + .re (raw_mode_in_data_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data.d), + .qre (reg2hw.raw_mode_in_data.re), + .qe (), + .q (reg2hw.raw_mode_in_data.q ), + .qs (raw_mode_in_data_qs) + ); + + + + // Subregister 0 of Multireg raw_mode_out_ch_mask + // R[raw_mode_out_ch_mask_0]: V(False) + + // F[raw_mode_out_ch_mask_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[0].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[1].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[2].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[3].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[4].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[5].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[6].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[7].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[8].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[9].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[10].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[11].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[12].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[13].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[14].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[15].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[16].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[17].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[18].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[19].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[20].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[21].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[22].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[23].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[24].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[25].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[26].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[27].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[28].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[29].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[30].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_we), + .wd (raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[31].q ), + + .qs () + ); + + + // Subregister 32 of Multireg raw_mode_out_ch_mask + // R[raw_mode_out_ch_mask_1]: V(False) + + // F[raw_mode_out_ch_mask_32]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[32].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_33]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[33].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_34]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[34].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_35]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[35].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_36]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[36].q ), + + .qs () + ); + + + // F[raw_mode_out_ch_mask_37]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_we), + .wd (raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask[37].q ), + + .qs () + ); + + + + // R[raw_mode_out_data_fifo]: V(False) + + prim_subreg #( + .DW (16), + .SWACCESS("WO"), + .RESVAL (16'h0) + ) u_raw_mode_out_data_fifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_data_fifo_we), + .wd (raw_mode_out_data_fifo_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.raw_mode_out_data_fifo.qe), + .q (reg2hw.raw_mode_out_data_fifo.q ), + + .qs () + ); + + + // R[raw_mode_out_data_fifo_ctrl]: V(True) + + // F[clear]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_out_data_fifo_ctrl_clear ( + .re (1'b0), + .we (raw_mode_out_data_fifo_ctrl_clear_we), + .wd (raw_mode_out_data_fifo_ctrl_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.raw_mode_out_data_fifo_ctrl.clear.qe), + .q (reg2hw.raw_mode_out_data_fifo_ctrl.clear.q ), + .qs () + ); + + + // F[fill_state]: 10:8 + prim_subreg_ext #( + .DW (3) + ) u_raw_mode_out_data_fifo_ctrl_fill_state ( + .re (raw_mode_out_data_fifo_ctrl_fill_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_out_data_fifo_ctrl.fill_state.d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_out_data_fifo_ctrl_fill_state_qs) + ); + + + // F[is_full]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_out_data_fifo_ctrl_is_full ( + .re (raw_mode_out_data_fifo_ctrl_is_full_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_out_data_fifo_ctrl.is_full.d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_out_data_fifo_ctrl_is_full_qs) + ); + + + // R[raw_mode_out_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_raw_mode_out_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_en_we), + .wd (raw_mode_out_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_en.q ), + + // to register interface (read) + .qs (raw_mode_out_en_qs) + ); + + + // R[flow_control_fifo_clear]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_flow_control_fifo_clear ( + .re (1'b0), + .we (flow_control_fifo_clear_we), + .wd (flow_control_fifo_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.flow_control_fifo_clear.qe), + .q (reg2hw.flow_control_fifo_clear.q ), + .qs () + ); + + + // R[channel_alloc_tx_cfg]: V(False) + + // F[bypass_en]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_cfg_bypass_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_cfg_bypass_en_we), + .wd (channel_alloc_tx_cfg_bypass_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_cfg.bypass_en.q ), + + // to register interface (read) + .qs (channel_alloc_tx_cfg_bypass_en_qs) + ); + + + // F[auto_flush_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_cfg_auto_flush_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_cfg_auto_flush_en_we), + .wd (channel_alloc_tx_cfg_auto_flush_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_cfg.auto_flush_en.q ), + + // to register interface (read) + .qs (channel_alloc_tx_cfg_auto_flush_en_qs) + ); + + + // F[auto_flush_count]: 15:8 + prim_subreg #( + .DW (8), + .SWACCESS("RW"), + .RESVAL (8'h2) + ) u_channel_alloc_tx_cfg_auto_flush_count ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_cfg_auto_flush_count_we), + .wd (channel_alloc_tx_cfg_auto_flush_count_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_cfg.auto_flush_count.q ), + + // to register interface (read) + .qs (channel_alloc_tx_cfg_auto_flush_count_qs) + ); + + + + // Subregister 0 of Multireg channel_alloc_tx_ch_en + // R[channel_alloc_tx_ch_en_0]: V(False) + + // F[channel_alloc_tx_ch_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[0].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_qs) + ); + + + // F[channel_alloc_tx_ch_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[1].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_qs) + ); + + + // F[channel_alloc_tx_ch_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[2].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_qs) + ); + + + // F[channel_alloc_tx_ch_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[3].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_qs) + ); + + + // F[channel_alloc_tx_ch_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[4].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_qs) + ); + + + // F[channel_alloc_tx_ch_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[5].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_qs) + ); + + + // F[channel_alloc_tx_ch_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[6].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_qs) + ); + + + // F[channel_alloc_tx_ch_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[7].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_qs) + ); + + + // F[channel_alloc_tx_ch_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[8].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_qs) + ); + + + // F[channel_alloc_tx_ch_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[9].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_qs) + ); + + + // F[channel_alloc_tx_ch_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[10].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_qs) + ); + + + // F[channel_alloc_tx_ch_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[11].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_qs) + ); + + + // F[channel_alloc_tx_ch_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[12].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_qs) + ); + + + // F[channel_alloc_tx_ch_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[13].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_qs) + ); + + + // F[channel_alloc_tx_ch_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[14].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_qs) + ); + + + // F[channel_alloc_tx_ch_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[15].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_qs) + ); + + + // F[channel_alloc_tx_ch_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[16].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_qs) + ); + + + // F[channel_alloc_tx_ch_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[17].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_qs) + ); + + + // F[channel_alloc_tx_ch_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[18].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_qs) + ); + + + // F[channel_alloc_tx_ch_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[19].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_qs) + ); + + + // F[channel_alloc_tx_ch_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[20].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_qs) + ); + + + // F[channel_alloc_tx_ch_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[21].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_qs) + ); + + + // F[channel_alloc_tx_ch_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[22].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_qs) + ); + + + // F[channel_alloc_tx_ch_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[23].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_qs) + ); + + + // F[channel_alloc_tx_ch_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[24].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_qs) + ); + + + // F[channel_alloc_tx_ch_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[25].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_qs) + ); + + + // F[channel_alloc_tx_ch_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[26].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_qs) + ); + + + // F[channel_alloc_tx_ch_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[27].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_qs) + ); + + + // F[channel_alloc_tx_ch_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[28].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_qs) + ); + + + // F[channel_alloc_tx_ch_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[29].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_qs) + ); + + + // F[channel_alloc_tx_ch_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[30].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_qs) + ); + + + // F[channel_alloc_tx_ch_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_we), + .wd (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[31].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_qs) + ); + + + // Subregister 32 of Multireg channel_alloc_tx_ch_en + // R[channel_alloc_tx_ch_en_1]: V(False) + + // F[channel_alloc_tx_ch_en_32]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[32].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_qs) + ); + + + // F[channel_alloc_tx_ch_en_33]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[33].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_qs) + ); + + + // F[channel_alloc_tx_ch_en_34]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[34].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_qs) + ); + + + // F[channel_alloc_tx_ch_en_35]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[35].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_qs) + ); + + + // F[channel_alloc_tx_ch_en_36]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[36].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_qs) + ); + + + // F[channel_alloc_tx_ch_en_37]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_we), + .wd (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_tx_ch_en[37].q ), + + // to register interface (read) + .qs (channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_qs) + ); + + + + // R[channel_alloc_tx_ctrl]: V(True) + + // F[clear]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_channel_alloc_tx_ctrl_clear ( + .re (1'b0), + .we (channel_alloc_tx_ctrl_clear_we), + .wd (channel_alloc_tx_ctrl_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.channel_alloc_tx_ctrl.clear.qe), + .q (reg2hw.channel_alloc_tx_ctrl.clear.q ), + .qs () + ); + + + // F[flush]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_channel_alloc_tx_ctrl_flush ( + .re (1'b0), + .we (channel_alloc_tx_ctrl_flush_we), + .wd (channel_alloc_tx_ctrl_flush_wd), + .d ('0), + .qre (), + .qe (reg2hw.channel_alloc_tx_ctrl.flush.qe), + .q (reg2hw.channel_alloc_tx_ctrl.flush.q ), + .qs () + ); + + + // R[channel_alloc_rx_cfg]: V(False) + + // F[bypass_en]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_cfg_bypass_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_cfg_bypass_en_we), + .wd (channel_alloc_rx_cfg_bypass_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_cfg.bypass_en.q ), + + // to register interface (read) + .qs (channel_alloc_rx_cfg_bypass_en_qs) + ); + + + // F[auto_flush_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_cfg_auto_flush_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_cfg_auto_flush_en_we), + .wd (channel_alloc_rx_cfg_auto_flush_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_cfg.auto_flush_en.q ), + + // to register interface (read) + .qs (channel_alloc_rx_cfg_auto_flush_en_qs) + ); + + + // F[auto_flush_count]: 15:8 + prim_subreg #( + .DW (8), + .SWACCESS("RW"), + .RESVAL (8'h2) + ) u_channel_alloc_rx_cfg_auto_flush_count ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_cfg_auto_flush_count_we), + .wd (channel_alloc_rx_cfg_auto_flush_count_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_cfg.auto_flush_count.q ), + + // to register interface (read) + .qs (channel_alloc_rx_cfg_auto_flush_count_qs) + ); + + + // F[sync_en]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_cfg_sync_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_cfg_sync_en_we), + .wd (channel_alloc_rx_cfg_sync_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_cfg.sync_en.q ), + + // to register interface (read) + .qs (channel_alloc_rx_cfg_sync_en_qs) + ); + + + // R[channel_alloc_rx_ctrl]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_channel_alloc_rx_ctrl ( + .re (1'b0), + .we (channel_alloc_rx_ctrl_we), + .wd (channel_alloc_rx_ctrl_wd), + .d ('0), + .qre (), + .qe (reg2hw.channel_alloc_rx_ctrl.qe), + .q (reg2hw.channel_alloc_rx_ctrl.q ), + .qs () + ); + + + + // Subregister 0 of Multireg channel_alloc_rx_ch_en + // R[channel_alloc_rx_ch_en_0]: V(False) + + // F[channel_alloc_rx_ch_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[0].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_qs) + ); + + + // F[channel_alloc_rx_ch_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[1].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_qs) + ); + + + // F[channel_alloc_rx_ch_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[2].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_qs) + ); + + + // F[channel_alloc_rx_ch_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[3].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_qs) + ); + + + // F[channel_alloc_rx_ch_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[4].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_qs) + ); + + + // F[channel_alloc_rx_ch_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[5].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_qs) + ); + + + // F[channel_alloc_rx_ch_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[6].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_qs) + ); + + + // F[channel_alloc_rx_ch_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[7].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_qs) + ); + + + // F[channel_alloc_rx_ch_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[8].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_qs) + ); + + + // F[channel_alloc_rx_ch_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[9].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_qs) + ); + + + // F[channel_alloc_rx_ch_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[10].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_qs) + ); + + + // F[channel_alloc_rx_ch_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[11].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_qs) + ); + + + // F[channel_alloc_rx_ch_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[12].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_qs) + ); + + + // F[channel_alloc_rx_ch_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[13].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_qs) + ); + + + // F[channel_alloc_rx_ch_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[14].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_qs) + ); + + + // F[channel_alloc_rx_ch_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[15].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_qs) + ); + + + // F[channel_alloc_rx_ch_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[16].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_qs) + ); + + + // F[channel_alloc_rx_ch_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[17].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_qs) + ); + + + // F[channel_alloc_rx_ch_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[18].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_qs) + ); + + + // F[channel_alloc_rx_ch_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[19].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_qs) + ); + + + // F[channel_alloc_rx_ch_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[20].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_qs) + ); + + + // F[channel_alloc_rx_ch_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[21].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_qs) + ); + + + // F[channel_alloc_rx_ch_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[22].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_qs) + ); + + + // F[channel_alloc_rx_ch_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[23].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_qs) + ); + + + // F[channel_alloc_rx_ch_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[24].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_qs) + ); + + + // F[channel_alloc_rx_ch_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[25].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_qs) + ); + + + // F[channel_alloc_rx_ch_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[26].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_qs) + ); + + + // F[channel_alloc_rx_ch_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[27].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_qs) + ); + + + // F[channel_alloc_rx_ch_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[28].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_qs) + ); + + + // F[channel_alloc_rx_ch_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[29].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_qs) + ); + + + // F[channel_alloc_rx_ch_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[30].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_qs) + ); + + + // F[channel_alloc_rx_ch_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_we), + .wd (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[31].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_qs) + ); + + + // Subregister 32 of Multireg channel_alloc_rx_ch_en + // R[channel_alloc_rx_ch_en_1]: V(False) + + // F[channel_alloc_rx_ch_en_32]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[32].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_qs) + ); + + + // F[channel_alloc_rx_ch_en_33]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[33].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_qs) + ); + + + // F[channel_alloc_rx_ch_en_34]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[34].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_qs) + ); + + + // F[channel_alloc_rx_ch_en_35]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[35].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_qs) + ); + + + // F[channel_alloc_rx_ch_en_36]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[36].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_qs) + ); + + + // F[channel_alloc_rx_ch_en_37]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_we), + .wd (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.channel_alloc_rx_ch_en[37].q ), + + // to register interface (read) + .qs (channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_qs) + ); + + + + // R[quadrature_clock_delay]: V(False) + + prim_subreg #( + .DW (4), + .SWACCESS("WO"), + .RESVAL (4'h8) + ) u_quadrature_clock_delay ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (quadrature_clock_delay_we), + .wd (quadrature_clock_delay_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.quadrature_clock_delay.q ), + + .qs () + ); + + + + + logic [21:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == SERIAL_LINK_DELAY_LINE_CTRL_OFFSET); + addr_hit[ 1] = (reg_addr == SERIAL_LINK_DELAY_LINE_ISOLATED_OFFSET); + addr_hit[ 2] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_EN_OFFSET); + addr_hit[ 3] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_CH_SEL_OFFSET); + addr_hit[ 4] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_0_OFFSET); + addr_hit[ 5] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_VALID_1_OFFSET); + addr_hit[ 6] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_IN_DATA_OFFSET); + addr_hit[ 7] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_0_OFFSET); + addr_hit[ 8] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_CH_MASK_1_OFFSET); + addr_hit[ 9] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_OFFSET); + addr_hit[10] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_OFFSET); + addr_hit[11] = (reg_addr == SERIAL_LINK_DELAY_LINE_RAW_MODE_OUT_EN_OFFSET); + addr_hit[12] = (reg_addr == SERIAL_LINK_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_OFFSET); + addr_hit[13] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CFG_OFFSET); + addr_hit[14] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_0_OFFSET); + addr_hit[15] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CH_EN_1_OFFSET); + addr_hit[16] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_TX_CTRL_OFFSET); + addr_hit[17] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CFG_OFFSET); + addr_hit[18] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CTRL_OFFSET); + addr_hit[19] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_0_OFFSET); + addr_hit[20] = (reg_addr == SERIAL_LINK_DELAY_LINE_CHANNEL_ALLOC_RX_CH_EN_1_OFFSET); + addr_hit[21] = (reg_addr == SERIAL_LINK_DELAY_LINE_QUADRATURE_CLOCK_DELAY_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(SERIAL_LINK_DELAY_LINE_PERMIT[21] & ~reg_be))))); + end + + assign ctrl_clk_ena_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_clk_ena_wd = reg_wdata[0]; + + assign ctrl_reset_n_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_reset_n_wd = reg_wdata[1]; + + assign ctrl_axi_in_isolate_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_axi_in_isolate_wd = reg_wdata[8]; + + assign ctrl_axi_out_isolate_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_axi_out_isolate_wd = reg_wdata[9]; + + assign isolated_axi_in_re = addr_hit[1] & reg_re & !reg_error; + + assign isolated_axi_out_re = addr_hit[1] & reg_re & !reg_error; + + assign raw_mode_en_we = addr_hit[2] & reg_we & !reg_error; + assign raw_mode_en_wd = reg_wdata[0]; + + assign raw_mode_in_ch_sel_we = addr_hit[3] & reg_we & !reg_error; + assign raw_mode_in_ch_sel_wd = reg_wdata[5:0]; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_in_data_re = addr_hit[6] & reg_re & !reg_error; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_0_wd = reg_wdata[0]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_1_wd = reg_wdata[1]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_2_wd = reg_wdata[2]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_3_wd = reg_wdata[3]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_4_wd = reg_wdata[4]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_5_wd = reg_wdata[5]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_6_wd = reg_wdata[6]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_7_wd = reg_wdata[7]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_8_wd = reg_wdata[8]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_9_wd = reg_wdata[9]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_10_wd = reg_wdata[10]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_11_wd = reg_wdata[11]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_12_wd = reg_wdata[12]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_13_wd = reg_wdata[13]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_14_wd = reg_wdata[14]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_15_wd = reg_wdata[15]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_16_wd = reg_wdata[16]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_17_wd = reg_wdata[17]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_18_wd = reg_wdata[18]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_19_wd = reg_wdata[19]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_20_wd = reg_wdata[20]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_21_wd = reg_wdata[21]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_22_wd = reg_wdata[22]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_23_wd = reg_wdata[23]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_24_wd = reg_wdata[24]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_25_wd = reg_wdata[25]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_26_wd = reg_wdata[26]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_27_wd = reg_wdata[27]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_28_wd = reg_wdata[28]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_29_wd = reg_wdata[29]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_30_wd = reg_wdata[30]; + + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_0_raw_mode_out_ch_mask_31_wd = reg_wdata[31]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_32_wd = reg_wdata[0]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_33_wd = reg_wdata[1]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_34_wd = reg_wdata[2]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_35_wd = reg_wdata[3]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_36_wd = reg_wdata[4]; + + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_1_raw_mode_out_ch_mask_37_wd = reg_wdata[5]; + + assign raw_mode_out_data_fifo_we = addr_hit[9] & reg_we & !reg_error; + assign raw_mode_out_data_fifo_wd = reg_wdata[15:0]; + + assign raw_mode_out_data_fifo_ctrl_clear_we = addr_hit[10] & reg_we & !reg_error; + assign raw_mode_out_data_fifo_ctrl_clear_wd = reg_wdata[0]; + + assign raw_mode_out_data_fifo_ctrl_fill_state_re = addr_hit[10] & reg_re & !reg_error; + + assign raw_mode_out_data_fifo_ctrl_is_full_re = addr_hit[10] & reg_re & !reg_error; + + assign raw_mode_out_en_we = addr_hit[11] & reg_we & !reg_error; + assign raw_mode_out_en_wd = reg_wdata[0]; + + assign flow_control_fifo_clear_we = addr_hit[12] & reg_we & !reg_error; + assign flow_control_fifo_clear_wd = reg_wdata[0]; + + assign channel_alloc_tx_cfg_bypass_en_we = addr_hit[13] & reg_we & !reg_error; + assign channel_alloc_tx_cfg_bypass_en_wd = reg_wdata[0]; + + assign channel_alloc_tx_cfg_auto_flush_en_we = addr_hit[13] & reg_we & !reg_error; + assign channel_alloc_tx_cfg_auto_flush_en_wd = reg_wdata[1]; + + assign channel_alloc_tx_cfg_auto_flush_count_we = addr_hit[13] & reg_we & !reg_error; + assign channel_alloc_tx_cfg_auto_flush_count_wd = reg_wdata[15:8]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_wd = reg_wdata[0]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_wd = reg_wdata[1]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_wd = reg_wdata[2]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_wd = reg_wdata[3]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_wd = reg_wdata[4]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_wd = reg_wdata[5]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_wd = reg_wdata[6]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_wd = reg_wdata[7]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_wd = reg_wdata[8]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_wd = reg_wdata[9]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_wd = reg_wdata[10]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_wd = reg_wdata[11]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_wd = reg_wdata[12]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_wd = reg_wdata[13]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_wd = reg_wdata[14]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_wd = reg_wdata[15]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_wd = reg_wdata[16]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_wd = reg_wdata[17]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_wd = reg_wdata[18]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_wd = reg_wdata[19]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_wd = reg_wdata[20]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_wd = reg_wdata[21]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_wd = reg_wdata[22]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_wd = reg_wdata[23]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_wd = reg_wdata[24]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_wd = reg_wdata[25]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_wd = reg_wdata[26]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_wd = reg_wdata[27]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_wd = reg_wdata[28]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_wd = reg_wdata[29]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_wd = reg_wdata[30]; + + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_we = addr_hit[14] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_wd = reg_wdata[31]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_wd = reg_wdata[0]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_wd = reg_wdata[1]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_wd = reg_wdata[2]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_wd = reg_wdata[3]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_wd = reg_wdata[4]; + + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_we = addr_hit[15] & reg_we & !reg_error; + assign channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_wd = reg_wdata[5]; + + assign channel_alloc_tx_ctrl_clear_we = addr_hit[16] & reg_we & !reg_error; + assign channel_alloc_tx_ctrl_clear_wd = reg_wdata[0]; + + assign channel_alloc_tx_ctrl_flush_we = addr_hit[16] & reg_we & !reg_error; + assign channel_alloc_tx_ctrl_flush_wd = reg_wdata[1]; + + assign channel_alloc_rx_cfg_bypass_en_we = addr_hit[17] & reg_we & !reg_error; + assign channel_alloc_rx_cfg_bypass_en_wd = reg_wdata[0]; + + assign channel_alloc_rx_cfg_auto_flush_en_we = addr_hit[17] & reg_we & !reg_error; + assign channel_alloc_rx_cfg_auto_flush_en_wd = reg_wdata[1]; + + assign channel_alloc_rx_cfg_auto_flush_count_we = addr_hit[17] & reg_we & !reg_error; + assign channel_alloc_rx_cfg_auto_flush_count_wd = reg_wdata[15:8]; + + assign channel_alloc_rx_cfg_sync_en_we = addr_hit[17] & reg_we & !reg_error; + assign channel_alloc_rx_cfg_sync_en_wd = reg_wdata[16]; + + assign channel_alloc_rx_ctrl_we = addr_hit[18] & reg_we & !reg_error; + assign channel_alloc_rx_ctrl_wd = reg_wdata[0]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_wd = reg_wdata[0]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_wd = reg_wdata[1]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_wd = reg_wdata[2]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_wd = reg_wdata[3]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_wd = reg_wdata[4]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_wd = reg_wdata[5]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_wd = reg_wdata[6]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_wd = reg_wdata[7]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_wd = reg_wdata[8]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_wd = reg_wdata[9]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_wd = reg_wdata[10]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_wd = reg_wdata[11]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_wd = reg_wdata[12]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_wd = reg_wdata[13]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_wd = reg_wdata[14]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_wd = reg_wdata[15]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_wd = reg_wdata[16]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_wd = reg_wdata[17]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_wd = reg_wdata[18]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_wd = reg_wdata[19]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_wd = reg_wdata[20]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_wd = reg_wdata[21]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_wd = reg_wdata[22]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_wd = reg_wdata[23]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_wd = reg_wdata[24]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_wd = reg_wdata[25]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_wd = reg_wdata[26]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_wd = reg_wdata[27]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_wd = reg_wdata[28]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_wd = reg_wdata[29]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_wd = reg_wdata[30]; + + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_we = addr_hit[19] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_wd = reg_wdata[31]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_wd = reg_wdata[0]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_wd = reg_wdata[1]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_wd = reg_wdata[2]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_wd = reg_wdata[3]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_wd = reg_wdata[4]; + + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_we = addr_hit[20] & reg_we & !reg_error; + assign channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_wd = reg_wdata[5]; + + assign quadrature_clock_delay_we = addr_hit[21] & reg_we & !reg_error; + assign quadrature_clock_delay_wd = reg_wdata[3:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = ctrl_clk_ena_qs; + reg_rdata_next[1] = ctrl_reset_n_qs; + reg_rdata_next[8] = ctrl_axi_in_isolate_qs; + reg_rdata_next[9] = ctrl_axi_out_isolate_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = isolated_axi_in_qs; + reg_rdata_next[1] = isolated_axi_out_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[5:0] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_0_qs; + reg_rdata_next[1] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_1_qs; + reg_rdata_next[2] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_2_qs; + reg_rdata_next[3] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_3_qs; + reg_rdata_next[4] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_4_qs; + reg_rdata_next[5] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_5_qs; + reg_rdata_next[6] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_6_qs; + reg_rdata_next[7] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_7_qs; + reg_rdata_next[8] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_8_qs; + reg_rdata_next[9] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_9_qs; + reg_rdata_next[10] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_10_qs; + reg_rdata_next[11] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_11_qs; + reg_rdata_next[12] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_12_qs; + reg_rdata_next[13] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_13_qs; + reg_rdata_next[14] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_14_qs; + reg_rdata_next[15] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_15_qs; + reg_rdata_next[16] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_16_qs; + reg_rdata_next[17] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_17_qs; + reg_rdata_next[18] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_18_qs; + reg_rdata_next[19] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_19_qs; + reg_rdata_next[20] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_20_qs; + reg_rdata_next[21] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_21_qs; + reg_rdata_next[22] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_22_qs; + reg_rdata_next[23] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_23_qs; + reg_rdata_next[24] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_24_qs; + reg_rdata_next[25] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_25_qs; + reg_rdata_next[26] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_26_qs; + reg_rdata_next[27] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_27_qs; + reg_rdata_next[28] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_28_qs; + reg_rdata_next[29] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_29_qs; + reg_rdata_next[30] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_30_qs; + reg_rdata_next[31] = raw_mode_in_data_valid_0_raw_mode_in_data_valid_31_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_32_qs; + reg_rdata_next[1] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_33_qs; + reg_rdata_next[2] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_34_qs; + reg_rdata_next[3] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_35_qs; + reg_rdata_next[4] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_36_qs; + reg_rdata_next[5] = raw_mode_in_data_valid_1_raw_mode_in_data_valid_37_qs; + end + + addr_hit[6]: begin + reg_rdata_next[15:0] = raw_mode_in_data_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[8]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + end + + addr_hit[9]: begin + reg_rdata_next[15:0] = '0; + end + + addr_hit[10]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[10:8] = raw_mode_out_data_fifo_ctrl_fill_state_qs; + reg_rdata_next[31] = raw_mode_out_data_fifo_ctrl_is_full_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = raw_mode_out_en_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[13]: begin + reg_rdata_next[0] = channel_alloc_tx_cfg_bypass_en_qs; + reg_rdata_next[1] = channel_alloc_tx_cfg_auto_flush_en_qs; + reg_rdata_next[15:8] = channel_alloc_tx_cfg_auto_flush_count_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_0_qs; + reg_rdata_next[1] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_1_qs; + reg_rdata_next[2] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_2_qs; + reg_rdata_next[3] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_3_qs; + reg_rdata_next[4] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_4_qs; + reg_rdata_next[5] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_5_qs; + reg_rdata_next[6] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_6_qs; + reg_rdata_next[7] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_7_qs; + reg_rdata_next[8] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_8_qs; + reg_rdata_next[9] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_9_qs; + reg_rdata_next[10] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_10_qs; + reg_rdata_next[11] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_11_qs; + reg_rdata_next[12] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_12_qs; + reg_rdata_next[13] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_13_qs; + reg_rdata_next[14] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_14_qs; + reg_rdata_next[15] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_15_qs; + reg_rdata_next[16] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_16_qs; + reg_rdata_next[17] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_17_qs; + reg_rdata_next[18] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_18_qs; + reg_rdata_next[19] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_19_qs; + reg_rdata_next[20] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_20_qs; + reg_rdata_next[21] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_21_qs; + reg_rdata_next[22] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_22_qs; + reg_rdata_next[23] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_23_qs; + reg_rdata_next[24] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_24_qs; + reg_rdata_next[25] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_25_qs; + reg_rdata_next[26] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_26_qs; + reg_rdata_next[27] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_27_qs; + reg_rdata_next[28] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_28_qs; + reg_rdata_next[29] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_29_qs; + reg_rdata_next[30] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_30_qs; + reg_rdata_next[31] = channel_alloc_tx_ch_en_0_channel_alloc_tx_ch_en_31_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_32_qs; + reg_rdata_next[1] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_33_qs; + reg_rdata_next[2] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_34_qs; + reg_rdata_next[3] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_35_qs; + reg_rdata_next[4] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_36_qs; + reg_rdata_next[5] = channel_alloc_tx_ch_en_1_channel_alloc_tx_ch_en_37_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[17]: begin + reg_rdata_next[0] = channel_alloc_rx_cfg_bypass_en_qs; + reg_rdata_next[1] = channel_alloc_rx_cfg_auto_flush_en_qs; + reg_rdata_next[15:8] = channel_alloc_rx_cfg_auto_flush_count_qs; + reg_rdata_next[16] = channel_alloc_rx_cfg_sync_en_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[19]: begin + reg_rdata_next[0] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_0_qs; + reg_rdata_next[1] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_1_qs; + reg_rdata_next[2] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_2_qs; + reg_rdata_next[3] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_3_qs; + reg_rdata_next[4] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_4_qs; + reg_rdata_next[5] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_5_qs; + reg_rdata_next[6] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_6_qs; + reg_rdata_next[7] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_7_qs; + reg_rdata_next[8] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_8_qs; + reg_rdata_next[9] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_9_qs; + reg_rdata_next[10] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_10_qs; + reg_rdata_next[11] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_11_qs; + reg_rdata_next[12] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_12_qs; + reg_rdata_next[13] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_13_qs; + reg_rdata_next[14] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_14_qs; + reg_rdata_next[15] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_15_qs; + reg_rdata_next[16] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_16_qs; + reg_rdata_next[17] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_17_qs; + reg_rdata_next[18] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_18_qs; + reg_rdata_next[19] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_19_qs; + reg_rdata_next[20] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_20_qs; + reg_rdata_next[21] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_21_qs; + reg_rdata_next[22] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_22_qs; + reg_rdata_next[23] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_23_qs; + reg_rdata_next[24] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_24_qs; + reg_rdata_next[25] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_25_qs; + reg_rdata_next[26] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_26_qs; + reg_rdata_next[27] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_27_qs; + reg_rdata_next[28] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_28_qs; + reg_rdata_next[29] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_29_qs; + reg_rdata_next[30] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_30_qs; + reg_rdata_next[31] = channel_alloc_rx_ch_en_0_channel_alloc_rx_ch_en_31_qs; + end + + addr_hit[20]: begin + reg_rdata_next[0] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_32_qs; + reg_rdata_next[1] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_33_qs; + reg_rdata_next[2] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_34_qs; + reg_rdata_next[3] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_35_qs; + reg_rdata_next[4] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_36_qs; + reg_rdata_next[5] = channel_alloc_rx_ch_en_1_channel_alloc_rx_ch_en_37_qs; + end + + addr_hit[21]: begin + reg_rdata_next[3:0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +module serial_link_delay_line_reg_top_intf +#( + parameter int AW = 7, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output serial_link_delay_line_reg_pkg::serial_link_delay_line_reg2hw_t reg2hw, // Write + input serial_link_delay_line_reg_pkg::serial_link_delay_line_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + serial_link_delay_line_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/src/regs/serial_link_single_channel_delay_line.hjson b/src/regs/serial_link_single_channel_delay_line.hjson new file mode 100644 index 0000000..68c2584 --- /dev/null +++ b/src/regs/serial_link_single_channel_delay_line.hjson @@ -0,0 +1,231 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Author: Alessandro Ottaviano + +{ + name: "serial_link_single_channel_delay_line", + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: "32", + param_list: [ + { name: "NumChannels", + desc: "Number of channels", + type: "int", + default: "1", + local: "true" + }, + { name: "Log2NumChannels", + desc: "Number of channels", + type: "int", + default: "1", + local: "true" + }, + { name: "NumBits", + desc: "Number of bits transfered in one clock cycle (2 * NumLanes)", + type: "int", + default: "16", //16 for DDR, 8 for SDR + local: "true" + }, + { name: "Log2MaxClkDiv", + desc: "Number of bits for clock divider counter", + type: "int", + default: "10", + local: "true" + }, + { name: "Log2RawModeTXFifoDepth", + desc: "The depth of the TX FIFO for raw mode operation." + type: "int", + default: "3", + local: "true" + } + ], + + registers: [ + { + name: "CTRL", + desc: "Global clock, isolation and reset control configuration" + swaccess: "rw", + hwaccess: "hro", + // Clock disabled (i.e. gated) by default + fields: [ + { + bits: "0", + name: "clk_ena", + desc: "Clock gate enable for network, link, physical layer. (active-high)", + resval: 0, + }, + { + bits: "1", + name: "reset_n", + resval: 1, + // *Not* held in reset (i.e. signal high) by default. + // Since clock is gated on reset, inner serial link state should *not* change until ungate + desc: "SW controlled synchronous reset. (active-low)" + }, + // All channels isolated by default + { + bits: "8", + name: "axi_in_isolate", + resval: 1, + desc: "Isolate AXI slave in port. (active-high)" + }, + { + bits: "9", + name: "axi_out_isolate", + resval: 1, + desc: "Isolate AXI master out port. (active-high)" + } + ] + }, + { + name: "ISOLATED", + desc: "Isolation status of AXI ports", + swaccess: "ro", + hwaccess: "hwo", + hwqe: "true", + hwext: "true", + // All channels isolated by default + fields: [ + {bits: "0:0", name: "axi_in", resval: 1, desc: "slave in isolation status"}, + {bits: "1:1", name: "axi_out", resval: 1, desc: "master out isolation status"}, + ] + }, + { + name: "RAW_MODE_EN", + desc: "Enables Raw mode", + swaccess: "wo", + hwaccess: "hro", + fields: [ + {bits: "0", resval: 0} + ] + }, + { + name: "RAW_MODE_IN_CH_SEL", + desc: "Receive channel select in RAW mode", + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "Log2NumChannels-1:0", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_IN_DATA_VALID", + desc: "Mask for valid data in RX FIFOs during RAW mode.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "NumChannels-1:0", + } + ] + }, + { + name: "RAW_MODE_IN_DATA", + desc: "Data received by the selected channel in RAW mode", + swaccess: "ro", + hwaccess: "hrw", + hwext: "true", + hwre: "true", + fields: [ + { bits: "NumBits-1:0", + } + ] + }, + { + name: "RAW_MODE_OUT_CH_MASK", + desc: "Selects channels to send out data in RAW mode, '1 corresponds to broadcasting", + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "NumChannels-1:0", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_OUT_DATA_FIFO", + desc: "Data that will be pushed to the RAW mode output FIFO", + swaccess: "wo", + hwaccess: "hro", + hwqe: "true", + fields: [ + { bits: "NumBits-1:0", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_OUT_DATA_FIFO_CTRL", + desc: "Status and control register for the RAW mode data out FIFO", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + fields: [ + { + bits: "0", + name: "clear", + swaccess: "wo", + hwaccess: "hro", + desc: "Clears the raw mode TX FIFO.", + }, + { + bits: "8+Log2RawModeTXFifoDepth-1:8", + name: "fill_state", + swaccess: "ro", + hwaccess: "hwo", + desc: "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent.", + resval: 0 + }, + { + bits: "31", + name: "is_full", + swaccess: "ro", + hwaccess: "hwo", + desc: "If '1' the FIFO is full and does not accept any more items. Any additional write to the data fill register will be ignored until there is sufficient space again.", + resval: 0 + } + ] + }, + { + name: "RAW_MODE_OUT_EN", + desc: "Enable transmission of data currently hold in the output FIFO", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + resval: 0 + } + ] + }, + { + name: "FLOW_CONTROL_FIFO_CLEAR", + desc: "Clears the flow control Fifo", + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "0", + resval: 0 + } + ] + }, + { + name: "QUADRATURE_CLOCK_DELAY", + desc: "Delay to get quadrature clock", + swaccess: "wo", + hwaccess: "hro", + fields: [ + {bits: "4:0", resval: 8} + ] + }, + ] +} diff --git a/src/regs/serial_link_single_channel_delay_line_reg_pkg.sv b/src/regs/serial_link_single_channel_delay_line_reg_pkg.sv new file mode 100644 index 0000000..e5ba826 --- /dev/null +++ b/src/regs/serial_link_single_channel_delay_line_reg_pkg.sv @@ -0,0 +1,187 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package serial_link_single_channel_delay_line_reg_pkg; + + // Param list + parameter int NumChannels = 1; + parameter int Log2NumChannels = 1; + parameter int NumBits = 16; + parameter int Log2MaxClkDiv = 10; + parameter int Log2RawModeTXFifoDepth = 3; + + // Address widths within the block + parameter int BlockAw = 6; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } clk_ena; + struct packed { + logic q; + } reset_n; + struct packed { + logic q; + } axi_in_isolate; + struct packed { + logic q; + } axi_out_isolate; + } serial_link_single_channel_delay_line_reg2hw_ctrl_reg_t; + + typedef struct packed { + logic q; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_en_reg_t; + + typedef struct packed { + logic q; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_in_ch_sel_reg_t; + + typedef struct packed { + logic [15:0] q; + logic re; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_in_data_reg_t; + + typedef struct packed { + logic q; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_out_ch_mask_reg_t; + + typedef struct packed { + logic [15:0] q; + logic qe; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_out_data_fifo_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } clear; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_out_data_fifo_ctrl_reg_t; + + typedef struct packed { + logic q; + } serial_link_single_channel_delay_line_reg2hw_raw_mode_out_en_reg_t; + + typedef struct packed { + logic q; + logic qe; + } serial_link_single_channel_delay_line_reg2hw_flow_control_fifo_clear_reg_t; + + typedef struct packed { + logic [4:0] q; + } serial_link_single_channel_delay_line_reg2hw_quadrature_clock_delay_reg_t; + + typedef struct packed { + struct packed { + logic d; + } axi_in; + struct packed { + logic d; + } axi_out; + } serial_link_single_channel_delay_line_hw2reg_isolated_reg_t; + + typedef struct packed { + logic d; + } serial_link_single_channel_delay_line_hw2reg_raw_mode_in_data_valid_reg_t; + + typedef struct packed { + logic [15:0] d; + } serial_link_single_channel_delay_line_hw2reg_raw_mode_in_data_reg_t; + + typedef struct packed { + struct packed { + logic [2:0] d; + } fill_state; + struct packed { + logic d; + } is_full; + } serial_link_single_channel_delay_line_hw2reg_raw_mode_out_data_fifo_ctrl_reg_t; + + // Register -> HW type + typedef struct packed { + serial_link_single_channel_delay_line_reg2hw_ctrl_reg_t ctrl; // [50:47] + serial_link_single_channel_delay_line_reg2hw_raw_mode_en_reg_t raw_mode_en; // [46:46] + serial_link_single_channel_delay_line_reg2hw_raw_mode_in_ch_sel_reg_t raw_mode_in_ch_sel; // [45:45] + serial_link_single_channel_delay_line_reg2hw_raw_mode_in_data_reg_t raw_mode_in_data; // [44:28] + serial_link_single_channel_delay_line_reg2hw_raw_mode_out_ch_mask_reg_t raw_mode_out_ch_mask; // [27:27] + serial_link_single_channel_delay_line_reg2hw_raw_mode_out_data_fifo_reg_t raw_mode_out_data_fifo; // [26:10] + serial_link_single_channel_delay_line_reg2hw_raw_mode_out_data_fifo_ctrl_reg_t raw_mode_out_data_fifo_ctrl; // [9:8] + serial_link_single_channel_delay_line_reg2hw_raw_mode_out_en_reg_t raw_mode_out_en; // [7:7] + serial_link_single_channel_delay_line_reg2hw_flow_control_fifo_clear_reg_t flow_control_fifo_clear; // [6:5] + serial_link_single_channel_delay_line_reg2hw_quadrature_clock_delay_reg_t quadrature_clock_delay; // [4:0] + } serial_link_single_channel_delay_line_reg2hw_t; + + // HW -> register type + typedef struct packed { + serial_link_single_channel_delay_line_hw2reg_isolated_reg_t isolated; // [22:21] + serial_link_single_channel_delay_line_hw2reg_raw_mode_in_data_valid_reg_t raw_mode_in_data_valid; // [20:20] + serial_link_single_channel_delay_line_hw2reg_raw_mode_in_data_reg_t raw_mode_in_data; // [19:4] + serial_link_single_channel_delay_line_hw2reg_raw_mode_out_data_fifo_ctrl_reg_t raw_mode_out_data_fifo_ctrl; // [3:0] + } serial_link_single_channel_delay_line_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_CTRL_OFFSET = 6'h 0; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED_OFFSET = 6'h 4; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_EN_OFFSET = 6'h 8; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_CH_SEL_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_VALID_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_CH_MASK_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_EN_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_QUADRATURE_CLOCK_DELAY_OFFSET = 6'h 2c; + + // Reset values for hwext registers and their fields + parameter logic [1:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED_RESVAL = 2'h 3; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED_AXI_IN_RESVAL = 1'h 1; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED_AXI_OUT_RESVAL = 1'h 1; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_VALID_RESVAL = 1'h 0; + parameter logic [15:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_RESVAL = 16'h 0; + parameter logic [31:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_RESVAL = 32'h 0; + parameter logic [2:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_FILL_STATE_RESVAL = 3'h 0; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_IS_FULL_RESVAL = 1'h 0; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_RESVAL = 1'h 0; + parameter logic [0:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_FLOW_CONTROL_FIFO_CLEAR_RESVAL = 1'h 0; + + // Register index + typedef enum int { + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_CTRL, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_EN, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_CH_SEL, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_VALID, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_CH_MASK, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_EN, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR, + SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_QUADRATURE_CLOCK_DELAY + } serial_link_single_channel_delay_line_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT [12] = '{ + 4'b 0011, // index[ 0] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_CTRL + 4'b 0001, // index[ 1] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED + 4'b 0001, // index[ 2] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_EN + 4'b 0001, // index[ 3] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_CH_SEL + 4'b 0001, // index[ 4] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_VALID + 4'b 0011, // index[ 5] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA + 4'b 0001, // index[ 6] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_CH_MASK + 4'b 0011, // index[ 7] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO + 4'b 1111, // index[ 8] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL + 4'b 0001, // index[ 9] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_EN + 4'b 0001, // index[10] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR + 4'b 0001 // index[11] SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_QUADRATURE_CLOCK_DELAY + }; + +endpackage + diff --git a/src/regs/serial_link_single_channel_delay_line_reg_top.sv b/src/regs/serial_link_single_channel_delay_line_reg_top.sv new file mode 100644 index 0000000..92d8ffa --- /dev/null +++ b/src/regs/serial_link_single_channel_delay_line_reg_top.sv @@ -0,0 +1,718 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module serial_link_single_channel_delay_line_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 6 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output serial_link_single_channel_delay_line_reg_pkg::serial_link_single_channel_delay_line_reg2hw_t reg2hw, // Write + input serial_link_single_channel_delay_line_reg_pkg::serial_link_single_channel_delay_line_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import serial_link_single_channel_delay_line_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [BlockAw-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic ctrl_clk_ena_qs; + logic ctrl_clk_ena_wd; + logic ctrl_clk_ena_we; + logic ctrl_reset_n_qs; + logic ctrl_reset_n_wd; + logic ctrl_reset_n_we; + logic ctrl_axi_in_isolate_qs; + logic ctrl_axi_in_isolate_wd; + logic ctrl_axi_in_isolate_we; + logic ctrl_axi_out_isolate_qs; + logic ctrl_axi_out_isolate_wd; + logic ctrl_axi_out_isolate_we; + logic isolated_axi_in_qs; + logic isolated_axi_in_re; + logic isolated_axi_out_qs; + logic isolated_axi_out_re; + logic raw_mode_en_wd; + logic raw_mode_en_we; + logic raw_mode_in_ch_sel_wd; + logic raw_mode_in_ch_sel_we; + logic raw_mode_in_data_valid_qs; + logic raw_mode_in_data_valid_re; + logic [15:0] raw_mode_in_data_qs; + logic raw_mode_in_data_re; + logic raw_mode_out_ch_mask_wd; + logic raw_mode_out_ch_mask_we; + logic [15:0] raw_mode_out_data_fifo_wd; + logic raw_mode_out_data_fifo_we; + logic raw_mode_out_data_fifo_ctrl_clear_wd; + logic raw_mode_out_data_fifo_ctrl_clear_we; + logic [2:0] raw_mode_out_data_fifo_ctrl_fill_state_qs; + logic raw_mode_out_data_fifo_ctrl_fill_state_re; + logic raw_mode_out_data_fifo_ctrl_is_full_qs; + logic raw_mode_out_data_fifo_ctrl_is_full_re; + logic raw_mode_out_en_qs; + logic raw_mode_out_en_wd; + logic raw_mode_out_en_we; + logic flow_control_fifo_clear_wd; + logic flow_control_fifo_clear_we; + logic [4:0] quadrature_clock_delay_wd; + logic quadrature_clock_delay_we; + + // Register instances + // R[ctrl]: V(False) + + // F[clk_ena]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_ctrl_clk_ena ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_clk_ena_we), + .wd (ctrl_clk_ena_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.clk_ena.q ), + + // to register interface (read) + .qs (ctrl_clk_ena_qs) + ); + + + // F[reset_n]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_reset_n ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_reset_n_we), + .wd (ctrl_reset_n_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.reset_n.q ), + + // to register interface (read) + .qs (ctrl_reset_n_qs) + ); + + + // F[axi_in_isolate]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_axi_in_isolate ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_axi_in_isolate_we), + .wd (ctrl_axi_in_isolate_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.axi_in_isolate.q ), + + // to register interface (read) + .qs (ctrl_axi_in_isolate_qs) + ); + + + // F[axi_out_isolate]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_ctrl_axi_out_isolate ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ctrl_axi_out_isolate_we), + .wd (ctrl_axi_out_isolate_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl.axi_out_isolate.q ), + + // to register interface (read) + .qs (ctrl_axi_out_isolate_qs) + ); + + + // R[isolated]: V(True) + + // F[axi_in]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_isolated_axi_in ( + .re (isolated_axi_in_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.isolated.axi_in.d), + .qre (), + .qe (), + .q (), + .qs (isolated_axi_in_qs) + ); + + + // F[axi_out]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_isolated_axi_out ( + .re (isolated_axi_out_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.isolated.axi_out.d), + .qre (), + .qe (), + .q (), + .qs (isolated_axi_out_qs) + ); + + + // R[raw_mode_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_en_we), + .wd (raw_mode_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_en.q ), + + .qs () + ); + + + // R[raw_mode_in_ch_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_in_ch_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_in_ch_sel_we), + .wd (raw_mode_in_ch_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_in_ch_sel.q ), + + .qs () + ); + + + // R[raw_mode_in_data_valid]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_in_data_valid ( + .re (raw_mode_in_data_valid_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data_valid.d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_in_data_valid_qs) + ); + + + // R[raw_mode_in_data]: V(True) + + prim_subreg_ext #( + .DW (16) + ) u_raw_mode_in_data ( + .re (raw_mode_in_data_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_in_data.d), + .qre (reg2hw.raw_mode_in_data.re), + .qe (), + .q (reg2hw.raw_mode_in_data.q ), + .qs (raw_mode_in_data_qs) + ); + + + // R[raw_mode_out_ch_mask]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h0) + ) u_raw_mode_out_ch_mask ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_ch_mask_we), + .wd (raw_mode_out_ch_mask_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_ch_mask.q ), + + .qs () + ); + + + // R[raw_mode_out_data_fifo]: V(False) + + prim_subreg #( + .DW (16), + .SWACCESS("WO"), + .RESVAL (16'h0) + ) u_raw_mode_out_data_fifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_data_fifo_we), + .wd (raw_mode_out_data_fifo_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.raw_mode_out_data_fifo.qe), + .q (reg2hw.raw_mode_out_data_fifo.q ), + + .qs () + ); + + + // R[raw_mode_out_data_fifo_ctrl]: V(True) + + // F[clear]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_out_data_fifo_ctrl_clear ( + .re (1'b0), + .we (raw_mode_out_data_fifo_ctrl_clear_we), + .wd (raw_mode_out_data_fifo_ctrl_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.raw_mode_out_data_fifo_ctrl.clear.qe), + .q (reg2hw.raw_mode_out_data_fifo_ctrl.clear.q ), + .qs () + ); + + + // F[fill_state]: 10:8 + prim_subreg_ext #( + .DW (3) + ) u_raw_mode_out_data_fifo_ctrl_fill_state ( + .re (raw_mode_out_data_fifo_ctrl_fill_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_out_data_fifo_ctrl.fill_state.d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_out_data_fifo_ctrl_fill_state_qs) + ); + + + // F[is_full]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_raw_mode_out_data_fifo_ctrl_is_full ( + .re (raw_mode_out_data_fifo_ctrl_is_full_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.raw_mode_out_data_fifo_ctrl.is_full.d), + .qre (), + .qe (), + .q (), + .qs (raw_mode_out_data_fifo_ctrl_is_full_qs) + ); + + + // R[raw_mode_out_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_raw_mode_out_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (raw_mode_out_en_we), + .wd (raw_mode_out_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.raw_mode_out_en.q ), + + // to register interface (read) + .qs (raw_mode_out_en_qs) + ); + + + // R[flow_control_fifo_clear]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_flow_control_fifo_clear ( + .re (1'b0), + .we (flow_control_fifo_clear_we), + .wd (flow_control_fifo_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.flow_control_fifo_clear.qe), + .q (reg2hw.flow_control_fifo_clear.q ), + .qs () + ); + + + // R[quadrature_clock_delay]: V(False) + + prim_subreg #( + .DW (5), + .SWACCESS("WO"), + .RESVAL (5'h8) + ) u_quadrature_clock_delay ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (quadrature_clock_delay_we), + .wd (quadrature_clock_delay_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.quadrature_clock_delay.q ), + + .qs () + ); + + + + + logic [11:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_CTRL_OFFSET); + addr_hit[ 1] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_ISOLATED_OFFSET); + addr_hit[ 2] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_EN_OFFSET); + addr_hit[ 3] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_CH_SEL_OFFSET); + addr_hit[ 4] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_VALID_OFFSET); + addr_hit[ 5] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_IN_DATA_OFFSET); + addr_hit[ 6] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_CH_MASK_OFFSET); + addr_hit[ 7] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_OFFSET); + addr_hit[ 8] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_DATA_FIFO_CTRL_OFFSET); + addr_hit[ 9] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_RAW_MODE_OUT_EN_OFFSET); + addr_hit[10] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_FLOW_CONTROL_FIFO_CLEAR_OFFSET); + addr_hit[11] = (reg_addr == SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_QUADRATURE_CLOCK_DELAY_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(SERIAL_LINK_SINGLE_CHANNEL_DELAY_LINE_PERMIT[11] & ~reg_be))))); + end + + assign ctrl_clk_ena_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_clk_ena_wd = reg_wdata[0]; + + assign ctrl_reset_n_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_reset_n_wd = reg_wdata[1]; + + assign ctrl_axi_in_isolate_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_axi_in_isolate_wd = reg_wdata[8]; + + assign ctrl_axi_out_isolate_we = addr_hit[0] & reg_we & !reg_error; + assign ctrl_axi_out_isolate_wd = reg_wdata[9]; + + assign isolated_axi_in_re = addr_hit[1] & reg_re & !reg_error; + + assign isolated_axi_out_re = addr_hit[1] & reg_re & !reg_error; + + assign raw_mode_en_we = addr_hit[2] & reg_we & !reg_error; + assign raw_mode_en_wd = reg_wdata[0]; + + assign raw_mode_in_ch_sel_we = addr_hit[3] & reg_we & !reg_error; + assign raw_mode_in_ch_sel_wd = reg_wdata[0]; + + assign raw_mode_in_data_valid_re = addr_hit[4] & reg_re & !reg_error; + + assign raw_mode_in_data_re = addr_hit[5] & reg_re & !reg_error; + + assign raw_mode_out_ch_mask_we = addr_hit[6] & reg_we & !reg_error; + assign raw_mode_out_ch_mask_wd = reg_wdata[0]; + + assign raw_mode_out_data_fifo_we = addr_hit[7] & reg_we & !reg_error; + assign raw_mode_out_data_fifo_wd = reg_wdata[15:0]; + + assign raw_mode_out_data_fifo_ctrl_clear_we = addr_hit[8] & reg_we & !reg_error; + assign raw_mode_out_data_fifo_ctrl_clear_wd = reg_wdata[0]; + + assign raw_mode_out_data_fifo_ctrl_fill_state_re = addr_hit[8] & reg_re & !reg_error; + + assign raw_mode_out_data_fifo_ctrl_is_full_re = addr_hit[8] & reg_re & !reg_error; + + assign raw_mode_out_en_we = addr_hit[9] & reg_we & !reg_error; + assign raw_mode_out_en_wd = reg_wdata[0]; + + assign flow_control_fifo_clear_we = addr_hit[10] & reg_we & !reg_error; + assign flow_control_fifo_clear_wd = reg_wdata[0]; + + assign quadrature_clock_delay_we = addr_hit[11] & reg_we & !reg_error; + assign quadrature_clock_delay_wd = reg_wdata[4:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = ctrl_clk_ena_qs; + reg_rdata_next[1] = ctrl_reset_n_qs; + reg_rdata_next[8] = ctrl_axi_in_isolate_qs; + reg_rdata_next[9] = ctrl_axi_out_isolate_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = isolated_axi_in_qs; + reg_rdata_next[1] = isolated_axi_out_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = raw_mode_in_data_valid_qs; + end + + addr_hit[5]: begin + reg_rdata_next[15:0] = raw_mode_in_data_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[7]: begin + reg_rdata_next[15:0] = '0; + end + + addr_hit[8]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[10:8] = raw_mode_out_data_fifo_ctrl_fill_state_qs; + reg_rdata_next[31] = raw_mode_out_data_fifo_ctrl_is_full_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = raw_mode_out_en_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[11]: begin + reg_rdata_next[4:0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +module serial_link_single_channel_delay_line_reg_top_intf +#( + parameter int AW = 6, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output serial_link_single_channel_delay_line_reg_pkg::serial_link_single_channel_delay_line_reg2hw_t reg2hw, // Write + input serial_link_single_channel_delay_line_reg_pkg::serial_link_single_channel_delay_line_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + serial_link_single_channel_delay_line_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/src/serial_link.sv b/src/serial_link.sv index 7841076..cbb84d0 100644 --- a/src/serial_link.sv +++ b/src/serial_link.sv @@ -24,6 +24,9 @@ module serial_link #( parameter int MaxClkDiv = 1024, // Whether to use a register CDC for the configuration registers parameter bit NoRegCdc = 1'b0, + // Whether to use a TX delay line in a channel's PHY. This instantiates one + // delay line per channel + parameter bit UseDelayLine = 1'b0, // The depth of the raw mode FIFO parameter int RawModeFifoDepth = 8, parameter type axi_req_t = logic, @@ -292,29 +295,52 @@ module serial_link #( //////////////////////// for (genvar i = 0; i < NumChannels; i++) begin : gen_phy_channels - serial_link_physical #( - .NumLanes ( NumLanes ), - .FifoDepth ( RawModeFifoDepth ), - .MaxClkDiv ( MaxClkDiv ), - .EnDdr ( EnDdr ), - .phy_data_t ( phy_data_t ) - ) i_serial_link_physical ( - .clk_i ( clk_sl_i ), - .rst_ni ( rst_sl_ni ), - .clk_div_i ( reg2hw.tx_phy_clk_div[i].q ), - .clk_shift_start_i ( reg2hw.tx_phy_clk_start[i].q ), - .clk_shift_end_i ( reg2hw.tx_phy_clk_end[i].q ), - .ddr_rcv_clk_i ( ddr_rcv_clk_i[i] ), - .ddr_rcv_clk_o ( ddr_rcv_clk_o[i] ), - .data_out_i ( alloc2phy_data_out[i] ), - .data_out_valid_i ( alloc2phy_data_out_valid[i] ), - .data_out_ready_o ( phy2alloc_data_out_ready[i] ), - .data_in_o ( phy2alloc_data_in[i] ), - .data_in_valid_o ( phy2alloc_data_in_valid[i] ), - .data_in_ready_i ( alloc2phy_data_in_ready[i] ), - .ddr_i ( ddr_i[i] ), - .ddr_o ( ddr_o[i] ) - ); + if (UseDelayLine) begin : gen_phy_with_delay_lines + serial_link_physical_delay_line #( + .NumLanes ( NumLanes ), + .FifoDepth ( RawModeFifoDepth ), + .EnDdr ( EnDdr ), + .phy_data_t ( phy_data_t ) + ) i_serial_link_physical_delay_line ( + .clk_i ( clk_sl_i ), + .rst_ni ( rst_sl_ni ), + .clk_delay_i ( reg2hw.quadrature_clk_delay ), + .ddr_rcv_clk_i ( ddr_rcv_clk_i[i] ), + .ddr_rcv_clk_o ( ddr_rcv_clk_o[i] ), + .data_out_i ( alloc2phy_data_out[i] ), + .data_out_valid_i ( alloc2phy_data_out_valid[i] ), + .data_out_ready_o ( phy2alloc_data_out_ready[i] ), + .data_in_o ( phy2alloc_data_in[i] ), + .data_in_valid_o ( phy2alloc_data_in_valid[i] ), + .data_in_ready_i ( alloc2phy_data_in_ready[i] ), + .ddr_i ( ddr_i[i] ), + .ddr_o ( ddr_o[i] ) + ); + end else begin : gen_phy_with_clk_divider + serial_link_physical #( + .NumLanes ( NumLanes ), + .FifoDepth ( RawModeFifoDepth ), + .MaxClkDiv ( MaxClkDiv ), + .EnDdr ( EnDdr ), + .phy_data_t ( phy_data_t ) + ) i_serial_link_physical ( + .clk_i ( clk_sl_i ), + .rst_ni ( rst_sl_ni ), + .clk_div_i ( reg2hw.tx_phy_clk_div[i].q ), + .clk_shift_start_i ( reg2hw.tx_phy_clk_start[i].q ), + .clk_shift_end_i ( reg2hw.tx_phy_clk_end[i].q ), + .ddr_rcv_clk_i ( ddr_rcv_clk_i[i] ), + .ddr_rcv_clk_o ( ddr_rcv_clk_o[i] ), + .data_out_i ( alloc2phy_data_out[i] ), + .data_out_valid_i ( alloc2phy_data_out_valid[i] ), + .data_out_ready_o ( phy2alloc_data_out_ready[i] ), + .data_in_o ( phy2alloc_data_in[i] ), + .data_in_valid_o ( phy2alloc_data_in_valid[i] ), + .data_in_ready_i ( alloc2phy_data_in_ready[i] ), + .ddr_i ( ddr_i[i] ), + .ddr_o ( ddr_o[i] ) + ); + end end ///////////////////////////////// @@ -342,31 +368,61 @@ module serial_link #( end if (NumChannels == 1) begin : gen_single_channel_cfg_regs - serial_link_single_channel_reg_top #( - .reg_req_t (cfg_req_t), - .reg_rsp_t (cfg_rsp_t) - ) i_serial_link_reg_top ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .reg_req_i ( cfg_req ), - .reg_rsp_o ( cfg_rsp ), - .reg2hw ( reg2hw ), - .hw2reg ( hw2reg ), - .devmode_i ( testmode_i ) - ); + if (UseDelayLine) begin : gen_delay_line + serial_link_single_channel_delay_line_reg_top #( + .reg_req_t (cfg_req_t), + .reg_rsp_t (cfg_rsp_t) + ) i_serial_link_reg_top ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .reg_req_i ( cfg_req ), + .reg_rsp_o ( cfg_rsp ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .devmode_i ( testmode_i ) + ); + end else begin : gen_no_delay_line + serial_link_single_channel_reg_top #( + .reg_req_t (cfg_req_t), + .reg_rsp_t (cfg_rsp_t) + ) i_serial_link_reg_top ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .reg_req_i ( cfg_req ), + .reg_rsp_o ( cfg_rsp ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .devmode_i ( testmode_i ) + ); + end end else begin : gen_multi_channel_cfg_regs - serial_link_reg_top #( - .reg_req_t (cfg_req_t), - .reg_rsp_t (cfg_rsp_t) - ) i_serial_link_reg_top ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .reg_req_i ( cfg_req ), - .reg_rsp_o ( cfg_rsp ), - .reg2hw ( reg2hw ), - .hw2reg ( hw2reg ), - .devmode_i ( testmode_i ) - ); + if (UseDelayLine) begin : gen_delay_line + serial_link_delay_line_reg_top #( + .reg_req_t (cfg_req_t), + .reg_rsp_t (cfg_rsp_t) + ) i_serial_link_reg_top ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .reg_req_i ( cfg_req ), + .reg_rsp_o ( cfg_rsp ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .devmode_i ( testmode_i ) + ); + end else begin : gen_no_delay_line + serial_link_reg_top #( + .reg_req_t (cfg_req_t), + .reg_rsp_t (cfg_rsp_t) + ) i_serial_link_reg_top ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .reg_req_i ( cfg_req ), + .reg_rsp_o ( cfg_rsp ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .devmode_i ( testmode_i ) + ); + end end assign clk_ena_o = reg2hw.ctrl.clk_ena.q; diff --git a/src/serial_link_occamy_wrapper.sv b/src/serial_link_occamy_wrapper.sv index 85fe5c5..109ef51 100644 --- a/src/serial_link_occamy_wrapper.sv +++ b/src/serial_link_occamy_wrapper.sv @@ -123,8 +123,10 @@ module serial_link_occamy_wrapper #( .reg2hw_t ( serial_link_reg_pkg::serial_link_reg2hw_t ), .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .NumCredits ( NumCredits ), .MaxClkDiv ( MaxClkDiv ), - .EnDdr ( EnDdr ) + .UseDelayLine ( UseDelayLine ) ) i_serial_link ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -163,8 +165,10 @@ module serial_link_occamy_wrapper #( .reg2hw_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ), .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .NumCredits ( NumCredits ), .MaxClkDiv ( MaxClkDiv ), - .EnDdr ( EnDdr ) + .UseDelayLine ( UseDelayLine ) ) i_serial_link ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/src/serial_link_physical_delay_line.sv b/src/serial_link_physical_delay_line.sv new file mode 100644 index 0000000..fa570ab --- /dev/null +++ b/src/serial_link_physical_delay_line.sv @@ -0,0 +1,216 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Alessandro Ottaviano + + +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + +// Implements a single TX channel which forwards the source-synchronous clock +module serial_link_physical_delay_line_tx #( + parameter int NumLanes = 8, + parameter bit EnDdr = 1'b1, + parameter type phy_data_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic clk_delay_i, + input phy_data_t data_out_i, + input logic data_out_valid_i, + output logic data_out_ready_o, + output logic ddr_rcv_clk_o, + output logic [NumLanes-1:0] ddr_o +); + + logic [NumLanes*2-1:0] data_out_q; + + // Valid is always set, but src_clk is clock gated + assign data_out_ready_o = data_out_valid_i; + + /////////////////////////////////////// + // CLOCK DIVIDER + PHASE SHIFTER // + /////////////////////////////////////// + + logic clk90, clk270; + + tc_clk_gating #( + .IS_FUNCTIONAL(1) + ) i_clk_gate ( + .clk_i, + .en_i (data_out_valid_i), + .test_en_i ('0), + .clk_o (clk_gate_out) + ); + + // Shift by 270deg = 90deg + inverter to sample data in the eye's center + configurable_delay #( + .NUM_STEPS (16) + ) i_delay90 ( + .clk_i (clk_gate_out), + `ifndef TARGET_ASIC + .enable_i (1'b1), + `endif + .delay_i(clk_delay_i), + .clk_o (clk90) + ); + + // Inverting clk90 <=> clk270 + tc_clk_inverter i_tc_clk_inverter_clk_270 ( + .clk_i(clk90), + .clk_o(clk270) + ); + + // assign output clock + assign ddr_rcv_clk_o = clk270; + + ///////////////// + // DDR OUT // + ///////////////// + `FF(data_out_q, data_out_i, '0, clk_i, rst_ni) + + if (EnDdr) begin : gen_ddr_mode + for (genvar i = 0; i < NumLanes; i++) begin + tc_clk_mux2 i_serial_link_physical_tx_tc_clk_mux2 ( + .clk0_i (data_out_q[NumLanes+i]), + .clk1_i (data_out_q[i]), + .clk_sel_i(clk_i), + .clk_o (ddr_o[i]) + ); + end + end else begin : gen_sdr_mode + assign ddr_o = data_out_q; + end + +endmodule + +// Impelements a single RX channel which samples the data with the received clock +// Synchronizes the data with the System clock with a CDC +module serial_link_physical_delay_line_rx #( + parameter int NumLanes = 8, + parameter int FifoDepth = 8, + parameter int CdcSyncStages = 2, + parameter bit EnDdr = 1'b1, + parameter type phy_data_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic ddr_rcv_clk_i, + output phy_data_t data_in_o, + output logic data_in_valid_o, + input logic data_in_ready_i, + input logic [NumLanes-1:0] ddr_i +); + + phy_data_t data_in; + logic [NumLanes-1:0] ddr_q; + + /////////////////////////////// + // CLOCK DOMAIN CROSSING // + /////////////////////////////// + + cdc_fifo_gray #( + .T ( phy_data_t ), + .LOG_DEPTH ( $clog2(FifoDepth) + CdcSyncStages ), + .SYNC_STAGES ( CdcSyncStages ) + ) i_cdc_in ( + .src_clk_i ( ddr_rcv_clk_i ), + .src_rst_ni ( rst_ni ), + .src_data_i ( data_in ), + .src_valid_i ( 1'b1 ), + .src_ready_o ( ), + + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_data_o ( data_in_o ), + .dst_valid_o ( data_in_valid_o ), + .dst_ready_i ( data_in_ready_i ) + ); + + // TODO: Fix assertion during reset + // `ASSERT(CdcRxFifoFull, !(i_cdc_in.src_valid_i & ~i_cdc_in.src_ready_o), ddr_rcv_clk_i, !rst_ni) + + //////////////// + // DDR IN // + //////////////// + if (EnDdr) begin : gen_ddr_mode + always_ff @(negedge ddr_rcv_clk_i, negedge rst_ni) begin + if (!rst_ni) begin + ddr_q <= 0; + end else begin + ddr_q <= ddr_i; + end + end + assign data_in = {ddr_i, ddr_q}; + end else begin : gen_sdr_mode + assign data_in = ddr_i; + end + +endmodule + +// Implements the Physical Layer of the Serial Link +// The number of Channels and Lanes per Channel is parametrizable +module serial_link_physical_delay_line #( + // Number of Wires in one channel + parameter int NumLanes = 8, + // Fifo Depth of CDC, dependent on + // Num Credit for Flow control + parameter int FifoDepth = 8, + // Enable DDR mode + parameter bit EnDdr = 1'b1, + // Data input type of the PHY + parameter type phy_data_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic clk_delay_i, + input logic ddr_rcv_clk_i, + output logic ddr_rcv_clk_o, + input logic [NumLanes*2-1:0] data_out_i, + input logic data_out_valid_i, + output logic data_out_ready_o, + output logic [NumLanes*2-1:0] data_in_o, + output logic data_in_valid_o, + input logic data_in_ready_i, + input logic [NumLanes-1:0] ddr_i, + output logic [NumLanes-1:0] ddr_o +); + + //////////////// + // PHY TX // + //////////////// + serial_link_physical_delay_line_tx #( + .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .phy_data_t ( phy_data_t ) + ) i_serial_link_physical_tx ( + .rst_ni, + .clk_i, + .clk_delay_i, + .data_out_i, + .data_out_valid_i, + .data_out_ready_o, + .ddr_rcv_clk_o, + .ddr_o + ); + + //////////////// + // PHY RX // + //////////////// + serial_link_physical_delay_line_rx #( + .NumLanes ( NumLanes ), + .FifoDepth ( FifoDepth ), + .EnDdr ( EnDdr ), + .phy_data_t ( phy_data_t ) + ) i_serial_link_physical_rx ( + .clk_i, + .rst_ni, + .ddr_rcv_clk_i, + .data_in_o, + .data_in_valid_o, + .data_in_ready_i, + .ddr_i + ); + +endmodule diff --git a/test/tb_axi_serial_link.sv b/test/tb_axi_serial_link.sv index 8edc41d..77abbba 100644 --- a/test/tb_axi_serial_link.sv +++ b/test/tb_axi_serial_link.sv @@ -8,7 +8,8 @@ module tb_axi_serial_link #( parameter int unsigned NumChannels = 1, parameter int unsigned NumLanes = 8, - parameter bit EnDdr = 1'b1 + parameter bit EnDdr = 1'b1, + parameter bit UseDelayLine = 1'b0 ); `include "axi/assign.svh" @@ -118,7 +119,8 @@ module tb_axi_serial_link #( .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), .MaxClkDiv ( MaxClkDiv ), - .EnDdr ( EnDdr ) + .EnDdr ( EnDdr ), + .UseDelayLine ( UseDelayLine ) ) i_serial_link_1 ( .clk_i ( clk_1 ), .rst_ni ( rst_1_n ), @@ -151,7 +153,8 @@ module tb_axi_serial_link #( .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), .MaxClkDiv ( MaxClkDiv ), - .EnDdr ( EnDdr ) + .EnDdr ( EnDdr ), + .UseDelayLine ( UseDelayLine ) ) i_serial_link_2 ( .clk_i ( clk_2 ), .rst_ni ( rst_2_n ), diff --git a/test/tb_ch_calib_serial_link.sv b/test/tb_ch_calib_serial_link.sv index 9e977b1..cd4bb5d 100644 --- a/test/tb_ch_calib_serial_link.sv +++ b/test/tb_ch_calib_serial_link.sv @@ -8,7 +8,8 @@ module tb_ch_calib_serial_link #( parameter int unsigned NumChannels = 38, parameter int unsigned NumLanes = 8, - parameter bit EnDdr = 1'b1 + parameter bit EnDdr = 1'b1, + parameter bit UseDelayLine = 1'b0 ); `include "axi/assign.svh" @@ -120,7 +121,8 @@ module tb_ch_calib_serial_link #( .cfg_rsp_t ( cfg_rsp_t ), .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), - .MaxClkDiv ( MaxClkDiv ) + .MaxClkDiv ( MaxClkDiv ), + .UseDelayLine ( UseDelayLine ) ) i_serial_link_1 ( .clk_i ( clk_1 ), .rst_ni ( rst_1_n ), @@ -153,7 +155,8 @@ module tb_ch_calib_serial_link #( .cfg_rsp_t ( cfg_rsp_t ), .NumChannels ( NumChannels ), .NumLanes ( NumLanes ), - .MaxClkDiv ( MaxClkDiv ) + .MaxClkDiv ( MaxClkDiv ), + .UseDelayLine ( UseDelayLine ) ) i_serial_link_2 ( .clk_i ( clk_2 ), .rst_ni ( rst_2_n ), From 8af222270f9d502cdb703b556e59df91a4548e9e Mon Sep 17 00:00:00 2001 From: aottaviano Date: Fri, 7 Feb 2025 13:39:33 +0100 Subject: [PATCH 2/3] Add generic wrapper --- Bender.yml | 5 +- src/serial_link_occamy_wrapper.sv | 128 +++++++++------------------ src/serial_link_wrapper.sv | 138 ++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+), 87 deletions(-) create mode 100644 src/serial_link_wrapper.sv diff --git a/Bender.yml b/Bender.yml index e3e69d6..63e91d3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -45,9 +45,12 @@ sources: - src/serial_link_physical.sv - src/serial_link_physical_delay_line.sv - # Serial Link Wrapper + # Serial Link top level - src/serial_link.sv + # Serial Link wrapper for single-channel/multi-channel selection + - src/serial_link_wrapper.sv + # Wrapper for Occamy - src/serial_link_occamy_wrapper.sv diff --git a/src/serial_link_occamy_wrapper.sv b/src/serial_link_occamy_wrapper.sv index 109ef51..10122d2 100644 --- a/src/serial_link_occamy_wrapper.sv +++ b/src/serial_link_occamy_wrapper.sv @@ -19,7 +19,9 @@ module serial_link_occamy_wrapper #( parameter int NumChannels = 1, parameter int NumLanes = 4, parameter int MaxClkDiv = 32, - parameter bit EnDdr = 1'b1 + parameter bit EnDdr = 1'b1, + parameter int NumCredits = 8, + parameter bit UseDelayLine = 1'b0 ) ( input logic clk_i, input logic rst_ni, @@ -108,90 +110,44 @@ module serial_link_occamy_wrapper #( .isolated_o ( isolated[1] ) ); - if (NumChannels > 1) begin : gen_multi_channel_serial_link - serial_link #( - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .cfg_req_t ( cfg_req_t ), - .cfg_rsp_t ( cfg_rsp_t ), - .hw2reg_t ( serial_link_reg_pkg::serial_link_hw2reg_t ), - .reg2hw_t ( serial_link_reg_pkg::serial_link_reg2hw_t ), - .NumChannels ( NumChannels ), - .NumLanes ( NumLanes ), - .EnDdr ( EnDdr ), - .NumCredits ( NumCredits ), - .MaxClkDiv ( MaxClkDiv ), - .UseDelayLine ( UseDelayLine ) - ) i_serial_link ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clk_sl_i ( clk_serial_link ), - .rst_sl_ni ( rst_serial_link_n ), - .clk_reg_i ( clk_reg_i ), - .rst_reg_ni ( rst_reg_ni ), - .testmode_i ( 1'b0 ), - .axi_in_req_i ( axi_in_req ), - .axi_in_rsp_o ( axi_in_rsp ), - .axi_out_req_o ( axi_out_req ), - .axi_out_rsp_i ( axi_out_rsp ), - .cfg_req_i ( cfg_req_i ), - .cfg_rsp_o ( cfg_rsp_o ), - .ddr_rcv_clk_i ( ddr_rcv_clk_i ), - .ddr_rcv_clk_o ( ddr_rcv_clk_o ), - .ddr_i ( ddr_i ), - .ddr_o ( ddr_o ), - .isolated_i ( isolated ), - .isolate_o ( isolate ), - .clk_ena_o ( clk_ena ), - .reset_no ( reset_n ) - ); - end else begin : gen_single_channel_serial_link - serial_link #( - .axi_req_t ( axi_req_t ), - .axi_rsp_t ( axi_rsp_t ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .cfg_req_t ( cfg_req_t ), - .cfg_rsp_t ( cfg_rsp_t ), - .hw2reg_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t ), - .reg2hw_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ), - .NumChannels ( NumChannels ), - .NumLanes ( NumLanes ), - .EnDdr ( EnDdr ), - .NumCredits ( NumCredits ), - .MaxClkDiv ( MaxClkDiv ), - .UseDelayLine ( UseDelayLine ) - ) i_serial_link ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clk_sl_i ( clk_serial_link ), - .rst_sl_ni ( rst_serial_link_n ), - .clk_reg_i ( clk_reg_i ), - .rst_reg_ni ( rst_reg_ni ), - .testmode_i ( 1'b0 ), - .axi_in_req_i ( axi_in_req ), - .axi_in_rsp_o ( axi_in_rsp ), - .axi_out_req_o ( axi_out_req ), - .axi_out_rsp_i ( axi_out_rsp ), - .cfg_req_i ( cfg_req_i ), - .cfg_rsp_o ( cfg_rsp_o ), - .ddr_rcv_clk_i ( ddr_rcv_clk_i ), - .ddr_rcv_clk_o ( ddr_rcv_clk_o ), - .ddr_i ( ddr_i ), - .ddr_o ( ddr_o ), - .isolated_i ( isolated ), - .isolate_o ( isolate ), - .clk_ena_o ( clk_ena ), - .reset_no ( reset_n ) - ); - end + serial_link_wrapper #( + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .cfg_req_t ( cfg_req_t ), + .cfg_rsp_t ( cfg_rsp_t ), + .NumChannels ( NumChannels ), + .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .NumCredits ( NumCredits ), + .MaxClkDiv ( MaxClkDiv ), + .UseDelayLine ( UseDelayLine ) + ) i_serial_link ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clk_sl_i ( clk_serial_link ), + .rst_sl_ni ( rst_serial_link_n ), + .clk_reg_i ( clk_reg_i ), + .rst_reg_ni ( rst_reg_ni ), + .testmode_i ( 1'b0 ), + .axi_in_req_i ( axi_in_req ), + .axi_in_rsp_o ( axi_in_rsp ), + .axi_out_req_o ( axi_out_req ), + .axi_out_rsp_i ( axi_out_rsp ), + .cfg_req_i ( cfg_req_i ), + .cfg_rsp_o ( cfg_rsp_o ), + .ddr_rcv_clk_i ( ddr_rcv_clk_i ), + .ddr_rcv_clk_o ( ddr_rcv_clk_o ), + .ddr_i ( ddr_i ), + .ddr_o ( ddr_o ), + .isolated_i ( isolated ), + .isolate_o ( isolate ), + .clk_ena_o ( clk_ena ), + .reset_no ( reset_n ) + ); endmodule diff --git a/src/serial_link_wrapper.sv b/src/serial_link_wrapper.sv new file mode 100644 index 0000000..8c7fbf7 --- /dev/null +++ b/src/serial_link_wrapper.sv @@ -0,0 +1,138 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Alessandro Ottaviano + +/// A wrapper around the Serial Link intended to enable single and multi-channel +/// configurations +module serial_link_wrapper #( + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type aw_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type cfg_req_t = logic, + parameter type cfg_rsp_t = logic, + parameter int NumChannels = 1, + parameter int NumLanes = 4, + parameter bit EnDdr = 1'b1, + parameter int NumCredits = 8, + parameter int MaxClkDiv = 32, + parameter bit UseDelayLine = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + input logic clk_sl_i, + input logic rst_sl_ni, + input logic clk_reg_i, + input logic rst_reg_ni, + input logic testmode_i, + input axi_req_t axi_in_req_i, + output axi_rsp_t axi_in_rsp_o, + output axi_req_t axi_out_req_o, + input axi_rsp_t axi_out_rsp_i, + input cfg_req_t cfg_req_i, + output cfg_rsp_t cfg_rsp_o, + input logic [NumChannels-1:0] ddr_rcv_clk_i, + output logic [NumChannels-1:0] ddr_rcv_clk_o, + input logic [NumChannels-1:0][NumLanes-1:0] ddr_i, + output logic [NumChannels-1:0][NumLanes-1:0] ddr_o, + // AXI isolation signals (in/out), if not used tie to 0 + input logic [1:0] isolated_i, + output logic [1:0] isolate_o, + // Clock gate register + output logic clk_ena_o, + // synch-reset register + output logic reset_no +); + + if (NumChannels > 1) begin : gen_multi_channel_serial_link + serial_link #( + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .cfg_req_t ( cfg_req_t ), + .cfg_rsp_t ( cfg_rsp_t ), + .hw2reg_t ( serial_link_reg_pkg::serial_link_hw2reg_t ), + .reg2hw_t ( serial_link_reg_pkg::serial_link_reg2hw_t ), + .NumChannels ( NumChannels ), + .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .NumCredits ( NumCredits ), + .MaxClkDiv ( MaxClkDiv ), + .UseDelayLine ( UseDelayLine ) + ) i_serial_link ( + .clk_i, + .rst_ni, + .clk_sl_i, + .rst_sl_ni, + .clk_reg_i, + .rst_reg_ni, + .testmode_i, + .axi_in_req_i, + .axi_in_rsp_o, + .axi_out_req_o, + .axi_out_rsp_i, + .cfg_req_i, + .cfg_rsp_o, + .ddr_rcv_clk_i, + .ddr_rcv_clk_o, + .ddr_i, + .ddr_o, + .isolated_i, + .isolate_o, + .clk_ena_o, + .reset_no + ); + end else begin : gen_single_channel_serial_link + serial_link #( + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_rsp_t ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .cfg_req_t ( cfg_req_t ), + .cfg_rsp_t ( cfg_rsp_t ), + .hw2reg_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t ), + .reg2hw_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ), + .NumChannels ( NumChannels ), + .NumLanes ( NumLanes ), + .EnDdr ( EnDdr ), + .NumCredits ( NumCredits ), + .MaxClkDiv ( MaxClkDiv ), + .UseDelayLine ( UseDelayLine ) + ) i_serial_link ( + .clk_i, + .rst_ni, + .clk_sl_i, + .rst_sl_ni, + .clk_reg_i, + .rst_reg_ni, + .testmode_i, + .axi_in_req_i, + .axi_in_rsp_o, + .axi_out_req_o, + .axi_out_rsp_i, + .cfg_req_i, + .cfg_rsp_o, + .ddr_rcv_clk_i, + .ddr_rcv_clk_o, + .ddr_i, + .ddr_o, + .isolated_i, + .isolate_o, + .clk_ena_o, + .reset_no + ); + end + +endmodule From 62d6e9732b7d65fd40f7443d3ff4a9ea67b7e6ea Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 14 Jun 2025 15:27:04 +0200 Subject: [PATCH 3/3] treewide: Do not always compile slink standalone testbenches * Some testbenches like tb_ch_calib_serial_link depend on a specific multi-channel configuration. --- Bender.yml | 10 +++++----- Makefile | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.yml b/Bender.yml index 63e91d3..88b9a81 100644 --- a/Bender.yml +++ b/Bender.yml @@ -58,19 +58,19 @@ sources: files: - src/serial_link_synth_wrapper.sv - - target: any(simulation, test) + - target: slink_test files: - test/axi_channel_compare.sv - - - target: test - files: - - models/configurable_delay.behav.sv - test/tb_axi_serial_link.sv - test/tb_ch_calib_serial_link.sv - test/tb_stream_chopper.sv - test/tb_stream_chopper_dechopper.sv - test/tb_channel_allocator.sv + - target: any(test, simulation) + files: + - models/configurable_delay.behav.sv + - target: fpga files: - models/configurable_delay.fpga.sv diff --git a/Makefile b/Makefile index ebed482..0e3045e 100644 --- a/Makefile +++ b/Makefile @@ -51,7 +51,7 @@ update-regs: src/regs/*.hjson TB_DUT ?= tb_axi_serial_link -BENDER_FLAGS := -t test -t simulation +BENDER_FLAGS := -t slink_test -t simulation VLOG_FLAGS += -suppress vlog-2583 VLOG_FLAGS += -suppress vlog-13314