From 2e8745812d32490628d2f636bcd2c22c4875b696 Mon Sep 17 00:00:00 2001 From: PengchengYang-xdu <24241214835@stu.xidian.edu.cn> Date: Tue, 13 Jan 2026 10:34:05 +0800 Subject: [PATCH] Fix: fix tdo io direction from input to inout --- target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v b/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v index 607ca954..874f20b0 100644 --- a/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v +++ b/target/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v @@ -70,7 +70,7 @@ module xilinx_pulpissimo ( inout wire pad_jtag_tck, inout wire pad_jtag_tdi, - input wire pad_jtag_tdo, + inout wire pad_jtag_tdo, inout wire pad_jtag_tms //input wire pad_jtag_trst );