From fac1a54c31e0b61c48b9436dea09943db5b081be Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Tue, 12 Feb 2019 19:54:58 +0100 Subject: [PATCH 1/2] Aligned to changes in Vincent Vega --- rtl/low_latency_interco/ArbitrationTree.sv | 18 +- rtl/low_latency_interco/ResponseTree.sv | 4 +- .../AddressDecoder_PE_Req.sv | 38 ++- rtl/peripheral_interco/ArbitrationTree_PE.sv | 227 +++++++++--------- rtl/peripheral_interco/RequestBlock2CH_PE.sv | 24 +- rtl/peripheral_interco/ResponseBlock_PE.sv | 52 +++- rtl/peripheral_interco/ResponseTree_PE.sv | 66 ++--- rtl/peripheral_interco/XBAR_PE.sv | 87 +++---- 8 files changed, 290 insertions(+), 226 deletions(-) diff --git a/rtl/low_latency_interco/ArbitrationTree.sv b/rtl/low_latency_interco/ArbitrationTree.sv index 293dd33..a205615 100644 --- a/rtl/low_latency_interco/ArbitrationTree.sv +++ b/rtl/low_latency_interco/ArbitrationTree.sv @@ -154,19 +154,19 @@ module ArbitrationTree //// ---------------------------------------------------------------------- //// //// ------- REQ ARBITRATION TREE WIRES ----------- //// //// ---------------------------------------------------------------------- //// - logic [DATA_WIDTH-1:0] data_wdata_LEVEL[N_WIRE-1:0]; - logic [ADDR_WIDTH-1:0] data_add_LEVEL[N_WIRE-1:0]; - logic data_req_LEVEL[N_WIRE-1:0]; - logic data_wen_LEVEL[N_WIRE-1:0]; - logic [ID_WIDTH-1:0] data_ID_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_wdata_LEVEL; + logic [N_WIRE-1:0][ADDR_WIDTH-1:0] data_add_LEVEL; + logic [N_WIRE-1:0] data_req_LEVEL; + logic [N_WIRE-1:0] data_wen_LEVEL; + logic [N_WIRE-1:0][ID_WIDTH-1:0] data_ID_LEVEL; - logic [LOG_MASTER-1:0] ID_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0][LOG_MASTER-1:0] ID_LEVEL; - logic [BE_WIDTH-1:0] data_be_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0][BE_WIDTH-1:0] data_be_LEVEL; `ifdef GNT_BASED_FC - logic data_gnt_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0] data_gnt_LEVEL; `else - logic data_stall_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0] data_stall_LEVEL; `endif diff --git a/rtl/low_latency_interco/ResponseTree.sv b/rtl/low_latency_interco/ResponseTree.sv index 5c0ed5b..a3f4415 100644 --- a/rtl/low_latency_interco/ResponseTree.sv +++ b/rtl/low_latency_interco/ResponseTree.sv @@ -67,8 +67,8 @@ module ResponseTree generate - logic [DATA_WIDTH-1:0] data_r_rdata_LEVEL[N_WIRE-1:0]; - logic data_r_valid_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_r_rdata_LEVEL; + logic [N_WIRE-1:0] data_r_valid_LEVEL; for(j=0; j < LOG_SLAVE; j++) // Iteration for the number of the stages minus one begin : STAGE diff --git a/rtl/peripheral_interco/AddressDecoder_PE_Req.sv b/rtl/peripheral_interco/AddressDecoder_PE_Req.sv index 88f6bae..c6628c3 100644 --- a/rtl/peripheral_interco/AddressDecoder_PE_Req.sv +++ b/rtl/peripheral_interco/AddressDecoder_PE_Req.sv @@ -33,6 +33,7 @@ // Revision: // // Revision v0.1 - File Created // // Revision v0.2 - Code Restyling (19/02/2015) // +// v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE // // // // Additional Comments: // // // @@ -42,7 +43,7 @@ //////////////////////////////////////////////////////////////////////////////// `include "parameters.v" -`include "pulp_soc_defines.sv" +`include "ulpsoc_defines.sv" module AddressDecoder_PE_Req #( @@ -96,22 +97,37 @@ module AddressDecoder_PE_Req `else if( ( data_add_i[31:20] >= PE_START ) && ( data_add_i[31:20] < PE_END ) ) `endif - ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB]; - else - ROUTING_ADDR = '1; + ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB]; + else + ROUTING_ADDR = '1; end - + always_comb begin : Combinational_ADDR_DEC_REQ //DEFAULT VALUES data_req_o = '0; + // Apply the rigth value - data_req_o[ROUTING_ADDR] = data_req_i; - `ifdef GNT_BASED_FC - data_gnt_o = data_gnt_i[ROUTING_ADDR]; - `else - data_stall_o = data_stall_i[ROUTING_ADDR]; - `endif + if(ROUTING_ADDR >= N_SLAVE-1) + begin + data_req_o[N_SLAVE-1] = data_req_i; + + `ifdef GNT_BASED_FC + data_gnt_o = data_gnt_i[N_SLAVE-1]; + `else + data_stall_o = data_stall_i[N_SLAVE-1]; + `endif + + end + else + begin + data_req_o[ROUTING_ADDR] = data_req_i; + `ifdef GNT_BASED_FC + data_gnt_o = data_gnt_i[ROUTING_ADDR]; + `else + data_stall_o = data_stall_i[ROUTING_ADDR]; + `endif + end end endmodule diff --git a/rtl/peripheral_interco/ArbitrationTree_PE.sv b/rtl/peripheral_interco/ArbitrationTree_PE.sv index 3b56ac9..492f379 100644 --- a/rtl/peripheral_interco/ArbitrationTree_PE.sv +++ b/rtl/peripheral_interco/ArbitrationTree_PE.sv @@ -36,6 +36,7 @@ // Revision: // // Revision v0.1 - File Created // // Revision v0.2 - Code Restyling (19/02/2015) // +// Revision v0.3 - Improved identation (19/04/2018) // // // // Additional Comments: // // // @@ -108,36 +109,36 @@ module ArbitrationTree_PE ( .RR_FLAG(RR_FLAG), // LEFT SIDE" - .data_wdata0_i(data_wdata_i[0]), - .data_wdata1_i(data_wdata_i[1]), - .data_add0_i(data_add_i[0]), - .data_add1_i(data_add_i[1]), - .data_req0_i(data_req_i[0]), - .data_req1_i(data_req_i[1]), - .data_wen0_i(data_wen_i[0]), - .data_wen1_i(data_wen_i[1]), - .data_ID0_i(data_ID_i[0]), - .data_ID1_i(data_ID_i[1]), - .data_be0_i(data_be_i[0]), - .data_be1_i(data_be_i[1]), + .data_wdata0_i ( data_wdata_i[0] ), + .data_wdata1_i ( data_wdata_i[1] ), + .data_add0_i ( data_add_i [0] ), + .data_add1_i ( data_add_i [1] ), + .data_req0_i ( data_req_i [0] ), + .data_req1_i ( data_req_i [1] ), + .data_wen0_i ( data_wen_i [0] ), + .data_wen1_i ( data_wen_i [1] ), + .data_ID0_i ( data_ID_i [0] ), + .data_ID1_i ( data_ID_i [1] ), + .data_be0_i ( data_be_i [0] ), + .data_be1_i ( data_be_i [1] ), `ifdef GNT_BASED_FC - .data_gnt0_o(data_gnt_o[0]), - .data_gnt1_o(data_gnt_o[1]), + .data_gnt0_o ( data_gnt_o [0] ), + .data_gnt1_o ( data_gnt_o [1] ), `else - .data_stall0_o(data_stall_o[0]), - .data_stall1_o(data_stall_o[1]), + .data_stall0_o ( data_stall_o[0] ), + .data_stall1_o ( data_stall_o[1] ), `endif // RIGTH SIDE" - .data_wdata_o(data_wdata_o), - .data_add_o(data_add_o), - .data_req_o(data_req_o), - .data_wen_o(data_wen_o), - .data_ID_o(data_ID_o), - .data_be_o(data_be_o), + .data_wdata_o ( data_wdata_o ), + .data_add_o ( data_add_o ), + .data_req_o ( data_req_o ), + .data_wen_o ( data_wen_o ), + .data_ID_o ( data_ID_o ), + .data_be_o ( data_be_o ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_i) + .data_gnt_i ( data_gnt_i ) `else - .data_stall_i(data_stall_i) + .data_stall_i ( data_stall_i ) `endif ); end // END OF MASTER == 2 @@ -146,16 +147,16 @@ module ArbitrationTree_PE //// ---------------------------------------------------------------------- //// //// ------- REQ ARBITRATION TREE WIRES ----------- //// //// ---------------------------------------------------------------------- //// - logic [DATA_WIDTH-1:0] data_wdata_LEVEL[N_WIRE-1:0]; - logic [ADDR_WIDTH-1:0] data_add_LEVEL[N_WIRE-1:0]; - logic data_req_LEVEL[N_WIRE-1:0]; - logic data_wen_LEVEL[N_WIRE-1:0]; - logic [ID_WIDTH-1:0] data_ID_LEVEL[N_WIRE-1:0]; - logic [BE_WIDTH-1:0] data_be_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0][DATA_WIDTH-1:0] data_wdata_LEVEL; + logic [N_WIRE-1:0][ADDR_WIDTH-1:0] data_add_LEVEL; + logic [N_WIRE-1:0] data_req_LEVEL; + logic [N_WIRE-1:0] data_wen_LEVEL; + logic [N_WIRE-1:0][ID_WIDTH-1:0] data_ID_LEVEL; + logic [N_WIRE-1:0][BE_WIDTH-1:0] data_be_LEVEL; `ifdef GNT_BASED_FC - logic data_gnt_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0] data_gnt_LEVEL; `else - logic data_stall_LEVEL[N_WIRE-1:0]; + logic [N_WIRE-1:0] data_stall_LEVEL; `endif for(j=0; j < LOG_MASTER; j++) // Iteration for the number of the stages minus one @@ -173,38 +174,38 @@ module ArbitrationTree_PE ) i_FanInPrimitive_Req_PE ( - .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), + .RR_FLAG ( RR_FLAG[LOG_MASTER-j-1] ), // LEFT SIDE - .data_wdata0_i(data_wdata_LEVEL[2*k]), - .data_wdata1_i(data_wdata_LEVEL[2*k+1]), - .data_add0_i(data_add_LEVEL[2*k]), - .data_add1_i(data_add_LEVEL[2*k+1]), - .data_req0_i(data_req_LEVEL[2*k]), - .data_req1_i(data_req_LEVEL[2*k+1]), - .data_wen0_i(data_wen_LEVEL[2*k]), - .data_wen1_i(data_wen_LEVEL[2*k+1]), - .data_ID0_i(data_ID_LEVEL[2*k]), - .data_ID1_i(data_ID_LEVEL[2*k+1]), - .data_be0_i(data_be_LEVEL[2*k]), - .data_be1_i(data_be_LEVEL[2*k+1]), + .data_wdata0_i ( data_wdata_LEVEL[2*k] ), + .data_wdata1_i ( data_wdata_LEVEL[2*k+1] ), + .data_add0_i ( data_add_LEVEL [2*k] ), + .data_add1_i ( data_add_LEVEL [2*k+1] ), + .data_req0_i ( data_req_LEVEL [2*k] ), + .data_req1_i ( data_req_LEVEL [2*k+1] ), + .data_wen0_i ( data_wen_LEVEL [2*k] ), + .data_wen1_i ( data_wen_LEVEL [2*k+1] ), + .data_ID0_i ( data_ID_LEVEL [2*k] ), + .data_ID1_i ( data_ID_LEVEL [2*k+1] ), + .data_be0_i ( data_be_LEVEL [2*k] ), + .data_be1_i ( data_be_LEVEL [2*k+1] ), `ifdef GNT_BASED_FC - .data_gnt0_o(data_gnt_LEVEL[2*k]), - .data_gnt1_o(data_gnt_LEVEL[2*k+1]), + .data_gnt0_o ( data_gnt_LEVEL [2*k] ), + .data_gnt1_o ( data_gnt_LEVEL [2*k+1] ), `else - .data_stall0_o(data_stall_LEVEL[2*k]), - .data_stall1_o(data_stall_LEVEL[2*k+1]), + .data_stall0_o ( data_stall_LEVEL[2*k] ), + .data_stall1_o ( data_stall_LEVEL[2*k+1] ), `endif // RIGTH SIDE - .data_wdata_o(data_wdata_o), - .data_add_o(data_add_o), - .data_req_o(data_req_o), - .data_wen_o(data_wen_o), - .data_ID_o(data_ID_o), - .data_be_o(data_be_o), + .data_wdata_o ( data_wdata_o ), + .data_add_o ( data_add_o ), + .data_req_o ( data_req_o ), + .data_wen_o ( data_wen_o ), + .data_ID_o ( data_ID_o ), + .data_be_o ( data_be_o ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_i) + .data_gnt_i ( data_gnt_i ) `else - .data_stall_i(data_stall_i) + .data_stall_i ( data_stall_i ) `endif ); end @@ -221,37 +222,37 @@ module ArbitrationTree_PE ( .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), // LEFT SIDE - .data_wdata0_i (data_wdata_LEVEL[((2**j)*2-2) + 2*k]), - .data_wdata1_i (data_wdata_LEVEL[((2**j)*2-2) + 2*k +1]), - .data_add0_i (data_add_LEVEL[((2**j)*2-2) + 2*k]), - .data_add1_i (data_add_LEVEL[((2**j)*2-2) + 2*k+1]), - .data_req0_i (data_req_LEVEL[((2**j)*2-2) + 2*k]), - .data_req1_i (data_req_LEVEL[((2**j)*2-2) + 2*k+1]), - .data_wen0_i (data_wen_LEVEL[((2**j)*2-2) + 2*k]), - .data_wen1_i (data_wen_LEVEL[((2**j)*2-2) + 2*k+1]), - .data_ID0_i (data_ID_LEVEL[((2**j)*2-2) + 2*k]), - .data_ID1_i (data_ID_LEVEL[((2**j)*2-2) + 2*k+1]), - .data_be0_i (data_be_LEVEL[((2**j)*2-2) + 2*k]), - .data_be1_i (data_be_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_wdata0_i (data_wdata_LEVEL [((2**j)*2-2) + 2*k] ), + .data_wdata1_i (data_wdata_LEVEL [((2**j)*2-2) + 2*k +1] ), + .data_add0_i (data_add_LEVEL [((2**j)*2-2) + 2*k] ), + .data_add1_i (data_add_LEVEL [((2**j)*2-2) + 2*k+1] ), + .data_req0_i (data_req_LEVEL [((2**j)*2-2) + 2*k] ), + .data_req1_i (data_req_LEVEL [((2**j)*2-2) + 2*k+1] ), + .data_wen0_i (data_wen_LEVEL [((2**j)*2-2) + 2*k] ), + .data_wen1_i (data_wen_LEVEL [((2**j)*2-2) + 2*k+1] ), + .data_ID0_i (data_ID_LEVEL [((2**j)*2-2) + 2*k] ), + .data_ID1_i (data_ID_LEVEL [((2**j)*2-2) + 2*k+1] ), + .data_be0_i (data_be_LEVEL [((2**j)*2-2) + 2*k] ), + .data_be1_i (data_be_LEVEL [((2**j)*2-2) + 2*k+1] ), `ifdef GNT_BASED_FC - .data_gnt0_o (data_gnt_LEVEL[((2**j)*2-2) + 2*k]), - .data_gnt1_o (data_gnt_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_gnt0_o (data_gnt_LEVEL [((2**j)*2-2) + 2*k] ), + .data_gnt1_o (data_gnt_LEVEL [((2**j)*2-2) + 2*k+1] ), `else - .data_stall0_o (data_stall_LEVEL[((2**j)*2-2) + 2*k]), - .data_stall1_o (data_stall_LEVEL[((2**j)*2-2) + 2*k+1]), + .data_stall0_o (data_stall_LEVEL [((2**j)*2-2) + 2*k] ), + .data_stall1_o (data_stall_LEVEL [((2**j)*2-2) + 2*k+1] ), `endif // RIGTH SIDE - .data_wdata_o(data_wdata_LEVEL[((2**(j-1))*2-2) + k]), - .data_add_o(data_add_LEVEL[((2**(j-1))*2-2) + k]), - .data_req_o(data_req_LEVEL[((2**(j-1))*2-2) + k]), - .data_wen_o(data_wen_LEVEL[((2**(j-1))*2-2) + k]), - .data_ID_o(data_ID_LEVEL[((2**(j-1))*2-2) + k]), - .data_be_o(data_be_LEVEL[((2**(j-1))*2-2) + k]), + .data_wdata_o (data_wdata_LEVEL [((2**(j-1))*2-2) + k] ), + .data_add_o (data_add_LEVEL [((2**(j-1))*2-2) + k] ), + .data_req_o (data_req_LEVEL [((2**(j-1))*2-2) + k] ), + .data_wen_o (data_wen_LEVEL [((2**(j-1))*2-2) + k] ), + .data_ID_o (data_ID_LEVEL [((2**(j-1))*2-2) + k] ), + .data_be_o (data_be_LEVEL [((2**(j-1))*2-2) + k] ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_LEVEL[((2**(j-1))*2-2) + k]) + .data_gnt_i (data_gnt_LEVEL [((2**(j-1))*2-2) + k] ) `else - .data_stall_i(data_stall_LEVEL[((2**(j-1))*2-2) + k]) + .data_stall_i (data_stall_LEVEL [((2**(j-1))*2-2) + k] ) `endif ); end // END of MIDDLE LEVELS Nodes @@ -268,37 +269,37 @@ module ArbitrationTree_PE ( .RR_FLAG(RR_FLAG[LOG_MASTER-j-1]), // LEFT SIDE - .data_wdata0_i(data_wdata_i[2*k]), - .data_wdata1_i(data_wdata_i[2*k+1]), - .data_add0_i(data_add_i[2*k]), - .data_add1_i(data_add_i[2*k+1]), - .data_req0_i(data_req_i[2*k]), - .data_req1_i(data_req_i[2*k+1]), - .data_wen0_i(data_wen_i[2*k]), - .data_wen1_i(data_wen_i[2*k+1]), - .data_ID0_i(data_ID_i[2*k]), - .data_ID1_i(data_ID_i[2*k+1]), - .data_be0_i(data_be_i[2*k]), - .data_be1_i(data_be_i[2*k+1]), + .data_wdata0_i ( data_wdata_i [2*k] ), + .data_wdata1_i ( data_wdata_i [2*k+1] ), + .data_add0_i ( data_add_i [2*k] ), + .data_add1_i ( data_add_i [2*k+1] ), + .data_req0_i ( data_req_i [2*k] ), + .data_req1_i ( data_req_i [2*k+1] ), + .data_wen0_i ( data_wen_i [2*k] ), + .data_wen1_i ( data_wen_i [2*k+1] ), + .data_ID0_i ( data_ID_i [2*k] ), + .data_ID1_i ( data_ID_i [2*k+1] ), + .data_be0_i ( data_be_i [2*k] ), + .data_be1_i ( data_be_i [2*k+1] ), `ifdef GNT_BASED_FC - .data_gnt0_o(data_gnt_o[2*k]), - .data_gnt1_o(data_gnt_o[2*k+1]), + .data_gnt0_o ( data_gnt_o [2*k] ), + .data_gnt1_o ( data_gnt_o [2*k+1] ), `else - .data_stall0_o(data_stall_o[2*k]), - .data_stall1_o(data_stall_o[2*k+1]), + .data_stall0_o ( data_stall_o [2*k] ), + .data_stall1_o ( data_stall_o [2*k+1] ), `endif // RIGTH SIDE - .data_wdata_o(data_wdata_LEVEL[((2**(j-1))*2-2) + k]), - .data_add_o(data_add_LEVEL[((2**(j-1))*2-2) + k]), - .data_req_o(data_req_LEVEL[((2**(j-1))*2-2) + k]), - .data_wen_o(data_wen_LEVEL[((2**(j-1))*2-2) + k]), - .data_ID_o(data_ID_LEVEL[((2**(j-1))*2-2) + k]), - .data_be_o(data_be_LEVEL[((2**(j-1))*2-2) + k]), + .data_wdata_o ( data_wdata_LEVEL [((2**(j-1))*2-2) + k] ), + .data_add_o ( data_add_LEVEL [((2**(j-1))*2-2) + k] ), + .data_req_o ( data_req_LEVEL [((2**(j-1))*2-2) + k] ), + .data_wen_o ( data_wen_LEVEL [((2**(j-1))*2-2) + k] ), + .data_ID_o ( data_ID_LEVEL [((2**(j-1))*2-2) + k] ), + .data_be_o ( data_be_LEVEL [((2**(j-1))*2-2) + k] ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_LEVEL[((2**(j-1))*2-2) + k]) + .data_gnt_i ( data_gnt_LEVEL [((2**(j-1))*2-2) + k] ) `else - .data_stall_i(data_stall_LEVEL[((2**(j-1))*2-2) + k]) + .data_stall_i ( data_stall_LEVEL [((2**(j-1))*2-2) + k] ) `endif ); end // End of FIRST LEVEL Nodes (LEAF) @@ -312,19 +313,19 @@ module ArbitrationTree_PE //COUNTER USED TO SWITCH PERIODICALLY THE PRIORITY FLAG" RR_Flag_Req_PE #( - .WIDTH(LOG_MASTER), - .MAX_COUNT(MAX_COUNT) + .WIDTH ( LOG_MASTER), + .MAX_COUNT ( MAX_COUNT) ) RR_REQ ( - .clk(clk), - .rst_n(rst_n), - .RR_FLAG_o(RR_FLAG), - .data_req_i(data_req_o), + .clk ( clk ), + .rst_n ( rst_n ), + .RR_FLAG_o ( RR_FLAG ), + .data_req_i ( data_req_o ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_i) + .data_gnt_i ( data_gnt_i ) `else - .data_stall_i(data_stall_i) + .data_stall_i ( data_stall_i ) `endif ); diff --git a/rtl/peripheral_interco/RequestBlock2CH_PE.sv b/rtl/peripheral_interco/RequestBlock2CH_PE.sv index 36d25ff..5c68aa7 100644 --- a/rtl/peripheral_interco/RequestBlock2CH_PE.sv +++ b/rtl/peripheral_interco/RequestBlock2CH_PE.sv @@ -292,12 +292,12 @@ module RequestBlock2CH_PE begin : CH0_ARB_TREE ArbitrationTree_PE #( - .ADDR_WIDTH ( ADDR_WIDTH ), - .ID_WIDTH ( ID_WIDTH ), - .N_MASTER ( N_CH0 ), - .DATA_WIDTH ( DATA_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .MAX_COUNT ( N_CH0 - 1 ) + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .N_MASTER ( 2**$clog2(N_CH0) ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .MAX_COUNT ( N_CH0 - 1 ) ) i_ArbitrationTree_PE ( @@ -334,12 +334,12 @@ module RequestBlock2CH_PE begin : CH1_ARB_TREE ArbitrationTree_PE #( - .ADDR_WIDTH ( ADDR_WIDTH ), - .ID_WIDTH ( ID_WIDTH ), - .N_MASTER ( N_CH1 ), - .DATA_WIDTH ( DATA_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .MAX_COUNT ( N_CH1 - 1 ) + .ADDR_WIDTH ( ADDR_WIDTH ), + .ID_WIDTH ( ID_WIDTH ), + .N_MASTER ( 2**$clog2(N_CH1) ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .MAX_COUNT ( N_CH1 - 1 ) ) i_ArbitrationTree_PE ( diff --git a/rtl/peripheral_interco/ResponseBlock_PE.sv b/rtl/peripheral_interco/ResponseBlock_PE.sv index 03914bd..89cdb11 100644 --- a/rtl/peripheral_interco/ResponseBlock_PE.sv +++ b/rtl/peripheral_interco/ResponseBlock_PE.sv @@ -32,6 +32,7 @@ // Revision v0.1 02/07/2011 - File Created // // v0.2 15/08/2012 - Improved the Interface Structure, // // Changed the routing mechanism // +// v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE // // // // Additional Comments: // // // @@ -95,19 +96,62 @@ module ResponseBlock_PE ); + // Response channel exploded to powr of 2 inputs + logic [2**$clog2(N_SLAVE)-1:0] data_r_valid_int; + logic [2**$clog2(N_SLAVE)-1:0][DATA_WIDTH-1:0] data_r_rdata_int; + logic [2**$clog2(N_SLAVE)-1:0] data_r_opc_int; + + + + genvar i; + + generate + if(2**$clog2(N_SLAVE) == N_SLAVE) + begin : EXACT_POW2 + + for(i=0;i ( j == N_SLAVE - 1 ) @@ -155,16 +157,16 @@ module ResponseTree_PE i_FanInPrimitive_PE_Resp ( // RIGTH SIDE - .data_r_rdata0_i(data_r_rdata_i[2*k]), - .data_r_rdata1_i(data_r_rdata_i[2*k+1]), - .data_r_valid0_i(data_r_valid_i[2*k]), - .data_r_valid1_i(data_r_valid_i[2*k+1]), - .data_r_opc0_i(data_r_opc_i[2*k]), - .data_r_opc1_i(data_r_opc_i[2*k+1]), + .data_r_rdata0_i ( data_r_rdata_i[2*k] ), + .data_r_rdata1_i ( data_r_rdata_i[2*k+1] ), + .data_r_valid0_i ( data_r_valid_i[2*k] ), + .data_r_valid1_i ( data_r_valid_i[2*k+1] ), + .data_r_opc0_i ( data_r_opc_i [2*k] ), + .data_r_opc1_i ( data_r_opc_i [2*k+1] ), // LEFT SIDE - .data_r_rdata_o(data_r_rdata_LEVEL[((2**(j-1))*2-2) + k]), - .data_r_valid_o(data_r_valid_LEVEL[((2**(j-1))*2-2) + k]), - .data_r_opc_o(data_r_opc_LEVEL[((2**(j-1))*2-2) + k]) + .data_r_rdata_o ( data_r_rdata_LEVEL [((2**(j-1))*2-2) + k] ), + .data_r_valid_o ( data_r_valid_LEVEL [((2**(j-1))*2-2) + k] ), + .data_r_opc_o ( data_r_opc_LEVEL [((2**(j-1))*2-2) + k] ) ); end // End of FIRST LEVEL Nodes (LEAF) end diff --git a/rtl/peripheral_interco/XBAR_PE.sv b/rtl/peripheral_interco/XBAR_PE.sv index 89f9765..ff3c12b 100644 --- a/rtl/peripheral_interco/XBAR_PE.sv +++ b/rtl/peripheral_interco/XBAR_PE.sv @@ -33,6 +33,7 @@ // v0.2 15/08/2012 - Improved the Interface Structure, // // Changed the routing mechanism // // v0.3 09/03/2015 - Improved identation // +// v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE // // // // Additional Comments: // // // @@ -45,12 +46,12 @@ module XBAR_PE #( - parameter N_CH0 = 16, //--> CH0 - parameter N_CH1 = 0, //--> CH1 - parameter N_SLAVE = 16, + parameter N_CH0 = 8, //--> CH0 + parameter N_CH1 = 1, //--> CH1 + parameter N_SLAVE = 9, parameter ID_WIDTH = N_CH0+N_CH1, - parameter PE_LSB = 2, + parameter PE_LSB = 0, parameter PE_MSB = 31, parameter LOG_CLUSTER = 5, @@ -58,8 +59,8 @@ module XBAR_PE parameter DATA_WIDTH = 32, parameter BE_WIDTH = DATA_WIDTH/8, - parameter PE_ROUTING_LSB = 16, - parameter PE_ROUTING_MSB = 19, + parameter PE_ROUTING_LSB = 10, + parameter PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(N_SLAVE)-1, parameter CLUSTER_ALIAS_BASE = 12'h000, @@ -157,60 +158,60 @@ module XBAR_PE begin : CH0_CH1 RequestBlock2CH_PE #( - .ADDR_WIDTH(ADDR_PE_WIDTH), - .N_CH0(N_CH0), - .N_CH1(N_CH1), - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .BE_WIDTH(DATA_WIDTH/8) + .ADDR_WIDTH ( ADDR_PE_WIDTH ), + .N_CH0 ( N_CH0 ), + .N_CH1 ( N_CH1 ), + .ID_WIDTH ( ID_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( DATA_WIDTH/8 ) ) i_RequestBlock2CH_PE ( // CHANNEL CH0 --> (example: Used for cores) - .data_req_CH0_i(data_req_to_MEM[j][N_CH0-1:0]), - .data_add_CH0_i(data_add[N_CH0-1:0]), - .data_wen_CH0_i(data_wen_i[N_CH0-1:0]), - .data_wdata_CH0_i(data_wdata_i[N_CH0-1:0]), - .data_be_CH0_i(data_be_i[N_CH0-1:0]), - .data_ID_CH0_i(data_ID[N_CH0-1:0]), + .data_req_CH0_i ( data_req_to_MEM[j] [N_CH0-1:0] ), + .data_add_CH0_i ( data_add [N_CH0-1:0] ), + .data_wen_CH0_i ( data_wen_i [N_CH0-1:0] ), + .data_wdata_CH0_i ( data_wdata_i [N_CH0-1:0] ), + .data_be_CH0_i ( data_be_i [N_CH0-1:0] ), + .data_ID_CH0_i ( data_ID [N_CH0-1:0] ), `ifdef GNT_BASED_FC - .data_gnt_CH0_o(data_gnt_from_MEM[j][N_CH0-1:0]), + .data_gnt_CH0_o ( data_gnt_from_MEM[j] [N_CH0-1:0] ), `else - .data_stall_CH0_o(data_stall_from_MEM[j][N_CH0-1:0]), + .data_stall_CH0_o ( data_stall_from_MEM[j][N_CH0-1:0] ), `endif - // CHANNEL CH1 --> (example: Used for DMAs) - .data_req_CH1_i(data_req_to_MEM[j][N_CH1+N_CH0-1:N_CH0]), - .data_add_CH1_i(data_add[N_CH1+N_CH0-1:N_CH0]), - .data_wen_CH1_i(data_wen_i[N_CH1+N_CH0-1:N_CH0]), - .data_wdata_CH1_i(data_wdata_i[N_CH1+N_CH0-1:N_CH0]), - .data_be_CH1_i(data_be_i[N_CH1+N_CH0-1:N_CH0]), - .data_ID_CH1_i(data_ID[N_CH1+N_CH0-1:N_CH0]), + // CHANNEL CH1 --> ( example: Used for DMAs ) + .data_req_CH1_i ( data_req_to_MEM[j] [N_CH1+N_CH0-1:N_CH0] ), + .data_add_CH1_i ( data_add [N_CH1+N_CH0-1:N_CH0] ), + .data_wen_CH1_i ( data_wen_i [N_CH1+N_CH0-1:N_CH0] ), + .data_wdata_CH1_i ( data_wdata_i [N_CH1+N_CH0-1:N_CH0] ), + .data_be_CH1_i ( data_be_i [N_CH1+N_CH0-1:N_CH0] ), + .data_ID_CH1_i ( data_ID [N_CH1+N_CH0-1:N_CH0] ), `ifdef GNT_BASED_FC - .data_gnt_CH1_o(data_gnt_from_MEM[j][N_CH1+N_CH0-1:N_CH0]), + .data_gnt_CH1_o ( data_gnt_from_MEM[j] [N_CH1+N_CH0-1:N_CH0] ), `else - .data_stall_CH1_o(data_stall_from_MEM[j][N_CH1+N_CH0-1:N_CH0]), + .data_stall_CH1_o ( data_stall_from_MEM[j][N_CH1+N_CH0-1:N_CH0] ), `endif // ----------------- MEMORY ------------------- // ---------------- RequestBlock OUTPUT (Connected to MEMORY) ---------------- - .data_req_o(data_req_o[j]), - .data_add_o(data_add_o[j]), - .data_wen_o(data_wen_o[j]), - .data_wdata_o(data_wdata_o[j]), - .data_be_o(data_be_o[j]), - .data_ID_o(data_ID_o[j]), + .data_req_o ( data_req_o[j] ), + .data_add_o ( data_add_o[j] ), + .data_wen_o ( data_wen_o[j] ), + .data_wdata_o ( data_wdata_o[j] ), + .data_be_o ( data_be_o[j] ), + .data_ID_o ( data_ID_o[j] ), `ifdef GNT_BASED_FC - .data_gnt_i(data_gnt_i[j]), + .data_gnt_i ( data_gnt_i[j] ), `else - .data_stall_i(data_stall_i[j]), + .data_stall_i ( data_stall_i[j] ), `endif - .data_r_valid_i(data_r_valid_i[j]), - .data_r_ID_i(data_r_ID_i[j]), + .data_r_valid_i ( data_r_valid_i[j] ), + .data_r_ID_i ( data_r_ID_i[j] ), // GEN VALID_SIGNALS in the response path - .data_r_valid_CH0_o(data_r_valid_from_MEM[j][N_CH0-1:0]), // N_CH0 Bit - .data_r_valid_CH1_o(data_r_valid_from_MEM[j][N_CH0+N_CH1-1:N_CH0]), // N_CH1 Bit - .clk(clk), - .rst_n(rst_n) + .data_r_valid_CH0_o ( data_r_valid_from_MEM[j][N_CH0-1:0] ), // N_CH0 Bit + .data_r_valid_CH1_o ( data_r_valid_from_MEM[j][N_CH0+N_CH1-1:N_CH0] ), // N_CH1 Bit + .clk ( clk ), + .rst_n ( rst_n ) ); end else From 4ff19495103c99d9dbc0c22497da1a117d01a7da Mon Sep 17 00:00:00 2001 From: Florent Rotenberg Date: Mon, 9 Sep 2019 12:00:55 +0200 Subject: [PATCH 2/2] Add parameters in IP yml description for JG EDA tool --- src_files.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/src_files.yml b/src_files.yml index de2be17..dd33995 100644 --- a/src_files.yml +++ b/src_files.yml @@ -19,6 +19,7 @@ low_latency_interco: - rtl/low_latency_interco/TCDM_PIPE_RESP.sv - rtl/low_latency_interco/grant_mask.sv - rtl/low_latency_interco/priority_Flag_Req.sv + peripheral_interco: incdirs: [ rtl/peripheral_interco,