From 9242841e647f81447c41e0ef018eff90e2e2879d Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Feb 2022 17:23:23 +0100 Subject: [PATCH 1/4] Added condition for LIC topology within assertion. --- rtl/tcdm_interconnect/tcdm_interconnect.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/tcdm_interconnect/tcdm_interconnect.sv b/rtl/tcdm_interconnect/tcdm_interconnect.sv index 0b4025f..d0cc132 100644 --- a/rtl/tcdm_interconnect/tcdm_interconnect.sv +++ b/rtl/tcdm_interconnect/tcdm_interconnect.sv @@ -315,7 +315,7 @@ end initial begin assert(AddrMemWidth+NumOutLog2 <= AddrWidth) else $fatal(1,"Address not wide enough to accomodate the requested TCDM configuration."); - assert(NumOut >= NumIn) else + assert( (NumOut >= NumIn) | (Topology == tcdm_interconnect_pkg::LIC) ) else $fatal(1,"NumOut < NumIn is not supported."); end // pragma translate_on From ba37ace21426f88506ed19d65f4b8a1d41841e48 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Feb 2022 17:30:55 +0100 Subject: [PATCH 2/4] Modified support for 64-bit datawidth to avoid datawidth warnings. --- rtl/tcdm_interconnect/amo_shim.sv | 43 +++++++++++++++++-------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/rtl/tcdm_interconnect/amo_shim.sv b/rtl/tcdm_interconnect/amo_shim.sv index 6ef262d..e7f0eb1 100644 --- a/rtl/tcdm_interconnect/amo_shim.sv +++ b/rtl/tcdm_interconnect/amo_shim.sv @@ -51,20 +51,32 @@ module amo_shim #( logic [AddrMemWidth-1:0] addr_q; logic [31:0] amo_operand_a; - logic [31:0] amo_operand_b_q; + logic [31:0] amo_operand_b_d, + amo_operand_b_q; // requested amo should be performed on upper 32 bit - logic upper_word_q; - logic [31:0] swap_value_q; - logic [31:0] amo_result; // result of atomic memory operation + logic upper_word_d, + upper_word_q; + logic [31:0] swap_value_d, + swap_value_q; + logic [31:0] amo_res, + amo_result; // result of atomic memory operation always_comb begin - if (DataWidth == 64 && upper_word_q) begin - amo_operand_a = out_rdata_i[63:32]; + if (DataWidth == 64) begin + amo_operand_a = (upper_word_q) ? out_rdata_i[DataWidth-1:DataWidth-32] : out_rdata_i[31:0]; + amo_operand_b_d = (!in_be_i[0]) ? in_wdata_i[DataWidth-1:DataWidth-32] : in_wdata_i[31:0]; + upper_word_d = in_be_i[4]; + swap_value_d = in_wdata_i[DataWidth-1:DataWidth-1]; + amo_res = out_rdata_i[DataWidth-1:DataWidth-32]; end else begin - amo_operand_a = out_rdata_i[31:0]; + amo_operand_a = out_rdata_i[31:0]; + amo_operand_b_d = in_wdata_i[31:0]; + upper_word_d = '0; + swap_value_d = '0; + amo_res = out_rdata_i[31:0]; end end - + always_comb begin // feed-through out_req_o = in_req_i; @@ -125,16 +137,9 @@ module amo_shim #( if (load_amo) begin amo_op_q <= amo_op_t'(in_amo_i); addr_q <= in_add_i; - if (DataWidth == 64) begin - if (!in_be_i[0]) begin - amo_operand_b_q <= in_wdata_i[63:32]; - end - upper_word_q <= in_be_i[4]; - // swap value is located in the upper word - swap_value_q <= in_wdata_i[63:32]; - end else begin - amo_operand_b_q <= in_wdata_i[31:0]; - end + amo_operand_b_q <= amo_operand_b_d; + upper_word_q <= upper_word_d; + swap_value_q <= swap_value_d; state_q <= DoAMO; end else begin amo_op_q <= AMONone; @@ -191,7 +196,7 @@ module amo_shim #( amo_result = swap_value_q; // values are not euqal -> don't update end else begin - amo_result = upper_word_q ? out_rdata_i[63:32] : out_rdata_i[31:0]; + amo_result = amo_res; end `ifndef TARGET_SYNTHESIS end else begin From b265a44a23eb39c567932aceef16539b52c4b668 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Feb 2022 19:05:41 +0100 Subject: [PATCH 3/4] Comments on modified code and bitwidth fix. --- rtl/tcdm_interconnect/amo_shim.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/tcdm_interconnect/amo_shim.sv b/rtl/tcdm_interconnect/amo_shim.sv index e7f0eb1..965e8b2 100644 --- a/rtl/tcdm_interconnect/amo_shim.sv +++ b/rtl/tcdm_interconnect/amo_shim.sv @@ -61,14 +61,14 @@ module amo_shim #( logic [31:0] amo_res, amo_result; // result of atomic memory operation - always_comb begin + always_comb begin // Generate parametric code for 64-bit datawidth if (DataWidth == 64) begin amo_operand_a = (upper_word_q) ? out_rdata_i[DataWidth-1:DataWidth-32] : out_rdata_i[31:0]; amo_operand_b_d = (!in_be_i[0]) ? in_wdata_i[DataWidth-1:DataWidth-32] : in_wdata_i[31:0]; upper_word_d = in_be_i[4]; - swap_value_d = in_wdata_i[DataWidth-1:DataWidth-1]; + swap_value_d = in_wdata_i[DataWidth-1:DataWidth-32]; amo_res = out_rdata_i[DataWidth-1:DataWidth-32]; - end else begin + end else begin // Standard 32-bit datawidth implementation amo_operand_a = out_rdata_i[31:0]; amo_operand_b_d = in_wdata_i[31:0]; upper_word_d = '0; From de2ef4f92684fcf00b5ef0b5c9c8542e31b1e800 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 16 Feb 2022 11:18:28 +0100 Subject: [PATCH 4/4] Fixed amo_result assignment. --- rtl/tcdm_interconnect/amo_shim.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/tcdm_interconnect/amo_shim.sv b/rtl/tcdm_interconnect/amo_shim.sv index 965e8b2..5188858 100644 --- a/rtl/tcdm_interconnect/amo_shim.sv +++ b/rtl/tcdm_interconnect/amo_shim.sv @@ -61,13 +61,13 @@ module amo_shim #( logic [31:0] amo_res, amo_result; // result of atomic memory operation - always_comb begin // Generate parametric code for 64-bit datawidth + always_comb begin // Generate parametric code for 64-bit datawidth (only 32-bit and 64-bit supported) if (DataWidth == 64) begin amo_operand_a = (upper_word_q) ? out_rdata_i[DataWidth-1:DataWidth-32] : out_rdata_i[31:0]; amo_operand_b_d = (!in_be_i[0]) ? in_wdata_i[DataWidth-1:DataWidth-32] : in_wdata_i[31:0]; upper_word_d = in_be_i[4]; swap_value_d = in_wdata_i[DataWidth-1:DataWidth-32]; - amo_res = out_rdata_i[DataWidth-1:DataWidth-32]; + amo_res = (upper_word_q) ? out_rdata_i[DataWidth-1:DataWidth-32] : out_rdata_i[31:0]; end else begin // Standard 32-bit datawidth implementation amo_operand_a = out_rdata_i[31:0]; amo_operand_b_d = in_wdata_i[31:0];