I do not see a top level parameter to specify the number of interrupt levels. This would be important, as most designs will only need a few, not 256. I would expect between 3 and 5 level bits to be used, with the rest fixed to one.
The CLIC specification defines a standard parameter, but that definition is currently being reworked. Thus, I would suggest waiting on riscv/riscv-fast-interrupt#331 to complete